DE69525496D1 - Leiterrahmen und Herstellungsverfahren - Google Patents

Leiterrahmen und Herstellungsverfahren

Info

Publication number
DE69525496D1
DE69525496D1 DE69525496T DE69525496T DE69525496D1 DE 69525496 D1 DE69525496 D1 DE 69525496D1 DE 69525496 T DE69525496 T DE 69525496T DE 69525496 T DE69525496 T DE 69525496T DE 69525496 D1 DE69525496 D1 DE 69525496D1
Authority
DE
Germany
Prior art keywords
manufacturing process
lead frame
lead
frame
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69525496T
Other languages
English (en)
Other versions
DE69525496T2 (de
Inventor
Kenichiro Tsuchiya
Masahiro Iwabuchi
Toshiaki Ishizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Publication of DE69525496D1 publication Critical patent/DE69525496D1/de
Application granted granted Critical
Publication of DE69525496T2 publication Critical patent/DE69525496T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
DE69525496T 1994-08-11 1995-08-10 Leiterrahmen und Herstellungsverfahren Expired - Fee Related DE69525496T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18925094A JP3257904B2 (ja) 1994-08-11 1994-08-11 リードフレームとその製造方法

Publications (2)

Publication Number Publication Date
DE69525496D1 true DE69525496D1 (de) 2002-03-28
DE69525496T2 DE69525496T2 (de) 2002-08-14

Family

ID=16238152

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69525496T Expired - Fee Related DE69525496T2 (de) 1994-08-11 1995-08-10 Leiterrahmen und Herstellungsverfahren

Country Status (5)

Country Link
US (1) US5633205A (de)
EP (1) EP0701280B1 (de)
JP (1) JP3257904B2 (de)
KR (1) KR100202286B1 (de)
DE (1) DE69525496T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789280A (en) * 1994-10-11 1998-08-04 Motorola, Inc. Leadframe having secured outer leads, semiconductor device using the leadframe and method of making them
US5691242A (en) * 1996-02-26 1997-11-25 Motorola, Inc. Method for making an electronic component having an organic substrate
TW374952B (en) * 1997-03-24 1999-11-21 Seiko Epson Corp Semiconductor device substrate, lead frame, semiconductor device and the manufacturing method, circuit substrate and the electronic machine
NL1011929C2 (nl) * 1999-04-29 2000-10-31 3P Licensing Bv Werkwijze voor het inkapselen van elektronische componenten, in het bijzonder geintegreerde schakelingen.
JP2001320007A (ja) 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
JP4840893B2 (ja) * 2000-05-12 2011-12-21 大日本印刷株式会社 樹脂封止型半導体装置用フレーム
JP2003258183A (ja) * 2002-03-04 2003-09-12 Shinko Electric Ind Co Ltd リードフレームの製造方法
KR100833938B1 (ko) * 2002-03-28 2008-05-30 삼성테크윈 주식회사 반도체 패키지용 리드프레임 및 리드프레임 제조 방법
JP3666594B2 (ja) * 2002-10-17 2005-06-29 ローム株式会社 パッケージ型電子部品におけるリード端子の切断方法
TW200418149A (en) * 2003-03-11 2004-09-16 Siliconware Precision Industries Co Ltd Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same
KR100688835B1 (ko) * 2004-12-24 2007-03-02 삼성전기주식회사 도금 리드선을 포함하는 기판의 가공 방법
JP2009049072A (ja) * 2007-08-15 2009-03-05 Panasonic Corp リードフレーム、半導体装置、リードフレームの製造方法、および半導体装置の製造方法
WO2010036051A2 (en) * 2008-09-25 2010-04-01 Lg Innotek Co., Ltd. Structure and manufacture method for multi-row lead frame and semiconductor package
CN102169867A (zh) * 2011-04-02 2011-08-31 上海凯虹科技电子有限公司 一种引线框架
US20140131086A1 (en) * 2011-09-06 2014-05-15 Texas Instuments Incorporated Lead Frame Strip with Half (1/2) Thickness Pull Out Tab
JP6837314B2 (ja) * 2016-11-01 2021-03-03 旭化成エレクトロニクス株式会社 半導体装置
TWI758227B (zh) * 2021-09-06 2022-03-11 復盛精密工業股份有限公司 封裝導線架的製作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56169338A (en) * 1980-05-30 1981-12-26 Hitachi Ltd Semiconductor device
US4711700A (en) * 1985-07-03 1987-12-08 United Technologies Corporation Method for densifying leadframe conductor spacing
GB2178895B (en) * 1985-08-06 1988-11-23 Gen Electric Co Plc Improved preparation of fragile devices
US4701363A (en) * 1986-01-27 1987-10-20 Olin Corporation Process for manufacturing bumped tape for tape automated bonding and the product produced thereby
JPH02197158A (ja) * 1989-01-26 1990-08-03 Dainippon Printing Co Ltd リードフレームの製造方法
JPH0783081B2 (ja) 1989-02-09 1995-09-06 株式会社三井ハイテック 半導体装置に用いるリードフレームの製造方法
JP2797542B2 (ja) * 1989-11-06 1998-09-17 ソニー株式会社 リードフレームの製造方法
US5253415A (en) * 1990-03-20 1993-10-19 Die Tech, Inc. Method of making an integrated circuit substrate lead assembly
JPH03280563A (ja) * 1990-03-29 1991-12-11 Toppan Printing Co Ltd リードフレームの製造方法
JPH0494156A (ja) * 1990-08-09 1992-03-26 Hitachi Cable Ltd エッチングリードフレームとその製造方法
JP3018542B2 (ja) * 1991-04-03 2000-03-13 セイコーエプソン株式会社 リードフレーム及びその製造方法

Also Published As

Publication number Publication date
EP0701280A3 (de) 1997-03-12
JP3257904B2 (ja) 2002-02-18
EP0701280A2 (de) 1996-03-13
KR960009144A (ko) 1996-03-22
JPH0855948A (ja) 1996-02-27
EP0701280B1 (de) 2002-02-20
KR100202286B1 (ko) 1999-06-15
DE69525496T2 (de) 2002-08-14
US5633205A (en) 1997-05-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee