DE69525558T2 - Methode zur Herstellung eines Dünnfilm-Transistors mit invertierter Struktur - Google Patents

Methode zur Herstellung eines Dünnfilm-Transistors mit invertierter Struktur

Info

Publication number
DE69525558T2
DE69525558T2 DE69525558T DE69525558T DE69525558T2 DE 69525558 T2 DE69525558 T2 DE 69525558T2 DE 69525558 T DE69525558 T DE 69525558T DE 69525558 T DE69525558 T DE 69525558T DE 69525558 T2 DE69525558 T2 DE 69525558T2
Authority
DE
Germany
Prior art keywords
manufacturing
thin film
film transistor
inverted structure
inverted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69525558T
Other languages
English (en)
Other versions
DE69525558D1 (de
Inventor
Shin Koide
Susumi C O Nec Corporation Ohi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69525558D1 publication Critical patent/DE69525558D1/de
Publication of DE69525558T2 publication Critical patent/DE69525558T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
DE69525558T 1994-04-22 1995-04-20 Methode zur Herstellung eines Dünnfilm-Transistors mit invertierter Struktur Expired - Lifetime DE69525558T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8422994 1994-04-22

Publications (2)

Publication Number Publication Date
DE69525558D1 DE69525558D1 (de) 2002-04-04
DE69525558T2 true DE69525558T2 (de) 2002-08-22

Family

ID=13824652

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69525558T Expired - Lifetime DE69525558T2 (de) 1994-04-22 1995-04-20 Methode zur Herstellung eines Dünnfilm-Transistors mit invertierter Struktur

Country Status (5)

Country Link
US (1) US5561074A (de)
EP (1) EP0678907B1 (de)
KR (1) KR0180323B1 (de)
DE (1) DE69525558T2 (de)
TW (1) TW291597B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2833545B2 (ja) * 1995-03-06 1998-12-09 日本電気株式会社 半導体装置の製造方法
JP3082679B2 (ja) * 1996-08-29 2000-08-28 日本電気株式会社 薄膜トランジスタおよびその製造方法
WO1998057506A1 (en) * 1997-06-12 1998-12-17 Northern Telecom Limited Directory service based on geographic location of a mobile telecommunications unit
JP2001308339A (ja) 2000-02-18 2001-11-02 Sharp Corp 薄膜トランジスタ
JP4118484B2 (ja) 2000-03-06 2008-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2001257350A (ja) 2000-03-08 2001-09-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP4700160B2 (ja) 2000-03-13 2011-06-15 株式会社半導体エネルギー研究所 半導体装置
JP4118485B2 (ja) 2000-03-13 2008-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4683688B2 (ja) 2000-03-16 2011-05-18 株式会社半導体エネルギー研究所 液晶表示装置の作製方法
JP4393662B2 (ja) 2000-03-17 2010-01-06 株式会社半導体エネルギー研究所 液晶表示装置の作製方法
JP4785229B2 (ja) 2000-05-09 2011-10-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7071037B2 (en) 2001-03-06 2006-07-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR101576813B1 (ko) * 2007-08-17 2015-12-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
WO2009060922A1 (en) * 2007-11-05 2009-05-14 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and display device having the thin film transistor
TWI535037B (zh) * 2008-11-07 2016-05-21 半導體能源研究所股份有限公司 半導體裝置和其製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61237420A (ja) * 1985-04-13 1986-10-22 Oki Electric Ind Co Ltd P型アモルフアスシリコン薄膜の製造方法
US4882295A (en) * 1985-07-26 1989-11-21 Energy Conversion Devices, Inc. Method of making a double injection field effect transistor
US5270224A (en) * 1988-03-11 1993-12-14 Fujitsu Limited Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit
JPH01241175A (ja) * 1988-03-23 1989-09-26 Seikosha Co Ltd 非晶質シリコン薄膜トランジスタの製造方法
US5053354A (en) * 1988-05-30 1991-10-01 Seikosha Co., Ltd. Method of fabricating a reverse staggered type silicon thin film transistor
JPH01302769A (ja) * 1988-05-30 1989-12-06 Seikosha Co Ltd 逆スタガー型シリコン薄膜トランジスタの製造方法
JPH07114285B2 (ja) * 1988-12-16 1995-12-06 日本電気株式会社 薄膜トランジスタの製造方法
US5109260A (en) * 1989-07-10 1992-04-28 Seikosha Co., Ltd. Silicon thin film transistor and method for producing the same
EP0606114A1 (de) * 1989-08-11 1994-07-13 Seiko Instruments Inc. Verfahren zur Herstellung eines Feldeffekttransistors
DE4192351T (de) * 1990-10-05 1992-10-08
JPH04321275A (ja) * 1991-04-19 1992-11-11 Nec Corp 薄膜トランジスタ
JPH04367277A (ja) * 1991-06-14 1992-12-18 Nec Corp 薄膜トランジスタおよびその製造方法
JPH04367276A (ja) * 1991-06-14 1992-12-18 Nec Corp 薄膜トランジスタおよびその製造方法
JPH0583197A (ja) * 1991-09-21 1993-04-02 Alpine Electron Inc デイジタルオーデイオ装置

Also Published As

Publication number Publication date
EP0678907A2 (de) 1995-10-25
KR950030282A (ko) 1995-11-24
EP0678907A3 (de) 1997-08-20
TW291597B (de) 1996-11-21
KR0180323B1 (ko) 1999-04-15
US5561074A (en) 1996-10-01
EP0678907B1 (de) 2002-02-27
DE69525558D1 (de) 2002-04-04

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC LCD TECHNOLOGIES, LTD., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKYO, JP

R082 Change of representative

Ref document number: 678907

Country of ref document: EP

Representative=s name: MUELLER-BORE & PARTNER PATENTANWAELTE, EUROPEA, DE