DE69527330D1 - Halbleiteranordnung und Herstellungsverfahren - Google Patents

Halbleiteranordnung und Herstellungsverfahren

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Publication number
DE69527330D1
DE69527330D1 DE69527330T DE69527330T DE69527330D1 DE 69527330 D1 DE69527330 D1 DE 69527330D1 DE 69527330 T DE69527330 T DE 69527330T DE 69527330 T DE69527330 T DE 69527330T DE 69527330 D1 DE69527330 D1 DE 69527330D1
Authority
DE
Germany
Prior art keywords
semiconductor device
manufacturing process
manufacturing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69527330T
Other languages
English (en)
Other versions
DE69527330T2 (de
Inventor
Michio Horiuchi
Yoichi Harayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Application granted granted Critical
Publication of DE69527330D1 publication Critical patent/DE69527330D1/de
Publication of DE69527330T2 publication Critical patent/DE69527330T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
DE69527330T 1994-09-08 1995-09-07 Halbleiteranordnung und Herstellungsverfahren Expired - Fee Related DE69527330T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6214428A JPH0878574A (ja) 1994-09-08 1994-09-08 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69527330D1 true DE69527330D1 (de) 2002-08-14
DE69527330T2 DE69527330T2 (de) 2003-03-13

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Publication number Publication date
JPH0878574A (ja) 1996-03-22
DE69527330T2 (de) 2003-03-13
US5602059A (en) 1997-02-11
EP0701278B1 (de) 2002-07-10
EP0701278A3 (de) 1997-03-26
EP0701278A2 (de) 1996-03-13
KR100285117B1 (ko) 2001-03-15
KR100268610B1 (en) 2000-07-14

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