DE69535438D1 - Verfahren zur Planierung von Dielektrika in Halbleitervorrichtungen - Google Patents

Verfahren zur Planierung von Dielektrika in Halbleitervorrichtungen

Info

Publication number
DE69535438D1
DE69535438D1 DE69535438T DE69535438T DE69535438D1 DE 69535438 D1 DE69535438 D1 DE 69535438D1 DE 69535438 T DE69535438 T DE 69535438T DE 69535438 T DE69535438 T DE 69535438T DE 69535438 D1 DE69535438 D1 DE 69535438D1
Authority
DE
Germany
Prior art keywords
semiconductor devices
planarizing
dielectrics
planarizing dielectrics
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69535438T
Other languages
English (en)
Other versions
DE69535438T2 (de
Inventor
Manoj K Jain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69535438D1 publication Critical patent/DE69535438D1/de
Publication of DE69535438T2 publication Critical patent/DE69535438T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
DE69535438T 1994-08-17 1995-08-09 Verfahren zur Planierung von Dielektrika in Halbleitervorrichtungen Expired - Lifetime DE69535438T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US291636 1994-08-17
US08/291,636 US5494854A (en) 1994-08-17 1994-08-17 Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films

Publications (2)

Publication Number Publication Date
DE69535438D1 true DE69535438D1 (de) 2007-05-10
DE69535438T2 DE69535438T2 (de) 2007-12-13

Family

ID=23121136

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69535438T Expired - Lifetime DE69535438T2 (de) 1994-08-17 1995-08-09 Verfahren zur Planierung von Dielektrika in Halbleitervorrichtungen

Country Status (4)

Country Link
US (2) US5494854A (de)
EP (1) EP0697722B1 (de)
JP (1) JP4106101B2 (de)
DE (1) DE69535438T2 (de)

Families Citing this family (157)

* Cited by examiner, † Cited by third party
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EP0697722A2 (de) 1996-02-21
JPH0869999A (ja) 1996-03-12
EP0697722A3 (de) 1997-07-09
US5494854A (en) 1996-02-27
DE69535438T2 (de) 2007-12-13
JP4106101B2 (ja) 2008-06-25
US5621241A (en) 1997-04-15
EP0697722B1 (de) 2007-03-28

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