DE69621294T2 - Halbleiterspeicheranordnungen - Google Patents

Halbleiterspeicheranordnungen

Info

Publication number
DE69621294T2
DE69621294T2 DE69621294T DE69621294T DE69621294T2 DE 69621294 T2 DE69621294 T2 DE 69621294T2 DE 69621294 T DE69621294 T DE 69621294T DE 69621294 T DE69621294 T DE 69621294T DE 69621294 T2 DE69621294 T2 DE 69621294T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory devices
devices
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69621294T
Other languages
English (en)
Other versions
DE69621294D1 (de
Inventor
Hiroshige Hirano
Toshiyuki Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69621294D1 publication Critical patent/DE69621294D1/de
Application granted granted Critical
Publication of DE69621294T2 publication Critical patent/DE69621294T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
DE69621294T 1995-08-02 1996-08-01 Halbleiterspeicheranordnungen Expired - Lifetime DE69621294T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19735295 1995-08-02

Publications (2)

Publication Number Publication Date
DE69621294D1 DE69621294D1 (de) 2002-06-27
DE69621294T2 true DE69621294T2 (de) 2003-01-09

Family

ID=16373063

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69621294T Expired - Lifetime DE69621294T2 (de) 1995-08-02 1996-08-01 Halbleiterspeicheranordnungen

Country Status (5)

Country Link
US (2) US5831904A (de)
EP (1) EP0757359B1 (de)
KR (1) KR100242099B1 (de)
DE (1) DE69621294T2 (de)
SG (1) SG72699A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272046B1 (en) * 2000-05-02 2001-08-07 Advanced Micro Devices, Inc. Individual source line to decrease column leakage
US6426898B1 (en) * 2001-03-05 2002-07-30 Micron Technology, Inc. Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells
US6967872B2 (en) * 2001-12-18 2005-11-22 Sandisk Corporation Method and system for programming and inhibiting multi-level, non-volatile memory cells

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63153797A (ja) * 1986-12-17 1988-06-27 Fujitsu Ltd 書込み可能なリ−ドオンリメモリ
US5233562A (en) * 1991-12-30 1993-08-03 Intel Corporation Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device
US5388069A (en) * 1992-03-19 1995-02-07 Fujitsu Limited Nonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenon
JPH06162787A (ja) * 1992-11-17 1994-06-10 Matsushita Electric Ind Co Ltd 電気的一括消去機能を有する不揮発性メモリの読み出し方法
JPH06349288A (ja) * 1993-06-02 1994-12-22 Fujitsu Ltd 不揮発性半導体記憶装置
US5422846A (en) * 1994-04-04 1995-06-06 Motorola Inc. Nonvolatile memory having overerase protection
US5576991A (en) * 1994-07-01 1996-11-19 Advanced Micro Devices, Inc. Multistepped threshold convergence for a flash memory array
JP3238574B2 (ja) * 1994-07-28 2001-12-17 株式会社東芝 不揮発性半導体記憶装置とその消去方法
US5546340A (en) * 1995-06-13 1996-08-13 Advanced Micro Devices, Inc. Non-volatile memory array with over-erase correction
US5608672A (en) * 1995-09-26 1997-03-04 Advanced Micro Devices, Inc. Correction method leading to a uniform threshold voltage distribution for a flash eprom

Also Published As

Publication number Publication date
EP0757359B1 (de) 2002-05-22
KR970012767A (ko) 1997-03-29
DE69621294D1 (de) 2002-06-27
EP0757359A3 (de) 1998-10-07
KR100242099B1 (ko) 2000-03-02
US5920509A (en) 1999-07-06
US5831904A (en) 1998-11-03
SG72699A1 (en) 2000-05-23
EP0757359A2 (de) 1997-02-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP