DE69629147D1 - Digitaler Phasenregelkreis - Google Patents

Digitaler Phasenregelkreis

Info

Publication number
DE69629147D1
DE69629147D1 DE69629147T DE69629147T DE69629147D1 DE 69629147 D1 DE69629147 D1 DE 69629147D1 DE 69629147 T DE69629147 T DE 69629147T DE 69629147 T DE69629147 T DE 69629147T DE 69629147 D1 DE69629147 D1 DE 69629147D1
Authority
DE
Germany
Prior art keywords
locked loop
phase locked
digital phase
digital
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69629147T
Other languages
English (en)
Other versions
DE69629147T2 (de
Inventor
Yoshinori Rokugo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69629147D1 publication Critical patent/DE69629147D1/de
Application granted granted Critical
Publication of DE69629147T2 publication Critical patent/DE69629147T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
DE69629147T 1995-04-28 1996-04-26 Digitaler Phasenregelkreis Expired - Lifetime DE69629147T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10593395 1995-04-28
JP7105933A JP2964912B2 (ja) 1995-04-28 1995-04-28 デジタルｐｌｌ

Publications (2)

Publication Number Publication Date
DE69629147D1 true DE69629147D1 (de) 2003-08-28
DE69629147T2 DE69629147T2 (de) 2004-02-19

Family

ID=14420660

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69629147T Expired - Lifetime DE69629147T2 (de) 1995-04-28 1996-04-26 Digitaler Phasenregelkreis

Country Status (5)

Country Link
US (1) US5694068A (de)
EP (1) EP0740423B1 (de)
JP (1) JP2964912B2 (de)
CA (1) CA2175133C (de)
DE (1) DE69629147T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788237A4 (de) * 1995-08-03 1998-11-25 Anritsu Corp Frequenzteiler mit rationalem teilerverhältnis und frequenzsynthetisierer damit
US6021503A (en) * 1996-12-21 2000-02-01 Micron Communications, Inc. Bit synchronization for interrogator
US6223317B1 (en) * 1998-02-28 2001-04-24 Micron Technology, Inc. Bit synchronizers and methods of synchronizing and calculating error
US6959062B1 (en) 2000-01-28 2005-10-25 Micron Technology, Inc. Variable delay line
US7170963B2 (en) * 2003-01-15 2007-01-30 Nano Silicon Pte. Ltd. Clock recovery method by phase selection
JP3803805B2 (ja) * 2003-09-05 2006-08-02 日本テキサス・インスツルメンツ株式会社 ディジタル位相同期ループ回路
WO2011150964A1 (en) * 2010-06-01 2011-12-08 Abb Technology Ag Precision switching for carrier based pwm
CN115085727A (zh) 2016-04-22 2022-09-20 康杜实验室公司 高性能锁相环
US10193716B2 (en) 2016-04-28 2019-01-29 Kandou Labs, S.A. Clock data recovery with decision feedback equalization
US10411922B2 (en) 2016-09-16 2019-09-10 Kandou Labs, S.A. Data-driven phase detector element for phase locked loops
US10200188B2 (en) 2016-10-21 2019-02-05 Kandou Labs, S.A. Quadrature and duty cycle error correction in matrix phase lock loop
CN110945830B (zh) 2017-05-22 2022-09-09 康杜实验室公司 多模式数据驱动型时钟恢复电路
CN107911114B (zh) * 2017-11-15 2021-03-09 中国科学技术大学 一种恒定环路带宽的宽带锁相环
US10554380B2 (en) 2018-01-26 2020-02-04 Kandou Labs, S.A. Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
KR102445856B1 (ko) 2018-06-12 2022-09-21 칸도우 랩스 에스에이 저지연 조합 클록 데이터 복구 로직 회로망 및 차지 펌프 회로
US10958251B2 (en) 2019-04-08 2021-03-23 Kandou Labs, S.A. Multiple adjacent slicewise layout of voltage-controlled oscillator
US10673443B1 (en) 2019-04-08 2020-06-02 Kandou Labs, S.A. Multi-ring cross-coupled voltage-controlled oscillator
US10630272B1 (en) 2019-04-08 2020-04-21 Kandou Labs, S.A. Measurement and correction of multiphase clock duty cycle and skew
US11463092B1 (en) 2021-04-01 2022-10-04 Kanou Labs Sa Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios
US11563605B2 (en) 2021-04-07 2023-01-24 Kandou Labs SA Horizontal centering of sampling point using multiple vertical voltage measurements
US11496282B1 (en) 2021-06-04 2022-11-08 Kandou Labs, S.A. Horizontal centering of sampling point using vertical vernier

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808884A (en) * 1985-12-02 1989-02-28 Western Digital Corporation High order digital phase-locked loop system
JP2993200B2 (ja) * 1991-07-31 1999-12-20 日本電気株式会社 位相同期ループ
FR2682236B1 (fr) * 1991-10-04 1997-01-03 Cit Alcatel Procede et dispositif de commande de mode de fonctionnement d'une boucle a verrouillage de phase numerique
JP3232351B2 (ja) * 1993-10-06 2001-11-26 三菱電機株式会社 デジタル回路装置
US5463351A (en) * 1994-09-29 1995-10-31 Motorola, Inc. Nested digital phase lock loop

Also Published As

Publication number Publication date
EP0740423A3 (de) 1998-04-08
JP2964912B2 (ja) 1999-10-18
JPH08307250A (ja) 1996-11-22
DE69629147T2 (de) 2004-02-19
US5694068A (en) 1997-12-02
CA2175133C (en) 2000-04-04
EP0740423A2 (de) 1996-10-30
EP0740423B1 (de) 2003-07-23
CA2175133A1 (en) 1996-10-29

Similar Documents

Publication Publication Date Title
FI954624A (fi) Digitaalinen vaihelukittu sisäsilmukka
GB9414729D0 (en) Digital phase locked loop
DE69629147D1 (de) Digitaler Phasenregelkreis
DE69415378D1 (de) Digitaler Phasenregelkreis
DE69202531T2 (de) Phasenregelschleife.
DE69309349D1 (de) Digitaler Phasenregelkreis
DE69619783D1 (de) Phasenregelschleife mit regelbarer Antwortzeit
DE69307581T2 (de) Phasenregelkreis
DE69737801D1 (de) Phasenregelkreisschaltung
DE69510577T2 (de) Phasenregelkreis
DE69620839D1 (de) Phasenregelschleife
DE59406102D1 (de) Digitale Phasenregelschleife
DE69224872D1 (de) Entscheidungsgeführte Phasenverriegelte Schleife
DE69629545D1 (de) Digitale Phasenregelkreisschaltung
DE69710165D1 (de) Phasenregelschleife
DE59003079D1 (de) Digitaler Phasenregelkreis.
DE69330310T2 (de) Digitaler phasenschieber
DE69512121T2 (de) Phasenregelkreisschaltung
DE59409844D1 (de) Optischer Phasenregelkreis
DE59208112D1 (de) Digitaler Phasenregelkreis
DE69409903T2 (de) Digitaler Phasenkomparator
GB2296397B (en) Digital phase locked loop
DE69721450D1 (de) Phasenregelkreisschaltung
DE59107340D1 (de) Phasenregelkreis höherer Ordnung
DE69610505T2 (de) Digitaler phasenumkehrdetektor

Legal Events

Date Code Title Description
8364 No opposition during term of opposition