DE69702256D1 - Verfahren für einen merhfachen, bits pro zelle flash eeprom, speicher mit seitenprogrammierungsmodus und leseverfahren - Google Patents

Verfahren für einen merhfachen, bits pro zelle flash eeprom, speicher mit seitenprogrammierungsmodus und leseverfahren

Info

Publication number
DE69702256D1
DE69702256D1 DE69702256T DE69702256T DE69702256D1 DE 69702256 D1 DE69702256 D1 DE 69702256D1 DE 69702256 T DE69702256 T DE 69702256T DE 69702256 T DE69702256 T DE 69702256T DE 69702256 D1 DE69702256 D1 DE 69702256D1
Authority
DE
Germany
Prior art keywords
memory
bits per
per cell
programming mode
flash eeprom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69702256T
Other languages
English (en)
Other versions
DE69702256T2 (de
Inventor
Stewart Bill
Prakash Gutala
Qimeng Derek Zhou
Shichang Su
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69702256D1 publication Critical patent/DE69702256D1/de
Publication of DE69702256T2 publication Critical patent/DE69702256T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5622—Concurrent multilevel programming of more than one cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
DE69702256T 1996-06-24 1997-01-31 Verfahren für einen merhfachen, bits pro zelle flash eeprom, speicher mit seitenprogrammierungsmodus und leseverfahren Expired - Lifetime DE69702256T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66879596A 1996-06-24 1996-06-24
PCT/US1997/001822 WO1997050089A1 (en) 1996-06-24 1997-01-31 A method for a multiple bits-per-cell flash eeprom with page mode program and read

Publications (2)

Publication Number Publication Date
DE69702256D1 true DE69702256D1 (de) 2000-07-13
DE69702256T2 DE69702256T2 (de) 2001-01-18

Family

ID=24683776

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69702256T Expired - Lifetime DE69702256T2 (de) 1996-06-24 1997-01-31 Verfahren für einen merhfachen, bits pro zelle flash eeprom, speicher mit seitenprogrammierungsmodus und leseverfahren

Country Status (5)

Country Link
US (1) US5754475A (de)
EP (1) EP0907954B1 (de)
DE (1) DE69702256T2 (de)
TW (1) TW316311B (de)
WO (1) WO1997050089A1 (de)

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100566466B1 (ko) * 1995-01-31 2006-03-31 가부시끼가이샤 히다치 세이사꾸쇼 반도체 메모리 장치
JP3062730B2 (ja) 1996-07-10 2000-07-12 株式会社日立製作所 不揮発性半導体記憶装置および書込み方法
US6320785B1 (en) * 1996-07-10 2001-11-20 Hitachi, Ltd. Nonvolatile semiconductor memory device and data writing method therefor
JP3127953B2 (ja) * 1996-08-09 2001-01-29 日本電気株式会社 半導体記憶装置
US6857099B1 (en) * 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
IL125604A (en) 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6430077B1 (en) 1997-12-12 2002-08-06 Saifun Semiconductors Ltd. Method for regulating read voltage level at the drain of a cell in a symmetric array
US6633499B1 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Method for reducing voltage drops in symmetric array architectures
US6633496B2 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Symmetric architecture for memory cells having widely spread metal bit lines
JP3346274B2 (ja) * 1998-04-27 2002-11-18 日本電気株式会社 不揮発性半導体記憶装置
KR100285065B1 (ko) * 1998-06-12 2001-03-15 윤종용 불 휘발성 반도체 메모리 장치
JP2000021185A (ja) * 1998-06-30 2000-01-21 Sharp Corp 不揮発性半導体メモリの書込み方法
US6160440A (en) * 1998-09-25 2000-12-12 Intel Corporation Scaleable charge pump for use with a low voltage power supply
US6038169A (en) * 1999-03-18 2000-03-14 Halo Lsi Design & Device Technology, Inc. Read reference scheme for flash memory
FR2801419B1 (fr) * 1999-11-18 2003-07-25 St Microelectronics Sa Procede et dispositif de lecture pour memoire en circuit integre
US6304486B1 (en) * 1999-12-20 2001-10-16 Fujitsu Limited Sensing time control device and method
US6226213B1 (en) * 2000-01-31 2001-05-01 Taiwan Semiconductor Manufacturing Co., Ltd. Reference cell array to generate the reference current for sense amplifier
US6396741B1 (en) * 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6928001B2 (en) * 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
EP1160795B1 (de) * 2000-05-31 2007-12-19 STMicroelectronics S.r.l. Referenzzellenmatrixanordnung zum Datenlesen in einer nichtflüchtigen Speicheranordnung
JP4212760B2 (ja) * 2000-06-02 2009-01-21 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
US6614692B2 (en) 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6677805B2 (en) * 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
TW559814B (en) * 2001-05-31 2003-11-01 Semiconductor Energy Lab Nonvolatile memory and method of driving the same
US6906951B2 (en) * 2001-06-14 2005-06-14 Multi Level Memory Technology Bit line reference circuits for binary and multiple-bit-per-cell memories
US6574139B2 (en) * 2001-06-20 2003-06-03 Fujitsu Limited Method and device for reading dual bit memory cells using multiple reference cells with two side read
US6574158B1 (en) 2001-09-27 2003-06-03 Cypress Semiconductor Corp. Method and system for measuring threshold of EPROM cells
US6791396B2 (en) * 2001-10-24 2004-09-14 Saifun Semiconductors Ltd. Stack element circuit
US6643181B2 (en) 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US6583007B1 (en) 2001-12-20 2003-06-24 Saifun Semiconductors Ltd. Reducing secondary injection effects
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
US6690602B1 (en) * 2002-04-08 2004-02-10 Advanced Micro Devices, Inc. Algorithm dynamic reference programming
US6700815B2 (en) 2002-04-08 2004-03-02 Advanced Micro Devices, Inc. Refresh scheme for dynamic page programming
US6799256B2 (en) * 2002-04-12 2004-09-28 Advanced Micro Devices, Inc. System and method for multi-bit flash reads using dual dynamic references
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6826107B2 (en) * 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US6992932B2 (en) * 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6963505B2 (en) * 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US6967896B2 (en) * 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US6906958B2 (en) * 2003-03-26 2005-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Word-line voltage generator
US7142464B2 (en) * 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7237074B2 (en) * 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US7324374B2 (en) * 2003-06-20 2008-01-29 Spansion Llc Memory with a core-based virtual ground and dynamic reference sensing scheme
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US6954393B2 (en) * 2003-09-16 2005-10-11 Saifun Semiconductors Ltd. Reading array cell with matched reference cell
JP4443886B2 (ja) * 2003-09-30 2010-03-31 株式会社東芝 半導体記憶装置
US7301807B2 (en) 2003-10-23 2007-11-27 Sandisk Corporation Writable tracking cells
US7177200B2 (en) * 2004-02-10 2007-02-13 Msystems Ltd. Two-phase programming of a flash memory
US7652930B2 (en) * 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
US7460918B2 (en) * 2004-06-10 2008-12-02 Moteurs Leroy-Somer Devices and methods for updating the programming of a system for controlling an electric rotary machine
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060036803A1 (en) * 2004-08-16 2006-02-16 Mori Edan Non-volatile memory device controlled by a micro-controller
KR100928738B1 (ko) * 2004-08-30 2009-11-27 스펜션 엘엘씨 반도체 장치, 반도체 장치의 테스트 방법 및 데이터 기록방법
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
US7113427B1 (en) * 2005-03-09 2006-09-26 National Semiconductor Corporation NVM PMOS-cell with one erased and two programmed states
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
JP2006294144A (ja) * 2005-04-12 2006-10-26 Toshiba Corp 不揮発性半導体記憶装置
WO2006129344A1 (ja) * 2005-05-30 2006-12-07 Spansion Llc 半導体装置
US8400841B2 (en) * 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) * 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
JP2007012180A (ja) * 2005-06-30 2007-01-18 Renesas Technology Corp 半導体記憶装置
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7447077B2 (en) * 2005-08-05 2008-11-04 Halo Lsi, Inc. Referencing scheme for trap memory
US20070036007A1 (en) * 2005-08-09 2007-02-15 Saifun Semiconductors, Ltd. Sticky bit buffer
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7224619B2 (en) * 2005-09-09 2007-05-29 Macronix International Co., Ltd. Method and apparatus for protection from over-erasing nonvolatile memory cells
JP4874637B2 (ja) * 2005-11-30 2012-02-15 ラピスセミコンダクタ株式会社 不揮発性記憶装置およびその読出し方法
US7263004B2 (en) * 2005-12-08 2007-08-28 Elite Semiconductor Memory Technology Inc. Method and apparatus for determining sensing timing of flash memory
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US20070272090A1 (en) * 2006-02-01 2007-11-29 Bommaraju Tilak V Hydrogen mitigation and energy generation with water-activated chemical heaters
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US20070255889A1 (en) * 2006-03-22 2007-11-01 Yoav Yogev Non-volatile memory device and method of operating the device
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7336532B2 (en) * 2006-05-12 2008-02-26 Elite Semiconductor Memory Method for reading NAND memory device and memory cell array thereof
US7558907B2 (en) * 2006-10-13 2009-07-07 Spansion Llc Virtual memory card controller
US7443753B2 (en) * 2006-11-21 2008-10-28 Macronix International Co., Ltd. Memory structure, programming method and reading method therefor, and memory control circuit thereof
US7719899B2 (en) 2007-02-13 2010-05-18 Micron Technology, Inc. Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory
KR100865821B1 (ko) * 2007-03-14 2008-10-28 주식회사 하이닉스반도체 불휘발성 메모리 장치의 독출 방법
JP4911508B2 (ja) * 2007-03-30 2012-04-04 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置及びその動作方法
US7800951B2 (en) 2007-08-20 2010-09-21 Marvell World Trade Ltd. Threshold voltage digitizer for array of programmable threshold transistors
US7778098B2 (en) * 2007-12-31 2010-08-17 Cypress Semiconductor Corporation Dummy cell for memory circuits
TWI451420B (zh) * 2010-01-20 2014-09-01 Macronix Int Co Ltd 具有記憶體程式化放電電路之積體電路裝置及其方法
US20140269061A1 (en) * 2013-03-15 2014-09-18 Silicon Storage Technology, Inc. High Speed Sensing For Advanced Nanometer Flash Memory Device
US9484068B2 (en) * 2015-02-17 2016-11-01 Kilopass Technology, Inc. MTP-thyristor memory cell circuits and methods of operation
US9659624B1 (en) * 2016-03-15 2017-05-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Method for sense reference generation for MTJ based memories
JP2020047326A (ja) * 2018-09-18 2020-03-26 キオクシア株式会社 半導体メモリ装置、メモリシステム、および方法
CN111696607B (zh) 2019-03-13 2022-05-17 力旺电子股份有限公司 可编程可抹除的非易失性存储器
CN114664355B (zh) * 2022-03-16 2022-11-25 珠海博雅科技股份有限公司 非易失性存储器的参考电流产生模块和参考电流设置方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4993175A (en) * 1988-08-12 1991-02-19 Black & Decker, Inc. Soleplate steam slot arrangement
JP2573335B2 (ja) * 1988-11-09 1997-01-22 株式会社東芝 不揮発性メモリ
JPH0373495A (ja) * 1989-02-15 1991-03-28 Ricoh Co Ltd 半導体メモリ装置
US5172338B1 (en) * 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
WO1990016069A1 (en) * 1989-06-12 1990-12-27 Kabushiki Kaisha Toshiba Semiconductor memory device
JP2853217B2 (ja) * 1989-11-21 1999-02-03 日本電気株式会社 半導体メモリ
US5532962A (en) * 1992-05-20 1996-07-02 Sandisk Corporation Soft errors handling in EEPROM devices
US5386132A (en) * 1992-11-02 1995-01-31 Wong; Chun C. D. Multimedia storage system with highly compact memory device

Also Published As

Publication number Publication date
EP0907954B1 (de) 2000-06-07
US5754475A (en) 1998-05-19
DE69702256T2 (de) 2001-01-18
EP0907954A1 (de) 1999-04-14
TW316311B (en) 1997-09-21
WO1997050089A1 (en) 1997-12-31

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Owner name: SPANSION LLC (N.D.GES.D. STAATES DELAWARE), SU, US