DE69708188T2 - Speichersteuerungseinheit - Google Patents

Speichersteuerungseinheit

Info

Publication number
DE69708188T2
DE69708188T2 DE69708188T DE69708188T DE69708188T2 DE 69708188 T2 DE69708188 T2 DE 69708188T2 DE 69708188 T DE69708188 T DE 69708188T DE 69708188 T DE69708188 T DE 69708188T DE 69708188 T2 DE69708188 T2 DE 69708188T2
Authority
DE
Germany
Prior art keywords
control unit
memory control
memory
unit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69708188T
Other languages
English (en)
Other versions
DE69708188D1 (de
Inventor
Thomas Basilio Genduso
Edward Robert Vanderslice
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69708188D1 publication Critical patent/DE69708188D1/de
Publication of DE69708188T2 publication Critical patent/DE69708188T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
DE69708188T 1996-04-04 1997-03-14 Speichersteuerungseinheit Expired - Fee Related DE69708188T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/628,230 US5778422A (en) 1996-04-04 1996-04-04 Data processing system memory controller that selectively caches data associated with write requests

Publications (2)

Publication Number Publication Date
DE69708188D1 DE69708188D1 (de) 2001-12-20
DE69708188T2 true DE69708188T2 (de) 2002-06-20

Family

ID=24518023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69708188T Expired - Fee Related DE69708188T2 (de) 1996-04-04 1997-03-14 Speichersteuerungseinheit

Country Status (6)

Country Link
US (1) US5778422A (de)
EP (1) EP0800137B1 (de)
JP (1) JPH1055306A (de)
KR (1) KR100268204B1 (de)
DE (1) DE69708188T2 (de)
TW (1) TW408266B (de)

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US6374330B1 (en) * 1997-04-14 2002-04-16 International Business Machines Corporation Cache-coherency protocol with upstream undefined state
US6094708A (en) 1997-05-06 2000-07-25 Cisco Technology, Inc. Secondary cache write-through blocking mechanism
US6341335B1 (en) 1997-10-29 2002-01-22 Hitachi, Ltd. Information processing system for read ahead buffer memory equipped with register and memory controller
US6115385A (en) 1998-03-11 2000-09-05 Cisco Technology, Inc. Method and system for subnetting in a switched IP network
US6138208A (en) * 1998-04-13 2000-10-24 International Business Machines Corporation Multiple level cache memory with overlapped L1 and L2 memory access
US6785274B2 (en) 1998-10-07 2004-08-31 Cisco Technology, Inc. Efficient network multicast switching apparatus and methods
US20020056027A1 (en) * 1998-10-29 2002-05-09 Hiroki Kanai Information processing system
US6483736B2 (en) 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6460114B1 (en) * 1999-07-29 2002-10-01 Micron Technology, Inc. Storing a flushed cache line in a memory buffer of a controller
JP2001060169A (ja) * 1999-08-24 2001-03-06 Hitachi Ltd キャッシュコントローラ及びコンピュータシステム
US7099998B1 (en) * 2000-03-31 2006-08-29 Intel Corporation Method for reducing an importance level of a cache line
US8575719B2 (en) 2000-04-28 2013-11-05 Sandisk 3D Llc Silicon nitride antifuse for use in diode-antifuse memory arrays
EP2988331B1 (de) 2000-08-14 2019-01-09 SanDisk Technologies LLC Halbleiterspeicherbauelement
KR100364800B1 (ko) * 2000-08-29 2002-12-16 주식회사 하이닉스반도체 반도체 메모리의 데이터 입출력 제어 장치
US6598119B2 (en) * 2001-02-09 2003-07-22 At&T Corp. Database management system with a multiple-level cache arrangement
US7352199B2 (en) 2001-02-20 2008-04-01 Sandisk Corporation Memory card with enhanced testability and methods of making and using the same
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6593624B2 (en) 2001-09-25 2003-07-15 Matrix Semiconductor, Inc. Thin film transistors with vertically offset drain regions
US6843421B2 (en) 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US6624485B2 (en) 2001-11-05 2003-09-23 Matrix Semiconductor, Inc. Three-dimensional, mask-programmed read only memory
US6731011B2 (en) 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
US6853049B2 (en) 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
TWI282513B (en) * 2002-06-12 2007-06-11 Mediatek Inc A pre-fetch device of instruction for an embedded system
US6737675B2 (en) 2002-06-27 2004-05-18 Matrix Semiconductor, Inc. High density 3D rail stack arrays
EP1387276A3 (de) * 2002-07-31 2004-03-31 Texas Instruments Incorporated Verfahren und Vorrichtung zur Speicherverwaltung
JP2005115603A (ja) 2003-10-07 2005-04-28 Hitachi Ltd 記憶デバイス制御装置及びその制御方法
DE102004055013A1 (de) * 2004-11-15 2006-05-24 Infineon Technologies Ag Computereinrichtung
US7409502B2 (en) * 2006-05-11 2008-08-05 Freescale Semiconductor, Inc. Selective cache line allocation instruction execution and circuitry
JP4412676B2 (ja) 2007-05-30 2010-02-10 インターナショナル・ビジネス・マシーンズ・コーポレーション メインメモリに書き込むデータをキャッシュする技術
US20120324195A1 (en) * 2011-06-14 2012-12-20 Alexander Rabinovitch Allocation of preset cache lines
US9431064B2 (en) 2012-11-02 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and cache circuit configuration
US9384136B2 (en) 2013-04-12 2016-07-05 International Business Machines Corporation Modification of prefetch depth based on high latency event
US9478495B1 (en) 2015-10-26 2016-10-25 Sandisk Technologies Llc Three dimensional memory device containing aluminum source contact via structure and method of making thereof
KR102398201B1 (ko) * 2017-06-30 2022-05-17 삼성전자주식회사 프로세서의 개입 없이 단순 작업을 관리하는 스토리지 장치

Family Cites Families (18)

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US4464712A (en) * 1981-07-06 1984-08-07 International Business Machines Corporation Second level cache replacement method and apparatus
US5155828A (en) * 1989-07-05 1992-10-13 Hewlett-Packard Company Computing system with a cache memory and an additional look-aside cache memory
US5133058A (en) * 1989-09-18 1992-07-21 Sun Microsystems, Inc. Page-tagging translation look-aside buffer for a computer memory system
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
CA2044487A1 (en) * 1990-06-15 1991-12-16 Michael E. Tullis Lookaside cache
DE69127936T2 (de) * 1990-06-29 1998-05-07 Digital Equipment Corp Busprotokoll für Prozessor mit write-back cache
DE69130967T2 (de) * 1990-08-06 1999-10-21 Ncr Int Inc Rechnerspeicheranordnung
US5249282A (en) * 1990-11-21 1993-09-28 Benchmarq Microelectronics, Inc. Integrated cache memory system with primary and secondary cache memories
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5386547A (en) * 1992-01-21 1995-01-31 Digital Equipment Corporation System and method for exclusive two-level caching
WO1993018459A1 (en) * 1992-03-06 1993-09-16 Rambus Inc. Prefetching into a cache to minimize main memory access time and cache size in a computer system
US5367657A (en) * 1992-10-01 1994-11-22 Intel Corporation Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems
US5566324A (en) * 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
GB2276964A (en) * 1993-03-31 1994-10-12 Hypertech Pty Ltd Buffering write cycles.
US5623628A (en) * 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
US5564035A (en) * 1994-03-23 1996-10-08 Intel Corporation Exclusive and/or partially inclusive extension cache system and method to minimize swapping therein
US5561779A (en) * 1994-05-04 1996-10-01 Compaq Computer Corporation Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
US5737565A (en) * 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer

Also Published As

Publication number Publication date
KR970071282A (ko) 1997-11-07
DE69708188D1 (de) 2001-12-20
KR100268204B1 (ko) 2000-10-16
US5778422A (en) 1998-07-07
JPH1055306A (ja) 1998-02-24
TW408266B (en) 2000-10-11
EP0800137B1 (de) 2001-11-14
EP0800137A1 (de) 1997-10-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee