DE69808286T2 - Emulationssytem mit zeitmultiplexverbindung - Google Patents

Emulationssytem mit zeitmultiplexverbindung

Info

Publication number
DE69808286T2
DE69808286T2 DE69808286T DE69808286T DE69808286T2 DE 69808286 T2 DE69808286 T2 DE 69808286T2 DE 69808286 T DE69808286 T DE 69808286T DE 69808286 T DE69808286 T DE 69808286T DE 69808286 T2 DE69808286 T2 DE 69808286T2
Authority
DE
Germany
Prior art keywords
emulation system
devices
time multiplex
circuit board
multiplex connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69808286T
Other languages
English (en)
Other versions
DE69808286D1 (de
Inventor
P Sample
Mikhail Bershteyn
R Butts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quickturn Design Systems Inc
Original Assignee
Quickturn Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quickturn Design Systems Inc filed Critical Quickturn Design Systems Inc
Publication of DE69808286D1 publication Critical patent/DE69808286D1/de
Application granted granted Critical
Publication of DE69808286T2 publication Critical patent/DE69808286T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S370/00—Multiplex communications
    • Y10S370/916—Multiplexer/demultiplexer
DE69808286T 1997-05-30 1998-05-18 Emulationssytem mit zeitmultiplexverbindung Expired - Lifetime DE69808286T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/865,741 US5960191A (en) 1997-05-30 1997-05-30 Emulation system with time-multiplexed interconnect
PCT/US1998/010171 WO1998054664A1 (en) 1997-05-30 1998-05-18 Emulation system with time-multiplexed interconnect

Publications (2)

Publication Number Publication Date
DE69808286D1 DE69808286D1 (de) 2002-10-31
DE69808286T2 true DE69808286T2 (de) 2003-07-31

Family

ID=25346124

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69808286T Expired - Lifetime DE69808286T2 (de) 1997-05-30 1998-05-18 Emulationssytem mit zeitmultiplexverbindung

Country Status (10)

Country Link
US (4) US5960191A (de)
EP (1) EP0983562B1 (de)
JP (1) JP4424760B2 (de)
KR (1) KR20010013190A (de)
AT (1) ATE225058T1 (de)
CA (1) CA2291738A1 (de)
DE (1) DE69808286T2 (de)
IL (1) IL132983A (de)
TW (1) TW440796B (de)
WO (1) WO1998054664A1 (de)

Families Citing this family (318)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802348A (en) * 1995-12-18 1998-09-01 Virtual Machine Works, Inc. Logic analysis system for logic emulation systems
JPH10222374A (ja) 1996-10-28 1998-08-21 Altera Corp 遠隔ソフトウェア技術支援を提供するための方法
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US6286114B1 (en) * 1997-10-27 2001-09-04 Altera Corporation Enhanced embedded logic analyzer
US6370662B2 (en) * 1998-03-16 2002-04-09 S3 Incorporated Modifying circuit designs running from both edges of clock to run from positive edge
US6662327B1 (en) * 1998-05-13 2003-12-09 Janusz Rajski Method for clustered test pattern generation
US6240376B1 (en) 1998-07-24 2001-05-29 Mentor Graphics Corporation Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging
US6336087B2 (en) * 1998-07-24 2002-01-01 Luc M. Burgun Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging
KR100308189B1 (ko) * 1998-09-17 2001-11-30 윤종용 코어셀기반의집적회로의테스트용이도를증가시키기위한바운더리스캔회로
EP1156523A4 (de) * 1999-02-17 2003-08-06 Hitachi Ltd Speichermedium und halbleiter ic-herstellung
US6820051B1 (en) * 1999-02-19 2004-11-16 Texas Instruments Incorporated Software emulation monitor employed with hardware suspend mode
US6622233B1 (en) * 1999-03-31 2003-09-16 Star Bridge Systems, Inc. Hypercomputer
US6353915B1 (en) * 1999-04-01 2002-03-05 Unisys Corporation Methods for evaluating systems of electronic components
US6947882B1 (en) * 1999-09-24 2005-09-20 Mentor Graphics Corporation Regionally time multiplexed emulation system
US6473726B1 (en) * 1999-09-24 2002-10-29 Frederic Reblewski Method and apparatus for concurrent emulation of multiple circuit designs on an emulation system
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
JP2003527674A (ja) * 1999-10-22 2003-09-16 メンター・グラフィクス・コーポレーション エミュレーション信号の効率的なルーティングアーキテクチャを有するエミュレーションシステム
US6633838B1 (en) * 1999-11-04 2003-10-14 International Business Machines Corporation Multi-state logic analyzer integral to a microprocessor
US6262594B1 (en) * 1999-11-05 2001-07-17 Ati International, Srl Apparatus and method for configurable use of groups of pads of a system on chip
US6823497B2 (en) 1999-11-30 2004-11-23 Synplicity, Inc. Method and user interface for debugging an electronic system
US7240303B1 (en) 1999-11-30 2007-07-03 Synplicity, Inc. Hardware/software co-debugging in a hardware description language
US7065481B2 (en) * 1999-11-30 2006-06-20 Synplicity, Inc. Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
US6618839B1 (en) * 1999-11-30 2003-09-09 Synplicity, Inc. Method and system for providing an electronic system design with enhanced debugging capabilities
US7072818B1 (en) 1999-11-30 2006-07-04 Synplicity, Inc. Method and system for debugging an electronic system
US7356786B2 (en) * 1999-11-30 2008-04-08 Synplicity, Inc. Method and user interface for debugging an electronic system
US6931572B1 (en) 1999-11-30 2005-08-16 Synplicity, Inc. Design instrumentation circuitry
US6647525B1 (en) * 1999-12-16 2003-11-11 Texas Instruments Incorporated Electronics testing circuit and method
US6434735B1 (en) * 1999-12-16 2002-08-13 Lsi Logic Corporation Method for programming an FPGA and implementing an FPGA interconnect
US6633181B1 (en) * 1999-12-30 2003-10-14 Stretch, Inc. Multi-scale programmable array
US6539536B1 (en) * 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
US6754862B1 (en) 2000-03-09 2004-06-22 Altera Corporation Gaining access to internal nodes in a PLD
US6961691B1 (en) * 2000-03-30 2005-11-01 Mentor Graphics Corporation Non-synchronized multiplex data transport across synchronous systems
US6980563B2 (en) * 2000-04-13 2005-12-27 International Business Machines Corporation Method and system for fast ethernet serial port multiplexing to reduce I/O pin count
US6654919B1 (en) * 2000-04-17 2003-11-25 Lsi Logic Corporation Automated system for inserting and reading of probe points in silicon embedded testbenches
US6473889B1 (en) * 2000-04-29 2002-10-29 Hewlett-Packard Company Method of automatically generating repeater blocks in HDL and integrating them into a region constrained chip design
US7379859B2 (en) * 2001-04-24 2008-05-27 Mentor Graphics Corporation Emulator with switching network connections
US6826717B1 (en) * 2000-06-12 2004-11-30 Altera Corporation Synchronization of hardware and software debuggers
US6751723B1 (en) * 2000-09-02 2004-06-15 Actel Corporation Field programmable gate array and microcontroller system-on-a-chip
US6681373B1 (en) * 2000-10-02 2004-01-20 Lsi Logic Corporation Method and apparatus for dynamic buffer and inverter tree optimization
US7188063B1 (en) * 2000-10-26 2007-03-06 Cypress Semiconductor Corporation Capturing test/emulation and enabling real-time debugging using an FPGA for in-circuit emulation
US8103496B1 (en) 2000-10-26 2012-01-24 Cypress Semicondutor Corporation Breakpoint control in an in-circuit emulation system
US7765095B1 (en) 2000-10-26 2010-07-27 Cypress Semiconductor Corporation Conditional branching in an in-circuit emulation system
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US8149048B1 (en) 2000-10-26 2012-04-03 Cypress Semiconductor Corporation Apparatus and method for programmable power management in a programmable analog circuit block
US8160864B1 (en) 2000-10-26 2012-04-17 Cypress Semiconductor Corporation In-circuit emulator and pod synchronized boot
US7024653B1 (en) * 2000-10-30 2006-04-04 Cypress Semiconductor Corporation Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD)
WO2002042947A1 (en) * 2000-11-24 2002-05-30 Italtel S.P.A. A prototyping system
US7222315B2 (en) 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US6857110B1 (en) * 2001-01-30 2005-02-15 Stretch, Inc. Design methodology for merging programmable logic into a custom IC
US20020133325A1 (en) * 2001-02-09 2002-09-19 Hoare Raymond R. Discrete event simulator
US6493850B2 (en) * 2001-02-16 2002-12-10 Texas Instruments Incorporated Integrated circuit design error detector for electrostatic discharge and latch-up applications
KR20010067730A (ko) * 2001-03-14 2001-07-13 박규호 화상전화 단말기의 사용자 인증방법
RU2273965C2 (ru) * 2001-04-30 2006-04-10 Хуавей Текнолоджиз Ко., Лтд. Способ передачи данных по цепи объединительной панели при мультиплексировании с временным разделением и мостовой соединитель
US6605962B2 (en) * 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US20040023558A1 (en) * 2001-06-07 2004-02-05 Fowler Michael L. Mid-connect architecture with point-to-point connections for high speed data transfer
US20030002541A1 (en) * 2001-06-07 2003-01-02 Fowler Michael L. Mid-connect architecture with point-to-point connections for high speed data transfer
US20030046492A1 (en) * 2001-08-28 2003-03-06 International Business Machines Corporation, Armonk, New York Configurable memory array
JP2003085001A (ja) * 2001-09-12 2003-03-20 Toshiba Corp ソース・コード・デバッガ、デバッグ方法及びデバッグプログラム
US6681377B2 (en) 2001-09-18 2004-01-20 Quickturn Design Systems, Inc. Timing resynthesis in a multi-clock emulation system
EP1302775A1 (de) * 2001-10-16 2003-04-16 Italtel s.p.a. System zur Erzeugung von Taktsignalen für ein Prototypgerät
US7406674B1 (en) 2001-10-24 2008-07-29 Cypress Semiconductor Corporation Method and apparatus for generating microcontroller configuration information
CN1582533A (zh) * 2001-10-29 2005-02-16 捷豹逻辑股份有限公司 用于现场可编程门阵列核心的可编程接口
US7305633B2 (en) * 2001-10-30 2007-12-04 Mentor Graphics Corporation Distributed configuration of integrated circuits in an emulation system
US7130788B2 (en) * 2001-10-30 2006-10-31 Mentor Graphics Corporation Emulation components and system including distributed event monitoring, and testing of an IC design under emulation
US7035787B2 (en) * 2001-10-30 2006-04-25 Mentor Graphics Corporation Emulation components and system including distributed routing and configuration of emulation resources
US8078970B1 (en) 2001-11-09 2011-12-13 Cypress Semiconductor Corporation Graphical user interface with user-selectable list-box
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US7844437B1 (en) 2001-11-19 2010-11-30 Cypress Semiconductor Corporation System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US6971004B1 (en) 2001-11-19 2005-11-29 Cypress Semiconductor Corp. System and method of dynamically reconfiguring a programmable integrated circuit
US7774190B1 (en) 2001-11-19 2010-08-10 Cypress Semiconductor Corporation Sleep and stall in an in-circuit emulation system
US7770113B1 (en) * 2001-11-19 2010-08-03 Cypress Semiconductor Corporation System and method for dynamically generating a configuration datasheet
US8069405B1 (en) 2001-11-19 2011-11-29 Cypress Semiconductor Corporation User interface for efficiently browsing an electronic document using data-driven tabs
US20030105617A1 (en) * 2001-12-05 2003-06-05 Nec Usa, Inc. Hardware acceleration system for logic simulation
US6686769B1 (en) * 2001-12-14 2004-02-03 Altera Corporation Programmable I/O element circuit for high speed logic devices
US6996443B2 (en) * 2002-01-11 2006-02-07 Bae Systems Information And Electronic Systems Integration Inc. Reconfigurable digital processing system for space
US7114135B1 (en) * 2002-01-11 2006-09-26 Lsi Logic Corporation Routing of test signals of integrated circuits
US20030188278A1 (en) * 2002-03-26 2003-10-02 Carrie Susan Elizabeth Method and apparatus for accelerating digital logic simulations
TW552535B (en) * 2002-03-27 2003-09-11 Via Tech Inc Method of integrated circuit design flow
US8103497B1 (en) * 2002-03-28 2012-01-24 Cypress Semiconductor Corporation External interface for event architecture
US7117458B1 (en) * 2002-04-30 2006-10-03 Unisys Corporation Identifying specific netlist gates for use in code coverage testing
US7308608B1 (en) 2002-05-01 2007-12-11 Cypress Semiconductor Corporation Reconfigurable testing system and method
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US6704909B1 (en) * 2002-06-19 2004-03-09 Hewlett-Packard Development Company, L.P. Reduction of storage elements in synthesized synchronous circuits
FR2841668B1 (fr) * 2002-06-26 2006-08-11 Emulation And Verification Eng Procede et systeme d'emulation d'un circuit sous test associe a un environnement de test
US20040045007A1 (en) * 2002-08-30 2004-03-04 Bae Systems Information Electronic Systems Integration, Inc. Object oriented component and framework architecture for signal processing
US7017140B2 (en) * 2002-08-29 2006-03-21 Bae Systems Information And Electronic Systems Integration Inc. Common components in interface framework for developing field programmable based applications independent of target circuit board
US7761845B1 (en) 2002-09-09 2010-07-20 Cypress Semiconductor Corporation Method for parameterizing a user module
US6965972B2 (en) * 2002-09-25 2005-11-15 International Business Machines Corporation Real time emulation of coherence directories using global sparse directories
US20040078179A1 (en) * 2002-10-17 2004-04-22 Renesas Technology Corp. Logic verification system
US6816814B2 (en) * 2002-11-12 2004-11-09 Sonics, Inc. Method and apparatus for decomposing and verifying configurable hardware
US7036046B2 (en) * 2002-11-14 2006-04-25 Altera Corporation PLD debugging hub
US7051229B2 (en) * 2002-12-03 2006-05-23 Alcatel Canada Inc. Logical bus overlay for increasing the existing system bus data rate
US7069523B2 (en) * 2002-12-13 2006-06-27 Lsi Logic Corporation Automated selection and placement of memory during design of an integrated circuit
US7260794B2 (en) * 2002-12-20 2007-08-21 Quickturn Design Systems, Inc. Logic multiprocessor for FPGA implementation
US7539915B1 (en) 2003-01-07 2009-05-26 Marvell Israel (Misl) Ltd. Integrated circuit testing using segmented scan chains
US7007254B1 (en) 2003-01-17 2006-02-28 Synplicity, Inc. Method and apparatus for the design and analysis of digital circuits with time division multiplexing
EP1450278B1 (de) 2003-01-23 2013-04-24 Cadence Design Systems, Inc. Verfahren und Gerät zur Prüfung der Funtionsfähigkeit eines Schaltungsentwurfs
US7440884B2 (en) * 2003-01-23 2008-10-21 Quickturn Design Systems, Inc. Memory rewind and reconstruction for hardware emulator
US7146480B2 (en) * 2003-01-23 2006-12-05 Hewlett-Packard Development Company, L.P. Configurable memory system
US7076751B1 (en) 2003-01-24 2006-07-11 Altera Corporation Chip debugging using incremental recompilation
US7228265B2 (en) * 2003-05-02 2007-06-05 Egenera, Inc. System and method for emulating serial port communication
US6894527B1 (en) * 2003-05-12 2005-05-17 Xilinx, Inc. Evolved circuits for bitstream protection
US20040228411A1 (en) * 2003-05-12 2004-11-18 Sony Corporation Method and system for decoder clock control in presence of jitter
US7584392B2 (en) * 2003-05-23 2009-09-01 Cadence Design Systems, Inc. Test compaction using linear-matrix driven scan chains
US20040242261A1 (en) * 2003-05-29 2004-12-02 General Dynamics Decision Systems, Inc. Software-defined radio
US7286976B2 (en) * 2003-06-10 2007-10-23 Mentor Graphics (Holding) Ltd. Emulation of circuits with in-circuit memory
US7120571B2 (en) * 2003-06-16 2006-10-10 Fortelink, Inc. Resource board for emulation system
US7539900B1 (en) 2003-07-29 2009-05-26 Altera Corporation Embedded microprocessor for integrated circuit testing and debugging
US7512851B2 (en) * 2003-08-01 2009-03-31 Syntest Technologies, Inc. Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
US20050050503A1 (en) * 2003-08-25 2005-03-03 Keller S. Brandon Systems and methods for establishing data model consistency of computer aided design tools
US7356454B2 (en) * 2003-10-17 2008-04-08 Ud Technology Corporation Method and apparatus for emulation of logic circuits
US7086025B1 (en) * 2003-10-23 2006-08-01 Adaptec, Inc. Programmable logic device partitioning method for application specific integrated circuit prototyping
US7594197B2 (en) * 2003-11-12 2009-09-22 Paul Mack Semiconductor device having predictable electrical properties
US7657809B1 (en) 2003-11-19 2010-02-02 Cadence Design Systems, Inc. Dual scan chain design method and apparatus
US8694976B2 (en) * 2003-12-19 2014-04-08 Intel Corporation Sleep state mechanism for virtual multithreading
US7206967B1 (en) 2004-02-09 2007-04-17 Altera Corporation Chip debugging using incremental recompilation and register insertion
US7167025B1 (en) * 2004-02-14 2007-01-23 Herman Schmit Non-sequentially configurable IC
US7284222B1 (en) * 2004-06-30 2007-10-16 Tabula, Inc. Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit
US7425841B2 (en) 2004-02-14 2008-09-16 Tabula Inc. Configurable circuits, IC's, and systems
US7193440B1 (en) * 2004-02-14 2007-03-20 Herman Schmit Configurable circuits, IC's, and systems
US7109752B1 (en) * 2004-02-14 2006-09-19 Herman Schmit Configurable circuits, IC's, and systems
US7126381B1 (en) 2004-02-14 2006-10-24 Herman Schmit VPA interconnect circuit
US7552024B2 (en) * 2004-03-08 2009-06-23 Kelbon Richard G Circuit board diagnostic operating center
US7295049B1 (en) 2004-03-25 2007-11-13 Cypress Semiconductor Corporation Method and circuit for rapid alignment of signals
KR20060130256A (ko) 2004-03-30 2006-12-18 닛본 덴끼 가부시끼가이샤 회로 검증 장치, 회로 검증 방법 및 그를 위한 신호 분배방법
US7698118B2 (en) * 2004-04-15 2010-04-13 Mentor Graphics Corporation Logic design modeling and interconnection
US7440866B2 (en) * 2004-06-01 2008-10-21 Quickturn Design Systems Inc. System and method for validating an input/output voltage of a target system
US7721036B2 (en) * 2004-06-01 2010-05-18 Quickturn Design Systems Inc. System and method for providing flexible signal routing and timing
US7606697B2 (en) * 2004-06-01 2009-10-20 Quickturn Design Systems, Inc. System and method for resolving artifacts in differential signals
US7640155B2 (en) * 2004-06-01 2009-12-29 Quickturn Design Systems, Inc. Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications
US7145361B1 (en) * 2004-06-30 2006-12-05 Andre Rohe Configurable integrated circuit with different connection schemes
US7408382B2 (en) * 2004-06-30 2008-08-05 Tabula, Inc. Configurable circuits, IC's, and systems
US7439766B2 (en) * 2004-06-30 2008-10-21 Tabula, Inc. Configurable logic circuits with commutative properties
US7282950B1 (en) * 2004-11-08 2007-10-16 Tabula, Inc. Configurable IC's with logic resources with offset connections
US7312630B2 (en) * 2004-06-30 2007-12-25 Tabula, Inc. Configurable integrated circuit with built-in turns
US7449915B2 (en) * 2004-06-30 2008-11-11 Tabula Inc. VPA logic circuits
US8073672B2 (en) * 2004-07-06 2011-12-06 Mentor Graphics Corporation Managing communication bandwidth in co-verification of circuit designs
US8286125B2 (en) 2004-08-13 2012-10-09 Cypress Semiconductor Corporation Model for a hardware device-independent method of defining embedded firmware for programmable systems
US8069436B2 (en) 2004-08-13 2011-11-29 Cypress Semiconductor Corporation Providing hardware independence to automate code generation of processing device firmware
US7917559B2 (en) * 2004-11-08 2011-03-29 Tabula, Inc. Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations
US7276933B1 (en) * 2004-11-08 2007-10-02 Tabula, Inc. Reconfigurable IC that has sections running at different looperness
US7743085B2 (en) * 2004-11-08 2010-06-22 Tabula, Inc. Configurable IC with large carry chains
US7268586B1 (en) * 2004-11-08 2007-09-11 Tabula, Inc. Method and apparatus for accessing stored data in a reconfigurable IC
US7301368B2 (en) * 2005-03-15 2007-11-27 Tabula, Inc. Embedding memory within tile arrangement of a configurable IC
US7330050B2 (en) 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US20070244958A1 (en) * 2004-11-08 2007-10-18 Jason Redgrave Configurable IC's with carry bypass circuitry
US7342415B2 (en) * 2004-11-08 2008-03-11 Tabula, Inc. Configurable IC with interconnect circuits that also perform storage operations
US7242216B1 (en) 2004-11-08 2007-07-10 Herman Schmit Embedding memory between tile arrangement of a configurable IC
US7317331B2 (en) 2004-11-08 2008-01-08 Tabula, Inc. Reconfigurable IC that has sections running at different reconfiguration rates
US7295037B2 (en) 2004-11-08 2007-11-13 Tabula, Inc. Configurable IC with routing circuits with offset connections
US7573296B2 (en) * 2004-11-08 2009-08-11 Tabula Inc. Configurable IC with configurable routing resources that have asymmetric input and/or outputs
US7259587B1 (en) * 2004-11-08 2007-08-21 Tabula, Inc. Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs
US7224181B1 (en) * 2004-11-08 2007-05-29 Herman Schmit Clock distribution in a configurable IC
US7424416B1 (en) 2004-11-09 2008-09-09 Sun Microsystems, Inc. Interfacing hardware emulation to distributed simulation environments
US8046729B1 (en) * 2004-11-24 2011-10-25 Altera Corporation Method and apparatus for composing and decomposing low-skew networks
US7236009B1 (en) 2004-12-01 2007-06-26 Andre Rohe Operational time extension
US7461192B2 (en) 2004-12-15 2008-12-02 Rambus Inc. Interface for bridging out-of-band information and preventing false presence detection of terminating devices
US7750669B2 (en) * 2005-01-06 2010-07-06 Justin Martin Spangaro Reprogrammable integrated circuit
US7752016B2 (en) * 2005-01-11 2010-07-06 Hewlett-Packard Development Company, L.P. System and method for data analysis
US7228472B2 (en) * 2005-01-11 2007-06-05 Hewlett-Packard Development Company, L.P. System and method to control data capture
US7348799B2 (en) * 2005-01-11 2008-03-25 Hewlett-Packard Development Company, L.P. System and method for generating a trigger signal
US7809991B2 (en) * 2005-01-11 2010-10-05 Hewlett-Packard Development Company, L.P. System and method to qualify data capture
US7480609B1 (en) 2005-01-31 2009-01-20 Sun Microsystems, Inc. Applying distributed simulation techniques to hardware emulation
US7332976B1 (en) 2005-02-04 2008-02-19 Cypress Semiconductor Corporation Poly-phase frequency synthesis oscillator
US7353162B2 (en) * 2005-02-11 2008-04-01 S2C, Inc. Scalable reconfigurable prototyping system and method
US20070244959A1 (en) * 2005-03-15 2007-10-18 Steven Teig Configurable IC's with dual carry chains
US7224182B1 (en) * 2005-03-15 2007-05-29 Brad Hutchings Hybrid configurable circuit for a configurable IC
US7825684B2 (en) * 2005-03-15 2010-11-02 Tabula, Inc. Variable width management for a memory of a configurable IC
US7230869B1 (en) 2005-03-15 2007-06-12 Jason Redgrave Method and apparatus for accessing contents of memory cells
US7298169B2 (en) * 2005-03-15 2007-11-20 Tabula, Inc Hybrid logic/interconnect circuit in a configurable IC
US7530033B2 (en) * 2005-03-15 2009-05-05 Tabula, Inc. Method and apparatus for decomposing functions in a configurable IC
US7310003B2 (en) * 2005-03-15 2007-12-18 Tabula, Inc. Configurable IC with interconnect circuits that have select lines driven by user signals
US8145469B2 (en) 2005-04-06 2012-03-27 Quickturn Design Systems, Inc. System and method for providing compact mapping between dissimilar memory systems
US7577558B2 (en) * 2005-04-06 2009-08-18 Quickturn Design Systems, Inc. System and method for providing compact mapping between dissimilar memory systems
US7818705B1 (en) 2005-04-08 2010-10-19 Altera Corporation Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew
US8205186B1 (en) 2005-04-11 2012-06-19 Synopsys, Inc. Incremental modification of instrumentation logic
US7349670B2 (en) * 2005-04-12 2008-03-25 Azimuth Systems Inc. Modular wireless test architecture and method
US20060247909A1 (en) * 2005-04-27 2006-11-02 Desai Madhav P System and method for emulating a logic circuit design using programmable logic devices
US7400183B1 (en) 2005-05-05 2008-07-15 Cypress Semiconductor Corporation Voltage controlled oscillator delay cell and method
US7751436B2 (en) * 2005-05-24 2010-07-06 Sony Corporation System and method for dynamically establishing PLL speed based on receive buffer data accumulation for streaming video
WO2006133149A2 (en) 2005-06-03 2006-12-14 Quickturn Design Systems, Inc. Method for analyzing power consumption of circuit design using hardware emulation
US8089461B2 (en) 2005-06-23 2012-01-03 Cypress Semiconductor Corporation Touch wake for electronic devices
US7444276B2 (en) * 2005-09-28 2008-10-28 Liga Systems, Inc. Hardware acceleration system for logic simulation using shift register as local cache
US7265556B2 (en) * 2005-09-28 2007-09-04 Lucent Technologies Inc. System and method for adaptable testing of backplane interconnections and a test tool incorporating the same
US20070073999A1 (en) * 2005-09-28 2007-03-29 Verheyen Henry T Hardware acceleration system for logic simulation using shift register as local cache with path for bypassing shift register
US20070074000A1 (en) * 2005-09-28 2007-03-29 Liga Systems, Inc. VLIW Acceleration System Using Multi-state Logic
US7372297B1 (en) 2005-11-07 2008-05-13 Tabula Inc. Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources
US7818361B1 (en) 2005-11-07 2010-10-19 Tabula, Inc. Method and apparatus for performing two's complement multiplication
US8463836B1 (en) 2005-11-07 2013-06-11 Tabula, Inc. Performing mathematical and logical operations in multiple sub-cycles
US7765249B1 (en) 2005-11-07 2010-07-27 Tabula, Inc. Use of hybrid interconnect/logic circuits for multiplication
US7461362B1 (en) 2005-12-01 2008-12-02 Tabula, Inc. Replacing circuit design elements with their equivalents
US20070129926A1 (en) * 2005-12-01 2007-06-07 Verheyen Henry T Hardware acceleration system for simulation of logic and memory
US20070129924A1 (en) * 2005-12-06 2007-06-07 Verheyen Henry T Partitioning of tasks for execution by a VLIW hardware acceleration system
US7679401B1 (en) 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US7489162B1 (en) 2005-12-01 2009-02-10 Tabula, Inc. Users registers in a reconfigurable IC
US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
US20070150702A1 (en) * 2005-12-23 2007-06-28 Verheyen Henry T Processor
US8352242B2 (en) * 2006-02-21 2013-01-08 Mentor Graphics Corporation Communication scheme between programmable sub-cores in an emulation environment
EP1859372B1 (de) * 2006-02-23 2019-03-27 Mentor Graphics Corporation Crossbar-vermittlung in einer emulationsumgebung
EP1864219A1 (de) 2006-02-28 2007-12-12 Mentor Graphics Corporation Übrwachung physischer parameter in einer emulationsumgebung
EP1854035A1 (de) 2006-02-28 2007-11-14 Mentor Graphics Corporation Auf speicher basierendes trigger-erzeugungsschema in einer emulationsumgebung
US7797497B1 (en) 2006-03-08 2010-09-14 Tabula, Inc. System and method for providing more logical memory ports than physical memory ports
US7609085B1 (en) 2006-03-08 2009-10-27 Tabula, Inc. Configurable integrated circuit with a 4-to-1 multiplexer
US7694083B1 (en) * 2006-03-08 2010-04-06 Tabula, Inc. System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
US7555424B2 (en) 2006-03-16 2009-06-30 Quickturn Design Systems, Inc. Method and apparatus for rewinding emulated memory circuits
US7669097B1 (en) 2006-03-27 2010-02-23 Tabula, Inc. Configurable IC with error detection and correction circuitry
US8067948B2 (en) 2006-03-27 2011-11-29 Cypress Semiconductor Corporation Input/output multiplexer bus
KR101282963B1 (ko) * 2006-05-12 2013-07-08 삼성전자주식회사 에뮬레이션 시스템 및 그 방법
US7725304B1 (en) * 2006-05-22 2010-05-25 Cadence Design Systems, Inc. Method and apparatus for coupling data between discrete processor based emulation integrated chips
US8775147B1 (en) 2006-05-31 2014-07-08 The Mathworks, Inc. Algorithm and architecture for multi-argument associative operations that minimizes the number of components using a latency of the components
US20080229074A1 (en) * 2006-06-19 2008-09-18 International Business Machines Corporation Design Structure for Localized Control Caching Resulting in Power Efficient Control Logic
US20070294519A1 (en) * 2006-06-19 2007-12-20 Miller Laura F Localized Control Caching Resulting In Power Efficient Control Logic
US7536668B1 (en) * 2006-08-11 2009-05-19 Xilinx, Inc. Determining networks of a tile module of a programmable logic device
US7451425B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining controlling pins for a tile module of a programmable logic device
US7451424B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining programmable connections through a switchbox of a programmable logic device
US7451420B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining reachable pins of a network of a programmable logic device
US7584448B1 (en) * 2006-08-11 2009-09-01 Xilinx, Inc. Constructing a model of a programmable logic device
US7472370B1 (en) 2006-08-11 2008-12-30 Xilinx, Inc. Comparing graphical and netlist connections of a programmable logic device
US7451423B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining indices of configuration memory cell modules of a programmable logic device
US7847730B2 (en) * 2006-09-27 2010-12-07 Bae Systems Information And Electronic Systems Integration, Inc. Software defined navigation signal generator
US8232991B1 (en) * 2006-11-03 2012-07-31 Nvidia Corporation Z-test result reconciliation with multiple partitions
US7930666B1 (en) 2006-12-12 2011-04-19 Tabula, Inc. System and method of providing a memory hierarchy
US7877720B2 (en) * 2007-01-08 2011-01-25 International Business Machines Corporation Method and tool for designing electronic circuits on a printed circuit board
US7525344B2 (en) * 2007-03-20 2009-04-28 Tabula, Inc. Configurable IC having a routing fabric with storage elements
US7610566B1 (en) 2007-03-22 2009-10-27 Tabula, Inc. Method and apparatus for function decomposition
US8026739B2 (en) 2007-04-17 2011-09-27 Cypress Semiconductor Corporation System level interconnect with programmable switching
US8516025B2 (en) 2007-04-17 2013-08-20 Cypress Semiconductor Corporation Clock driven dynamic datapath chaining
US7737724B2 (en) 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US8092083B2 (en) 2007-04-17 2012-01-10 Cypress Semiconductor Corporation Temperature sensor with digital bandgap
US9564902B2 (en) 2007-04-17 2017-02-07 Cypress Semiconductor Corporation Dynamically configurable and re-configurable data path
US8040266B2 (en) 2007-04-17 2011-10-18 Cypress Semiconductor Corporation Programmable sigma-delta analog-to-digital converter
US8130025B2 (en) 2007-04-17 2012-03-06 Cypress Semiconductor Corporation Numerical band gap
US8266575B1 (en) 2007-04-25 2012-09-11 Cypress Semiconductor Corporation Systems and methods for dynamically reconfiguring a programmable system on a chip
US9720805B1 (en) 2007-04-25 2017-08-01 Cypress Semiconductor Corporation System and method for controlling a target device
US8065653B1 (en) 2007-04-25 2011-11-22 Cypress Semiconductor Corporation Configuration of programmable IC design elements
US8049569B1 (en) 2007-09-05 2011-11-01 Cypress Semiconductor Corporation Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
WO2009035586A1 (en) 2007-09-06 2009-03-19 Tabula, Inc. Configuration context switcher
US7925940B2 (en) * 2007-10-17 2011-04-12 Synopsys, Inc. Enhancing speed of simulation of an IC design while testing scan circuitry
US8352235B1 (en) 2007-10-31 2013-01-08 Cadence Design Systems, Inc. Emulation of power shutoff behavior for integrated circuits
US7983893B2 (en) 2008-01-08 2011-07-19 Mentor Graphics Corporation Fault support in an emulation environment
US7782084B1 (en) * 2008-02-04 2010-08-24 Netlogic Microsystems, Inc. Integrated circuit with reconfigurable inputs/outputs
US8863067B1 (en) 2008-02-06 2014-10-14 Tabula, Inc. Sequential delay analysis by placement engines
US7930165B2 (en) * 2008-02-07 2011-04-19 Accemic Gmbh & Co. Kg Procedure and device for emulating a programmable unit providing system integrity control
US8214192B2 (en) 2008-02-27 2012-07-03 Mentor Graphics Corporation Resource remapping in a hardware emulation environment
US7944234B2 (en) * 2008-03-19 2011-05-17 Micron Technology, Inc. Programmable on-chip logic analyzer apparatus, systems, and methods
US8214195B2 (en) 2008-03-21 2012-07-03 Mentor Graphics Corporation Testing in a hardware emulation environment
US20090248390A1 (en) * 2008-03-31 2009-10-01 Eric Durand Trace debugging in a hardware emulation environment
US20090259457A1 (en) * 2008-04-14 2009-10-15 Mentor Graphics Corporaton Trace Routing Network
KR101524828B1 (ko) * 2008-04-23 2015-06-02 삼성전자주식회사 에뮬레이션 시스템 및 그 구동 방법
US8108194B2 (en) 2008-04-25 2012-01-31 Cadence Design Systems, Inc. Peak power detection in digital designs using emulation systems
US8166435B2 (en) * 2008-06-26 2012-04-24 Tabula, Inc. Timing operations in an IC with configurable circuits
US8674721B2 (en) 2008-09-17 2014-03-18 Tabula, Inc. Controllable storage elements for an IC
JP5347482B2 (ja) * 2008-12-18 2013-11-20 富士通セミコンダクター株式会社 性能評価装置、性能評価方法及びシミュレーションプログラム
JPWO2010097875A1 (ja) * 2009-02-24 2012-08-30 パナソニック株式会社 データ処理装置、方法
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
US8145466B1 (en) * 2009-05-21 2012-03-27 Xilinx, Inc. Clustering of electronic circuit design modules for hardware-based and software-based co-simulation platforms
US8898051B2 (en) * 2009-06-12 2014-11-25 Cadence Design Systems, Inc. System and method for implementing a trace interface
US8724665B2 (en) * 2009-07-20 2014-05-13 Synopsys, Inc. Pseudo-synchronous time division multiplexing
US8473661B2 (en) * 2009-08-14 2013-06-25 Cadence Design Systems, Inc. System and method for providing multi-process protection using direct memory mapped control registers
US8327198B2 (en) * 2009-08-14 2012-12-04 Intel Corporation On-die logic analyzer for semiconductor die
US8108821B2 (en) * 2010-01-12 2012-01-31 International Business Machines Corporation Reduction of logic and delay through latch polarity inversion
US9324718B2 (en) * 2010-01-29 2016-04-26 Hewlett Packard Enterprise Development Lp Three dimensional multilayer circuit
US8839179B2 (en) 2010-02-12 2014-09-16 Synopsys Taiwan Co., LTD. Prototype and emulation system for multiple custom prototype boards
US8196081B1 (en) * 2010-03-31 2012-06-05 Xilinx, Inc. Incremental placement and routing
WO2011123151A1 (en) 2010-04-02 2011-10-06 Tabula Inc. System and method for reducing reconfiguration power usage
WO2011136212A1 (ja) * 2010-04-27 2011-11-03 日本電気株式会社 論理回路エミュレータ及び論理回路エミュレータの制御方法
US8269524B2 (en) * 2010-04-27 2012-09-18 Atmel Corporation General purpose input/output pin mapping
TWI450118B (zh) * 2010-11-02 2014-08-21 Global Unichip Corp 混合的電子設計系統及其可重組連接矩陣
US8707113B1 (en) * 2011-01-25 2014-04-22 Agilent Technologies, Inc. Method for modeling a device and generating test for that device
US8726109B2 (en) * 2011-05-02 2014-05-13 New York University Architecture, system, method, and computer-accessible medium for eliminating scan performance penalty
WO2012154612A1 (en) * 2011-05-06 2012-11-15 Xcelemor, Inc. Computing system with hardware scheduled reconfiguration mechanism and method of operation thereof
US8760193B2 (en) 2011-07-01 2014-06-24 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
WO2013071183A1 (en) 2011-11-11 2013-05-16 Tabula, Inc. Content addressable memory in integrated circuit
US8959010B1 (en) 2011-12-08 2015-02-17 Cadence Design Systems, Inc. Emulation system with improved reliability of interconnect and a method for programming such interconnect
US8743735B1 (en) 2012-01-18 2014-06-03 Cadence Design Systems, Inc. Emulation system for verifying a network device
US9230046B2 (en) 2012-03-30 2016-01-05 International Business Machines Corporation Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
US8595683B1 (en) 2012-04-12 2013-11-26 Cadence Design Systems, Inc. Generating user clocks for a prototyping environment
US9703579B2 (en) 2012-04-27 2017-07-11 Mentor Graphics Corporation Debug environment for a multi user hardware assisted verification system
FR2991476B1 (fr) * 2012-06-01 2022-04-22 Flexras Tech Prototypage multi-fpga d'un circuit asic
US9129072B2 (en) 2012-10-15 2015-09-08 Qualcomm Incorporated Virtual GPIO
US9240545B2 (en) 2012-11-05 2016-01-19 Cisco Technology, Inc. Dynamic state machine
US8949752B2 (en) * 2012-12-01 2015-02-03 Synopsys, Inc. System and method of emulating multiple custom prototype boards
JP6247452B2 (ja) * 2013-05-02 2017-12-13 キヤノン株式会社 記録ヘッド及び記録装置
EP2871589B1 (de) 2013-11-08 2019-06-26 Synopsys, Inc. Verfahren und System zur Erzeugung einer Schaltungsbeschreibung für ein feldprogrammierbares Gate-Array mit mehreren Matrizen
US9747244B2 (en) 2013-11-22 2017-08-29 Qualcomm Incorporated Clockless virtual GPIO
US9846587B1 (en) * 2014-05-15 2017-12-19 Xilinx, Inc. Performance analysis using configurable hardware emulation within an integrated circuit
US9292639B1 (en) 2014-10-30 2016-03-22 Cadence Design Systems Inc. Method and system for providing additional look-up tables
US9506982B2 (en) 2014-11-14 2016-11-29 Cavium, Inc. Testbench builder, system, device and method including a generic monitor and transporter
US9647688B1 (en) 2014-12-19 2017-05-09 Cadence Design Systems, Inc. System and method of encoding in a serializer/deserializer
US9379846B1 (en) 2014-12-19 2016-06-28 Cadence Design Systems, Inc. System and method of encoding in a serializer/deserializer
US9405877B1 (en) 2014-12-22 2016-08-02 Cadence Design Systems, Inc. System and method of fast phase aligned local generation of clocks on multiple FPGA system
US9495492B1 (en) 2015-01-05 2016-11-15 Cadence Design Systems, Inc. Implementing synchronous triggers for waveform capture in an FPGA prototyping system
US9294094B1 (en) 2015-01-08 2016-03-22 Cadence Design Systems, Inc. Method and apparatus for fast low skew phase generation for multiplexing signals on a multi-FPGA prototyping system
US10282315B2 (en) 2015-03-27 2019-05-07 Cavium, Llc Software assisted hardware configuration for software defined network system-on-chip
US10146727B2 (en) * 2015-04-14 2018-12-04 Qualcomm Incorporated Enhanced virtual GPIO with multi-mode modulation
ITUB20150760A1 (it) 2015-05-25 2016-11-25 St Microelectronics Srl Procedimento per riconfigurare unita' digitali, sistema, apparecchiatura e prodotto informatico corrispondenti
US9684743B2 (en) * 2015-06-19 2017-06-20 Synopsys, Inc. Isolated debugging in an FPGA based emulation environment
US9702933B1 (en) 2015-10-22 2017-07-11 Cadence Design Systems, Inc. System and method for concurrent interconnection diagnostics field
US9697324B1 (en) 2015-11-05 2017-07-04 Cadence Design Systems, Inc. System for concurrent target diagnostics field
US10176100B1 (en) 2015-12-21 2019-01-08 Cadence Design Systems, Inc. Cache coherency process
US10198538B1 (en) * 2015-12-28 2019-02-05 Cadence Design Systems, Inc. Relocate targets to different domains in an emulator
US10068041B2 (en) 2016-02-01 2018-09-04 King Fahd University Of Petroleum And Minerals Multi-core compact executable trace processor
US10783283B1 (en) * 2017-02-28 2020-09-22 Cadence Design Systems, Inc. Systems and methods for performing a reset sequence simulation in an electronic design
US10198539B1 (en) 2017-03-02 2019-02-05 Cadence Design Systems, Inc. Systems and methods for dynamic RTL monitors in emulation systems
US10796048B1 (en) * 2017-06-16 2020-10-06 Synopsys, Inc. Adding delay elements to enable mapping a time division multiplexing circuit on an FPGA of a hardware emulator
US20190069394A1 (en) * 2017-08-23 2019-02-28 Teradyne, Inc. Reducing timing skew in a circuit path
US10841246B2 (en) 2017-08-30 2020-11-17 Arista Networks, Inc. Distributed core switching with orthogonal fabric card and line cards
US11138356B1 (en) * 2018-08-17 2021-10-05 Synopsys, Inc. Dedicated reconfigurable IP for emulation-based power estimation
WO2020061045A1 (en) * 2018-09-18 2020-03-26 Leidos, Inc. Sensor array multiplexer
US10922203B1 (en) * 2018-09-21 2021-02-16 Nvidia Corporation Fault injection architecture for resilient GPU computing
US11243856B1 (en) * 2018-12-12 2022-02-08 Cadence Design Systems, Inc. Framing protocol supporting low-latency serial interface in an emulation system
US20200195586A1 (en) * 2018-12-18 2020-06-18 Arista Networks, Inc. Network devices with multiple switch cards
US10986423B2 (en) 2019-04-11 2021-04-20 Arista Networks, Inc. Network device with compact chassis
US11266007B2 (en) 2019-09-18 2022-03-01 Arista Networks, Inc. Linecard system using riser printed circuit boards (PCBS)
CN114265079B (zh) * 2021-12-23 2023-04-11 西南交通大学 一种采用掺铒光纤放大器的时分复用多普勒测速系统
CN114330191B (zh) * 2022-03-08 2022-06-10 上海国微思尔芯技术股份有限公司 一种信号复用传输的方法及装置

Family Cites Families (182)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL238555A (de) * 1958-04-25
US3287702A (en) * 1962-12-04 1966-11-22 Westinghouse Electric Corp Computer control
US3287703A (en) * 1962-12-04 1966-11-22 Westinghouse Electric Corp Computer
US3473160A (en) * 1966-10-10 1969-10-14 Stanford Research Inst Electronically controlled microelectronic cellular logic array
US3485953A (en) * 1966-12-06 1969-12-23 Control Data Corp Asynchronous time-sharing of multi-carrier channels
US3541524A (en) * 1968-03-14 1970-11-17 Ibm Time division communications processor
US4315315A (en) * 1971-03-09 1982-02-09 The Johns Hopkins University Graphical automatic programming
DE2158433C3 (de) * 1971-11-25 1975-07-31 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Einrichtung zur Fehlerprüfung und Fehlerlokalisierung in einer moduleren Datenverarbeitungsanlage
GB1444084A (en) 1972-06-21 1976-07-28 Honeywell Inf Systems Generalized logic device
US3955180A (en) * 1974-01-02 1976-05-04 Honeywell Information Systems Inc. Table driven emulation system
DE2412962B2 (de) * 1974-03-18 1976-02-26 Siemens AG, 1000 Berlin und 8000 München Verfahren zur zeitmultiplex-uebertragung von daten
NL7408823A (de) * 1974-07-01 1974-09-25
US4020469A (en) * 1975-04-09 1977-04-26 Frank Manning Programmable arrays
CH584488A5 (de) * 1975-05-05 1977-01-31 Ibm
US4290133A (en) * 1977-10-25 1981-09-15 Digital Equipment Corporation System timing means for data processing system
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
US4357678A (en) * 1979-12-26 1982-11-02 International Business Machines Corporation Programmable sequential logic array mechanism
US4386403A (en) * 1979-12-31 1983-05-31 International Business Machines Corp. System and method for LSI circuit analysis
JPS57105898A (en) * 1980-12-23 1982-07-01 Fujitsu Ltd Field programmable element
US4404635A (en) * 1981-03-27 1983-09-13 International Business Machines Corporation Programmable integrated circuit and method of testing the circuit before it is programmed
FR2508669A1 (fr) * 1981-06-24 1982-12-31 Fordahl Dispositif logique programmable de prise, traitement et transmission de donnees
US4488354A (en) * 1981-11-16 1984-12-18 Ncr Corporation Method for simulating and testing an integrated circuit chip
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4656580A (en) * 1982-06-11 1987-04-07 International Business Machines Corporation Logic simulation machine
JPS5916050A (ja) * 1982-07-16 1984-01-27 Nec Corp ダイナミツクゲ−トアレイ
US4525789A (en) * 1982-07-16 1985-06-25 At&T Bell Laboratories Programmable network tester with data formatter
US4539564A (en) * 1982-08-04 1985-09-03 Smithson G Ronald Electronically controlled interconnection system
US4527249A (en) * 1982-10-22 1985-07-02 Control Data Corporation Simulator system for logic design validation
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
US4527115A (en) * 1982-12-22 1985-07-02 Raytheon Company Configurable logic gate array
US4578761A (en) * 1983-03-25 1986-03-25 At&T Bell Laboratories Separating an equivalent circuit into components to detect terminating networks
US4791602A (en) * 1983-04-14 1988-12-13 Control Data Corporation Soft programmable logic array
US4583169A (en) * 1983-04-29 1986-04-15 The Boeing Company Method for emulating a Boolean network system
US4612618A (en) * 1983-06-10 1986-09-16 Rca Corporation Hierarchical, computerized design of integrated circuits
US4621339A (en) * 1983-06-13 1986-11-04 Duke University SIMD machine using cube connected cycles network architecture for vector processing
US4587625A (en) * 1983-07-05 1986-05-06 Motorola Inc. Processor for simulating digital structures
US4593363A (en) * 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US4524240A (en) * 1983-08-17 1985-06-18 Lucasfilm Ltd. Universal circuit prototyping board
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
US4600846A (en) * 1983-10-06 1986-07-15 Sanders Associates, Inc. Universal logic circuit modules
EP0138535A3 (en) * 1983-10-13 1987-01-28 British Telecommunications Plc Visual display logic simulation system
NL8303536A (nl) * 1983-10-14 1985-05-01 Philips Nv Geintegreerde schakeling op grote schaal welke verdeeld is in isochrone gebieden, werkwijze voor het machinaal ontwerpen van zo een geintegreerde schakeling, en werkwijze voor het machinaal testen van zo een geintegreerde schakeling.
WO1985002033A1 (en) * 1983-11-03 1985-05-09 Prime Computer, Inc. Digital system simulation method and apparatus
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4782461A (en) * 1984-06-21 1988-11-01 Step Engineering Logical grouping of facilities within a computer development system
US4695999A (en) * 1984-06-27 1987-09-22 International Business Machines Corporation Cross-point switch of multiple autonomous planes
JPS6124250A (ja) 1984-07-13 1986-02-01 Nippon Gakki Seizo Kk 半導体集積回路装置
JPS6142040A (ja) * 1984-08-03 1986-02-28 Nec Corp 論理シミユレ−タ
US4695950A (en) * 1984-09-17 1987-09-22 International Business Machines Corporation Fast two-level dynamic address translation method and means
US4713557A (en) * 1984-09-26 1987-12-15 Xilinx, Inc. Bidirectional buffer amplifier
US4642487A (en) * 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
US4695740A (en) * 1984-09-26 1987-09-22 Xilinx, Inc. Bidirectional buffer amplifier
US5023775A (en) 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
JPS61199166A (ja) * 1985-03-01 1986-09-03 Nec Corp 配線経路探索装置
US4937827A (en) * 1985-03-01 1990-06-26 Mentor Graphics Corporation Circuit verification accessory
US4697241A (en) * 1985-03-01 1987-09-29 Simulog, Inc. Hardware logic simulator
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US4766569A (en) * 1985-03-04 1988-08-23 Lattice Semiconductor Corporation Programmable logic array
US4814646A (en) * 1985-03-22 1989-03-21 Monolithic Memories, Inc. Programmable logic array using emitter-coupled logic
JPS61226844A (ja) * 1985-03-30 1986-10-08 Nec Corp 論理回路のシミユレ−シヨン制御方法
US4819150A (en) * 1985-04-05 1989-04-04 Unisys Corporation Array for simulating computer functions for large computer systems
US4674089A (en) * 1985-04-16 1987-06-16 Intel Corporation In-circuit emulator
JPH0668756B2 (ja) * 1985-04-19 1994-08-31 株式会社日立製作所 回路自動変換方法
DE3520003A1 (de) * 1985-06-04 1986-12-04 Texas Instruments Deutschland Gmbh, 8050 Freising Elektrisch programmierbare verknuepfungsmatrix
DE3630835C2 (de) 1985-09-11 1995-03-16 Pilkington Micro Electronics Integrierte Halbleiterkreisanordnungen und Systeme
US4725835A (en) * 1985-09-13 1988-02-16 T-Bar Incorporated Time multiplexed bus matrix switching system
JPH0756656B2 (ja) * 1985-09-26 1995-06-14 株式会社日立製作所 ゲ−ト論理自動更新方法
JPS6274158A (ja) * 1985-09-27 1987-04-04 Hitachi Ltd 回路変換方式
US4722084A (en) * 1985-10-02 1988-01-26 Itt Corporation Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits
ATE77184T1 (de) * 1985-10-23 1992-06-15 Pilkington Micro Electronics Integrierte geschaltete uebertragungsschaltung.
US4700187A (en) * 1985-12-02 1987-10-13 Concurrent Logic, Inc. Programmable, asynchronous logic cell and array
US4845633A (en) * 1985-12-02 1989-07-04 Apple Computer Inc. System for programming graphically a programmable, asynchronous logic cell and array
US4769817A (en) * 1986-01-31 1988-09-06 Zycad Corporation Concurrent fault simulation for logic designs
JPS62182939A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 情報処理装置の論理シミユレ−シヨン方法
JPS63137A (ja) * 1986-02-17 1988-01-05 Mitsubishi Electric Corp 配線領域決定処理装置
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits
JPH0770598B2 (ja) * 1986-03-20 1995-07-31 株式会社東芝 半導体集積回路装置の配線方法
JPH0731615B2 (ja) * 1986-04-18 1995-04-10 日本電気株式会社 情報処理装置
US4862347A (en) * 1986-04-22 1989-08-29 International Business Machine Corporation System for simulating memory arrays in a logic simulation machine
US4777606A (en) * 1986-06-05 1988-10-11 Northern Telecom Limited Method for deriving an interconnection route between elements in an interconnection medium
US4787061A (en) * 1986-06-25 1988-11-22 Ikos Systems, Inc. Dual delay mode pipelined logic simulator
US5126966A (en) 1986-06-25 1992-06-30 Ikos Systems, Inc. High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
US4787062A (en) * 1986-06-26 1988-11-22 Ikos Systems, Inc. Glitch detection by forcing the output of a simulated logic device to an undefined state
US5261116A (en) * 1986-07-02 1993-11-09 Advanced Micro Devices, Inc. Programmable, expandable controller with flexible I/O
GB8621357D0 (en) * 1986-09-04 1986-10-15 Mcallister R I Hinged barrier semiconductor integrated circuits
US5083083A (en) 1986-09-19 1992-01-21 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US4758745B1 (en) * 1986-09-19 1994-11-15 Actel Corp User programmable integrated circuit interconnect architecture and test method
US4736338A (en) * 1986-10-07 1988-04-05 Silicon Solutions Corporation Programmable look up system
JPH07120359B2 (ja) 1986-10-21 1995-12-20 日本電気株式会社 ハードウェアシミュレータにおけるシミュレーション方法
US4768196A (en) * 1986-10-28 1988-08-30 Silc Technologies, Inc. Programmable logic array
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US4786904A (en) * 1986-12-15 1988-11-22 Zoran Corporation Electronically programmable gate array having programmable interconnect lines
US4849928A (en) * 1987-01-28 1989-07-18 Hauck Lane T Logic array programmer
JPS63204441A (ja) 1987-02-20 1988-08-24 Fujitsu Ltd 論理シミユレ−シヨン専用プロセツサの処理方式
JP2699377B2 (ja) * 1987-02-25 1998-01-19 日本電気株式会社 ハードウエア論理シミユレータ
US4827427A (en) * 1987-03-05 1989-05-02 Hyduke Stanley M Instantaneous incremental compiler for producing logic circuit designs
JPS63223869A (ja) 1987-03-13 1988-09-19 Hitachi Ltd プログラム生成方法
US4965739A (en) 1987-03-26 1990-10-23 Vlsi Technology, Inc. Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected
US4908772A (en) * 1987-03-30 1990-03-13 Bell Telephone Laboratories Integrated circuits with component placement by rectilinear partitioning
US5329471A (en) 1987-06-02 1994-07-12 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US4815003A (en) * 1987-06-19 1989-03-21 General Electric Company Structured design method for high density standard cell and macrocell layout of VLSI chips
US4849904A (en) * 1987-06-19 1989-07-18 International Business Machines Corporation Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices
US5093920A (en) 1987-06-25 1992-03-03 At&T Bell Laboratories Programmable processing elements interconnected by a communication network including field operation unit for performing field operations
JPS6425399A (en) 1987-07-21 1989-01-27 Fujitsu Ltd Programmable device and its test method
FR2618624B1 (fr) * 1987-07-24 1992-04-30 Michel Servel Systeme de commutation de multiplex temporels hybrides a memoire tampon optimisee
DE3853860D1 (de) 1987-09-22 1995-06-29 Siemens Ag Vorrichtung zur Herstellung einer testkompatiblen, weitgehend fehlertoleranten Konfiguration von redundant implementierten systolischen VLSI-Systemen.
US4855669A (en) * 1987-10-07 1989-08-08 Xilinx, Inc. System for scan testing of logic circuit networks
US4901260A (en) * 1987-10-28 1990-02-13 American Telephone And Telegraph Company At&T Bell Laboratories Bounded lag distributed discrete event simulation method and apparatus
JP2541248B2 (ja) * 1987-11-20 1996-10-09 三菱電機株式会社 プログラマブル・ロジック・アレイ
FR2623653B1 (fr) 1987-11-24 1992-10-23 Sgs Thomson Microelectronics Procede de test de cellules de memoire electriquement programmable et circuit integre correspondant
JP2564344B2 (ja) 1987-12-23 1996-12-18 株式会社日立製作所 半導体集積回路の設計方式
US4922432A (en) * 1988-01-13 1990-05-01 International Chip Corporation Knowledge based method and apparatus for designing integrated circuits using functional specifications
JP2563451B2 (ja) 1988-03-10 1996-12-11 松下電器産業株式会社 論理シミュレーション方法と論理シミュレーション装置
US4931946A (en) * 1988-03-10 1990-06-05 Cirrus Logic, Inc. Programmable tiles
US5253363A (en) 1988-03-15 1993-10-12 Edward Hyman Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array
US5377123A (en) 1992-06-08 1994-12-27 Hyman; Edward Programmable logic device
US4914612A (en) * 1988-03-31 1990-04-03 International Business Machines Corporation Massively distributed simulation engine
US4854039A (en) * 1988-05-04 1989-08-08 The Technology Congress, Ltd. Prototype circuit board and method of testing
US5003487A (en) 1988-06-28 1991-03-26 International Business Machines Corporation Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis
US4901259A (en) * 1988-08-15 1990-02-13 Lsi Logic Corporation Asic emulator
JPH0650514B2 (ja) 1988-09-30 1994-06-29 日本電気株式会社 論理回路の自動合成方式
US5452231A (en) 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
WO1990004233A1 (en) 1988-10-05 1990-04-19 Mentor Graphics Corporation Method of using electronically reconfigurable gate array logic and apparatus formed thereby
US5109353A (en) 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5329470A (en) 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5140526A (en) 1989-01-06 1992-08-18 Minc Incorporated Partitioning of Boolean logic equations into physical logic devices
GB8902982D0 (en) 1989-02-10 1989-03-30 Plessey Co Plc Machine for circuit design
US5031129A (en) 1989-05-12 1991-07-09 Alcatel Na Network Systems Corp. Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same
US5051938A (en) 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
US5172011A (en) 1989-06-30 1992-12-15 Digital Equipment Corporation Latch circuit and method with complementary clocking and level sensitive scan capability
US5068812A (en) 1989-07-18 1991-11-26 Vlsi Technology, Inc. Event-controlled LCC stimulation
US5231588A (en) 1989-08-15 1993-07-27 Advanced Micro Devices, Inc. Programmable gate array with logic cells having symmetrical input/output structures
US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5644496A (en) * 1989-08-15 1997-07-01 Advanced Micro Devices, Inc. Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
US5377124A (en) 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
US5621650A (en) * 1989-10-30 1997-04-15 Advanced Micro Devices, Inc. Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
US5081602A (en) 1989-11-07 1992-01-14 Amp Incorporated Computer simulator for electrical connectors
JPH03180976A (ja) 1989-12-11 1991-08-06 Hitachi Ltd 入出力端子割付方法
US5128871A (en) 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US5084824A (en) 1990-03-29 1992-01-28 National Semiconductor Corporation Simulation model generation from a physical data base of a combinatorial circuit
EP0453171A3 (en) 1990-04-18 1992-11-19 Quickturn Systems Inc Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5259006A (en) 1990-04-18 1993-11-02 Quickturn Systems, Incorporated Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5276854A (en) 1990-08-17 1994-01-04 Cray Research, Inc. Method of multiple CPU logic simulation
US5224056A (en) 1991-10-30 1993-06-29 Xilinx, Inc. Logic placement using positionally asymmetrical partitioning algorithm
US5345580A (en) 1990-11-29 1994-09-06 Kabushiki Kaisha Toshiba Microprocessor device and emulator device thereof
FR2670299B1 (fr) 1990-12-07 1993-01-22 Thomson Composants Militaires Circuit integre avec controleur de test peripherique.
US5114353A (en) 1991-03-01 1992-05-19 Quickturn Systems, Incorporated Multiple connector arrangement for printed circuit board interconnection
US5321828A (en) 1991-06-07 1994-06-14 Step Engineering High speed microcomputer in-circuit emulator
JP2941135B2 (ja) 1992-01-24 1999-08-25 富士通株式会社 疑似ｌｓｉ装置及びそれを用いたデバッグ装置
US5475830A (en) 1992-01-31 1995-12-12 Quickturn Design Systems, Inc. Structure and method for providing a reconfigurable emulation circuit without hold time violations
US5475624A (en) 1992-04-30 1995-12-12 Schlumberger Technologies, Inc. Test generation by environment emulation
JP3620860B2 (ja) 1992-06-05 2005-02-16 株式会社メガチップス シミュレーション装置
US5352123A (en) 1992-06-08 1994-10-04 Quickturn Systems, Incorporated Switching midplane and interconnection system for interconnecting large numbers of signals
US5339262A (en) 1992-07-10 1994-08-16 Lsi Logic Corporation Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC
US5331571A (en) 1992-07-22 1994-07-19 Nec Electronics, Inc. Testing and emulation of integrated circuits
WO1994003856A1 (en) 1992-08-07 1994-02-17 Massachusetts Institute Of Technology Column-associative cache
US5572710A (en) 1992-09-11 1996-11-05 Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
US5425036A (en) 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5452239A (en) 1993-01-29 1995-09-19 Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
US5483178A (en) 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5381058A (en) * 1993-05-21 1995-01-10 At&T Corp. FPGA having PFU with programmable output driver inputs
TW253031B (de) * 1993-12-27 1995-08-01 At & T Corp
US5448522A (en) 1994-03-24 1995-09-05 Quickturn Design Systems, Inc. Multi-port memory emulation using tag registers
US5761484A (en) * 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5426378A (en) * 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
US5551013A (en) 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
WO1996013902A1 (en) 1994-11-01 1996-05-09 Virtual Machine Works, Inc. Programmable multiplexing input/output port
US5659716A (en) 1994-11-23 1997-08-19 Virtual Machine Works, Inc. Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
US6049223A (en) * 1995-03-22 2000-04-11 Altera Corporation Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
US5649176A (en) 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5574388A (en) 1995-10-13 1996-11-12 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage programmable interconnect network
US5754827A (en) * 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
US5804986A (en) * 1995-12-29 1998-09-08 Cypress Semiconductor Corp. Memory in a programmable logic device
US5977791A (en) * 1996-04-15 1999-11-02 Altera Corporation Embedded memory block with FIFO mode for programmable logic device
US5801955A (en) * 1996-05-31 1998-09-01 Mentor Graphics Corporation Method and apparatus for removing timing hazards in a circuit design
US5841967A (en) 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US6535505B1 (en) * 1998-09-30 2003-03-18 Cisco Technology, Inc. Method and apparatus for providing a time-division multiplexing (TDM) interface among a high-speed data stream and multiple processors

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US6732068B2 (en) 2004-05-04
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