DE69826863D1 - Verfahren und vorrichtung zur abstimmung eines zur verrieglung digitaler signalen gebrauchten taktsignals und speichervorrichtung die sie verwendet - Google Patents
Verfahren und vorrichtung zur abstimmung eines zur verrieglung digitaler signalen gebrauchten taktsignals und speichervorrichtung die sie verwendetInfo
- Publication number
- DE69826863D1 DE69826863D1 DE69826863T DE69826863T DE69826863D1 DE 69826863 D1 DE69826863 D1 DE 69826863D1 DE 69826863 T DE69826863 T DE 69826863T DE 69826863 T DE69826863 T DE 69826863T DE 69826863 D1 DE69826863 D1 DE 69826863D1
- Authority
- DE
- Germany
- Prior art keywords
- clock signal
- internal clock
- captured
- phase
- initialization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000011156 evaluation Methods 0.000 abstract 1
- 230000007704 transition Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US890055 | 1997-07-09 | ||
| US08/890,055 US5953284A (en) | 1997-07-09 | 1997-07-09 | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
| PCT/US1998/012656 WO1999003106A1 (en) | 1997-07-09 | 1998-07-02 | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69826863D1 true DE69826863D1 (de) | 2004-11-11 |
| DE69826863T2 DE69826863T2 (de) | 2005-10-20 |
Family
ID=25396185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69826863T Expired - Lifetime DE69826863T2 (de) | 1997-07-09 | 1998-07-02 | Verfahren und vorrichtung zur abstimmung eines zur verrieglung digitaler signalen gebrauchten taktsignals und speichervorrichtung die sie verwendet |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US5953284A (de) |
| EP (1) | EP0995196B1 (de) |
| AT (1) | ATE279007T1 (de) |
| AU (1) | AU8373898A (de) |
| DE (1) | DE69826863T2 (de) |
| TW (1) | TW452682B (de) |
| WO (1) | WO1999003106A1 (de) |
Families Citing this family (112)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
| US5946244A (en) | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
| US6173432B1 (en) | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
| US5926047A (en) * | 1997-08-29 | 1999-07-20 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
| US6000022A (en) | 1997-10-10 | 1999-12-07 | Micron Technology, Inc. | Method and apparatus for coupling signals between two circuits operating in different clock domains |
| US5982213A (en) * | 1997-11-14 | 1999-11-09 | Texas Instruments Incorporated | Digital phase lock loop |
| US6487647B1 (en) * | 1997-12-29 | 2002-11-26 | Intel Corporation | Adaptive memory interface timing generation |
| US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
| US6253333B1 (en) * | 1998-03-23 | 2001-06-26 | International Business Machines Corporation | Apparatus and method for testing programmable delays |
| JP2000036192A (ja) * | 1998-07-17 | 2000-02-02 | Fujitsu Ltd | 半導体集積回路 |
| US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
| US6279090B1 (en) | 1998-09-03 | 2001-08-21 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device |
| US6434684B1 (en) * | 1998-09-03 | 2002-08-13 | Micron Technology, Inc. | Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same |
| US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
| US6128749A (en) * | 1998-11-03 | 2000-10-03 | Intel Corporation | Cross-clock domain data transfer method and apparatus |
| US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
| US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
| KR100359157B1 (ko) * | 1998-12-30 | 2003-01-24 | 주식회사 하이닉스반도체 | 라이트 명령어 레이턴시회로 및 그 제어방법 |
| KR100295056B1 (ko) * | 1999-01-27 | 2001-07-12 | 윤종용 | 지연동기루프 및 방법 |
| US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
| JP2001068650A (ja) * | 1999-08-30 | 2001-03-16 | Hitachi Ltd | 半導体集積回路装置 |
| US7051130B1 (en) | 1999-10-19 | 2006-05-23 | Rambus Inc. | Integrated circuit device that stores a value representative of a drive strength setting |
| US6646953B1 (en) * | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
| US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
| US6321282B1 (en) | 1999-10-19 | 2001-11-20 | Rambus Inc. | Apparatus and method for topography dependent signaling |
| US6333893B1 (en) * | 2000-08-21 | 2001-12-25 | Micron Technology, Inc. | Method and apparatus for crossing clock domain boundaries |
| US6704828B1 (en) * | 2000-08-31 | 2004-03-09 | Micron Technology, Inc. | System and method for implementing data pre-fetch having reduced data lines and/or higher data rates |
| GB2384411B (en) * | 2000-10-06 | 2003-12-17 | Flextronics Semiconductor Desi | Coherent expandable high speed interface |
| GB2370450B (en) * | 2000-12-19 | 2004-07-07 | Voxsurf Ltd | Messaging protocol |
| FR2818424B1 (fr) * | 2000-12-20 | 2003-02-28 | St Microelectronics Sa | Procede et systeme d'ajustement d'une temporisation interne ou d'une reference associee dans un circuit integre et circuit integre correspondant |
| US7079775B2 (en) | 2001-02-05 | 2006-07-18 | Finisar Corporation | Integrated memory mapped controller circuit for fiber optics transceiver |
| US6535038B2 (en) | 2001-03-09 | 2003-03-18 | Micron Technology, Inc. | Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices |
| US6763444B2 (en) | 2001-05-08 | 2004-07-13 | Micron Technology, Inc. | Read/write timing calibration of a memory array using a row or a redundant row |
| US6801989B2 (en) * | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
| US6618283B2 (en) * | 2001-08-29 | 2003-09-09 | Micron Technology, Inc. | System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal |
| US6779096B1 (en) * | 2001-09-29 | 2004-08-17 | Apple Computer, Inc. | Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains |
| DE10149192B4 (de) * | 2001-10-05 | 2005-07-14 | Infineon Technologies Ag | Vorrichtung zum Erzeugen von Speicher-internen Befehlssignalen aus einem Speicheroperationsbefehl |
| US6920540B2 (en) | 2001-10-22 | 2005-07-19 | Rambus Inc. | Timing calibration apparatus and method for a memory device signaling system |
| US6922091B2 (en) | 2002-09-03 | 2005-07-26 | Rambus Inc. | Locked loop circuit with clock hold function |
| US6952123B2 (en) | 2002-03-22 | 2005-10-04 | Rambus Inc. | System with dual rail regulated locked loop |
| US6759881B2 (en) * | 2002-03-22 | 2004-07-06 | Rambus Inc. | System with phase jumping locked loop circuit |
| US6911853B2 (en) * | 2002-03-22 | 2005-06-28 | Rambus Inc. | Locked loop with dual rail regulation |
| US7135903B2 (en) * | 2002-09-03 | 2006-11-14 | Rambus Inc. | Phase jumping locked loop circuit |
| KR100510063B1 (ko) * | 2002-12-24 | 2005-08-26 | 주식회사 하이닉스반도체 | 레지스터 제어 지연고정루프 |
| KR100495908B1 (ko) * | 2003-04-29 | 2005-06-17 | 주식회사 하이닉스반도체 | 개선된 출력제어신호를 생성할 수 있는 반도체 집적회로및 개선된 출력제어신호발생방법 |
| US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
| KR20050022798A (ko) * | 2003-08-30 | 2005-03-08 | 주식회사 이즈텍 | 유전자 어휘 분류체계를 이용하여 바이오 칩을 분석하기위한 시스템 및 그 방법 |
| US7234070B2 (en) * | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
| US7065666B2 (en) | 2003-11-13 | 2006-06-20 | Micron Technology, Inc. | Apparatus and method for generating a delayed clock signal |
| US7119583B2 (en) * | 2004-03-31 | 2006-10-10 | Micron Technology, Inc. | Phase detector and method having hysteresis characteristics |
| JP4732709B2 (ja) * | 2004-05-20 | 2011-07-27 | 株式会社半導体エネルギー研究所 | シフトレジスタ及びそれを用いた電子機器 |
| US7142477B1 (en) * | 2004-06-18 | 2006-11-28 | Cypress Semiconductor Corp. | Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses |
| US7072378B2 (en) * | 2004-08-25 | 2006-07-04 | Battelle Energy Alliance, Llc | Induction heating apparatus and methods for selectively energizing an inductor in response to a measured electrical characteristic that is at least partially a function of a temperature of a material being heated |
| US7085305B2 (en) * | 2004-08-25 | 2006-08-01 | Battelle Energy Alliance, Llc | Induction heating apparatus and methods of operation thereof |
| US7126874B2 (en) * | 2004-08-31 | 2006-10-24 | Micron Technology, Inc. | Memory system and method for strobing data, command and address signals |
| KR100604904B1 (ko) * | 2004-10-02 | 2006-07-28 | 삼성전자주식회사 | 스캔 입력을 갖는 플립 플롭 회로 |
| US7417907B1 (en) | 2004-12-23 | 2008-08-26 | Sun Microsystems, Inc. | Systems and methods for resolving memory address collisions |
| US7752410B1 (en) * | 2005-01-14 | 2010-07-06 | Oracle America, Inc. | System and method for accessing data in a multicycle operations cache |
| US7493461B1 (en) * | 2005-01-20 | 2009-02-17 | Altera Corporation | Dynamic phase alignment for resynchronization of captured data |
| US7496167B2 (en) * | 2005-01-20 | 2009-02-24 | Marvell World Trade Ltd. | Storage efficient sliding window sum |
| US7609567B2 (en) * | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
| US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
| US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
| US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
| US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
| US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
| US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
| US8090897B2 (en) * | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
| US8055833B2 (en) * | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
| US7386656B2 (en) * | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
| US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
| US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
| US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
| US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
| US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
| US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
| US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
| US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
| US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
| US8327104B2 (en) * | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
| US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
| US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
| US20080028136A1 (en) * | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
| US7590796B2 (en) * | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
| US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
| US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
| US8060774B2 (en) * | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
| US7236028B1 (en) * | 2005-07-22 | 2007-06-26 | National Semiconductor Corporation | Adaptive frequency variable delay-locked loop |
| GB2444663B (en) | 2005-09-02 | 2011-12-07 | Metaram Inc | Methods and apparatus of stacking drams |
| US7549092B2 (en) * | 2005-09-29 | 2009-06-16 | Hynix Semiconductor, Inc. | Output controller with test unit |
| US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
| US7706996B2 (en) * | 2006-04-21 | 2010-04-27 | Altera Corporation | Write-side calibration for data interface |
| US7509223B2 (en) * | 2006-04-21 | 2009-03-24 | Altera Corporation | Read-side calibration for data interface |
| US20080028137A1 (en) * | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and Apparatus For Refresh Management of Memory Modules |
| US7724589B2 (en) * | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
| US7688928B2 (en) * | 2006-09-05 | 2010-03-30 | Lsi Corporation | Duty cycle counting phase calibration scheme of an input/output (I/O) interface |
| US7928770B1 (en) | 2006-11-06 | 2011-04-19 | Altera Corporation | I/O block for high performance memory interfaces |
| US7423456B2 (en) * | 2006-12-01 | 2008-09-09 | Micron Technology, Inc. | Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods |
| EP2109862A4 (de) * | 2007-02-16 | 2010-08-04 | Mosaid Technologies Inc | Halbleiterbauelement und verfahren zur veringerung des stromverbrauchs in einem system mit verbundenen bauelementen |
| US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
| US7816960B2 (en) * | 2007-08-09 | 2010-10-19 | Qualcomm Incorporated | Circuit device and method of measuring clock jitter |
| US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
| US8204166B2 (en) | 2007-10-08 | 2012-06-19 | Freescale Semiconductor, Inc. | Clock circuit with clock transfer capability and method |
| US8239715B2 (en) * | 2008-06-24 | 2012-08-07 | International Business Machines Corporation | Method and apparatus for a robust embedded interface |
| US7937632B2 (en) * | 2008-06-24 | 2011-05-03 | International Business Machines Corporation | Design structure and apparatus for a robust embedded interface |
| US8074040B2 (en) * | 2008-09-23 | 2011-12-06 | Mediatek Inc. | Flash device and method for improving performance of flash device |
| US8149643B2 (en) | 2008-10-23 | 2012-04-03 | Cypress Semiconductor Corporation | Memory device and method |
| EP2441007A1 (de) * | 2009-06-09 | 2012-04-18 | Google, Inc. | Programmierung von dimm-abschlusswiderstandswerten |
| WO2011130007A1 (en) * | 2010-04-14 | 2011-10-20 | Rambus Inc. | Levelization of memory interface for communicating with multiple memory devices |
| KR101930779B1 (ko) * | 2012-04-04 | 2018-12-20 | 에스케이하이닉스 주식회사 | 반도체 메모리 회로 및 이를 이용한 데이터 처리 시스템 |
| US10944387B2 (en) | 2019-06-14 | 2021-03-09 | Stmicroelectronics International N.V. | Programmable delay circuit |
| CN113808634B (zh) * | 2020-06-11 | 2024-02-27 | 华邦电子股份有限公司 | 延迟锁相回路装置及其更新方法 |
Family Cites Families (117)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3633174A (en) * | 1970-04-14 | 1972-01-04 | Us Navy | Memory system having self-adjusting strobe timing |
| US4096402A (en) * | 1975-12-29 | 1978-06-20 | Mostek Corporation | MOSFET buffer for TTL logic input and method of operation |
| US4096403A (en) * | 1976-06-28 | 1978-06-20 | Electric Power Research Institute, Inc. | Superconducting hybrid magnetic flux pump |
| US4077016A (en) * | 1977-02-22 | 1978-02-28 | Ncr Corporation | Apparatus and method for inhibiting false locking of a phase-locked loop |
| US4404474A (en) * | 1981-02-06 | 1983-09-13 | Rca Corporation | Active load pulse generating circuit |
| US4481625A (en) * | 1981-10-21 | 1984-11-06 | Elxsi | High speed data bus system |
| US4511846A (en) * | 1982-05-24 | 1985-04-16 | Fairchild Camera And Instrument Corporation | Deskewing time-critical signals in automatic test equipment |
| US4514647A (en) * | 1983-08-01 | 1985-04-30 | At&T Bell Laboratories | Chipset synchronization arrangement |
| US4687951A (en) * | 1984-10-29 | 1987-08-18 | Texas Instruments Incorporated | Fuse link for varying chip operating parameters |
| US4600895A (en) * | 1985-04-26 | 1986-07-15 | Minnesota Mining And Manufacturing Company | Precision phase synchronization of free-running oscillator output signal to reference signal |
| US4638187A (en) * | 1985-10-01 | 1987-01-20 | Vtc Incorporated | CMOS output buffer providing high drive current with minimum output signal distortion |
| GB2184622B (en) * | 1985-12-23 | 1989-10-18 | Philips Nv | Outputbuffer and control circuit providing limited current rate at the output |
| JPS6337894A (ja) * | 1986-07-30 | 1988-02-18 | Mitsubishi Electric Corp | ランダムアクセスメモリ |
| US4773085A (en) * | 1987-06-12 | 1988-09-20 | Bell Communications Research, Inc. | Phase and frequency detector circuits |
| US5086500A (en) * | 1987-08-07 | 1992-02-04 | Tektronix, Inc. | Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits |
| US4893087A (en) * | 1988-01-07 | 1990-01-09 | Motorola, Inc. | Low voltage and low power frequency synthesizer |
| KR0141494B1 (ko) * | 1988-01-28 | 1998-07-15 | 미다 가쓰시게 | 레벨시프트회로를 사용한 고속센스 방식의 반도체장치 |
| US4902986B1 (en) * | 1989-01-30 | 1998-09-01 | Credence Systems Corp | Phased locked loop to provide precise frequency and phase tracking of two signals |
| US5020023A (en) * | 1989-02-23 | 1991-05-28 | International Business Machines Corporation | Automatic vernier synchronization of skewed data streams |
| US4958088A (en) * | 1989-06-19 | 1990-09-18 | Micron Technology, Inc. | Low power three-stage CMOS input buffer with controlled switching |
| US5165046A (en) * | 1989-11-06 | 1992-11-17 | Micron Technology, Inc. | High speed CMOS driver circuit |
| JP2671538B2 (ja) * | 1990-01-17 | 1997-10-29 | 松下電器産業株式会社 | 入力バッファ回路 |
| JP2787725B2 (ja) * | 1990-02-14 | 1998-08-20 | 第一電子工業株式会社 | データ・クロックのタイミング合わせ回路 |
| US5408640A (en) * | 1990-02-21 | 1995-04-18 | Digital Equipment Corporation | Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes |
| US5239206A (en) * | 1990-03-06 | 1993-08-24 | Advanced Micro Devices, Inc. | Synchronous circuit with clock skew compensating function and circuits utilizing same |
| US5165049A (en) * | 1990-04-02 | 1992-11-17 | Inductotherm Corp. | Phase difference control circuit for induction furnace power supply |
| IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
| US5243703A (en) * | 1990-04-18 | 1993-09-07 | Rambus, Inc. | Apparatus for synchronously generating clock signals in a data processing system |
| US5038115A (en) * | 1990-05-29 | 1991-08-06 | Myers Glen A | Method and apparatus for frequency independent phase tracking of input signals in receiving systems and the like |
| US5134311A (en) * | 1990-06-07 | 1992-07-28 | International Business Machines Corporation | Self-adjusting impedance matching driver |
| JP2740063B2 (ja) | 1990-10-15 | 1998-04-15 | 株式会社東芝 | 半導体記憶装置 |
| US5122690A (en) * | 1990-10-16 | 1992-06-16 | General Electric Company | Interface circuits including driver circuits with switching noise reduction |
| US5257294A (en) * | 1990-11-13 | 1993-10-26 | National Semiconductor Corporation | Phase-locked loop circuit and method |
| TW198135B (de) * | 1990-11-20 | 1993-01-11 | Oki Electric Ind Co Ltd | |
| US5128563A (en) * | 1990-11-28 | 1992-07-07 | Micron Technology, Inc. | CMOS bootstrapped output driver method and circuit |
| US5281865A (en) * | 1990-11-28 | 1994-01-25 | Hitachi, Ltd. | Flip-flop circuit |
| US5150186A (en) * | 1991-03-06 | 1992-09-22 | Micron Technology, Inc. | CMOS output pull-up driver |
| US5128560A (en) * | 1991-03-22 | 1992-07-07 | Micron Technology, Inc. | Boosted supply output driver circuit for driving an all N-channel output stage |
| US5220208A (en) * | 1991-04-29 | 1993-06-15 | Texas Instruments Incorporated | Circuitry and method for controlling current in an electronic circuit |
| US5256989A (en) * | 1991-05-03 | 1993-10-26 | Motorola, Inc. | Lock detection for a phase lock loop |
| US5212601A (en) * | 1991-05-03 | 1993-05-18 | Western Digital Corporation | Disk drive data synchronizer with window shift synthesis |
| US5194765A (en) * | 1991-06-28 | 1993-03-16 | At&T Bell Laboratories | Digitally controlled element sizing |
| US5276642A (en) * | 1991-07-15 | 1994-01-04 | Micron Technology, Inc. | Method for performing a split read/write operation in a dynamic random access memory |
| KR970005124B1 (ko) * | 1991-08-14 | 1997-04-12 | 가부시끼가이샤 아드반테스트 | 가변지연회로 |
| US5465076A (en) * | 1991-10-04 | 1995-11-07 | Nippondenso Co., Ltd. | Programmable delay line programmable delay circuit and digital controlled oscillator |
| US5283631A (en) * | 1991-11-01 | 1994-02-01 | Hewlett-Packard Co. | Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations |
| US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
| US5295164A (en) * | 1991-12-23 | 1994-03-15 | Apple Computer, Inc. | Apparatus for providing a system clock locked to an external clock over a wide range of frequencies |
| DE4206082C1 (de) * | 1992-02-27 | 1993-04-08 | Siemens Ag, 8000 Muenchen, De | |
| DE4345604B3 (de) * | 1992-03-06 | 2012-07-12 | Rambus Inc. | Vorrichtung zur Kommunikation mit einem DRAM |
| US5355391A (en) * | 1992-03-06 | 1994-10-11 | Rambus, Inc. | High speed bus system |
| US5278460A (en) * | 1992-04-07 | 1994-01-11 | Micron Technology, Inc. | Voltage compensating CMOS input buffer |
| US5390308A (en) * | 1992-04-15 | 1995-02-14 | Rambus, Inc. | Method and apparatus for address mapping of dynamic random access memory |
| US5254883A (en) * | 1992-04-22 | 1993-10-19 | Rambus, Inc. | Electrical current source circuitry for a bus |
| US5485490A (en) * | 1992-05-28 | 1996-01-16 | Rambus, Inc. | Method and circuitry for clock synchronization |
| US5317202A (en) * | 1992-05-28 | 1994-05-31 | Intel Corporation | Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle |
| US5268639A (en) * | 1992-06-05 | 1993-12-07 | Rambus, Inc. | Testing timing parameters of high speed integrated circuit devices |
| US5274276A (en) * | 1992-06-26 | 1993-12-28 | Micron Technology, Inc. | Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit |
| US5473274A (en) * | 1992-09-14 | 1995-12-05 | Nec America, Inc. | Local clock generator |
| FR2696061B1 (fr) * | 1992-09-22 | 1994-12-02 | Rainard Jean Luc | Procédé pour retarder temporellement un signal et circuit à retard correspondant. |
| EP0596657A3 (de) * | 1992-11-05 | 1994-12-07 | American Telephone & Telegraph | Normalisierung der sichtbaren Fortpflanzungsverzögerung. |
| US5311481A (en) * | 1992-12-17 | 1994-05-10 | Micron Technology, Inc. | Wordline driver circuit having a directly gated pull-down device |
| JP2792801B2 (ja) * | 1992-12-28 | 1998-09-03 | 三菱電機株式会社 | 半導体集積回路並びにその設計方法及び製造方法 |
| US5347559A (en) * | 1992-12-30 | 1994-09-13 | Digital Equipment Corporation | Apparatus and method of data transfer between systems using different clocks |
| US5347177A (en) * | 1993-01-14 | 1994-09-13 | Lipp Robert J | System for interconnecting VLSI circuits with transmission line characteristics |
| US5544203A (en) * | 1993-02-17 | 1996-08-06 | Texas Instruments Incorporated | Fine resolution digital delay line with coarse and fine adjustment stages |
| US5488321A (en) * | 1993-04-07 | 1996-01-30 | Rambus, Inc. | Static high speed comparator |
| US5347179A (en) * | 1993-04-15 | 1994-09-13 | Micron Semiconductor, Inc. | Inverting output driver circuit for reducing electron injection into the substrate |
| US5337285A (en) * | 1993-05-21 | 1994-08-09 | Rambus, Inc. | Method and apparatus for power control in devices |
| US5506814A (en) * | 1993-05-28 | 1996-04-09 | Micron Technology, Inc. | Video random access memory device and method implementing independent two WE nibble control |
| AU6988494A (en) * | 1993-05-28 | 1994-12-20 | Rambus Inc. | Method and apparatus for implementing refresh in a synchronous dram system |
| JP2636677B2 (ja) * | 1993-06-02 | 1997-07-30 | 日本電気株式会社 | 半導体集積回路 |
| US5511024A (en) * | 1993-06-02 | 1996-04-23 | Rambus, Inc. | Dynamic random access memory system |
| US5428311A (en) * | 1993-06-30 | 1995-06-27 | Sgs-Thomson Microelectronics, Inc. | Fuse circuitry to control the propagation delay of an IC |
| US5473639A (en) * | 1993-07-26 | 1995-12-05 | Hewlett-Packard Company | Clock recovery apparatus with means for sensing an out of lock condition |
| JP3232351B2 (ja) * | 1993-10-06 | 2001-11-26 | 三菱電機株式会社 | デジタル回路装置 |
| US5451898A (en) * | 1993-11-12 | 1995-09-19 | Rambus, Inc. | Bias circuit and differential amplifier having stabilized output swing |
| JPH07153286A (ja) * | 1993-11-30 | 1995-06-16 | Sony Corp | 半導体不揮発性記憶装置 |
| US5400283A (en) * | 1993-12-13 | 1995-03-21 | Micron Semiconductor, Inc. | RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver |
| KR0132504B1 (ko) * | 1993-12-21 | 1998-10-01 | 문정환 | 데이타 출력버퍼 |
| US5579326A (en) * | 1994-01-31 | 1996-11-26 | Sgs-Thomson Microelectronics, Inc. | Method and apparatus for programming signal timing |
| KR100393317B1 (ko) * | 1994-02-15 | 2003-10-23 | 람버스 인코포레이티드 | 지연동기루프 |
| US5424672A (en) * | 1994-02-24 | 1995-06-13 | Micron Semiconductor, Inc. | Low current redundancy fuse assembly |
| US5440514A (en) * | 1994-03-08 | 1995-08-08 | Motorola Inc. | Write control for a memory using a delay locked loop |
| US5554946A (en) * | 1994-04-08 | 1996-09-10 | International Business Machines Corporation | Timing signal generator |
| JP3553639B2 (ja) * | 1994-05-12 | 2004-08-11 | アジレント・テクノロジーズ・インク | タイミング調整回路 |
| JP2541504B2 (ja) * | 1994-05-27 | 1996-10-09 | 日本電気株式会社 | クロック位相自動調整方式およびクロック位相自動調整機能付二重化デ―タ処理装置 |
| US5457407A (en) * | 1994-07-06 | 1995-10-10 | Sony Electronics Inc. | Binary weighted reference circuit for a variable impedance output buffer |
| JP3537500B2 (ja) | 1994-08-16 | 2004-06-14 | バー−ブラウン・コーポレーション | インバータ装置 |
| JP3176228B2 (ja) * | 1994-08-23 | 2001-06-11 | シャープ株式会社 | 半導体記憶装置 |
| GB9417266D0 (en) * | 1994-08-26 | 1994-10-19 | Inmos Ltd | Testing a non-volatile memory |
| JPH08139572A (ja) * | 1994-11-07 | 1996-05-31 | Mitsubishi Electric Corp | ラッチ回路 |
| US5497127A (en) * | 1994-12-14 | 1996-03-05 | David Sarnoff Research Center, Inc. | Wide frequency range CMOS relaxation oscillator with variable hysteresis |
| US5577236A (en) * | 1994-12-30 | 1996-11-19 | International Business Machines Corporation | Memory controller for reading data from synchronous RAM |
| US5489864A (en) * | 1995-02-24 | 1996-02-06 | Intel Corporation | Delay interpolation circuitry |
| US5578940A (en) * | 1995-04-04 | 1996-11-26 | Rambus, Inc. | Modular bus with single or double parallel termination |
| US5621690A (en) * | 1995-04-28 | 1997-04-15 | Intel Corporation | Nonvolatile memory blocking architecture and redundancy |
| JP3386924B2 (ja) * | 1995-05-22 | 2003-03-17 | 株式会社日立製作所 | 半導体装置 |
| US5581197A (en) * | 1995-05-31 | 1996-12-03 | Hewlett-Packard Co. | Method of programming a desired source resistance for a driver stage |
| US5576645A (en) * | 1995-06-05 | 1996-11-19 | Hughes Aircraft Company | Sample and hold flip-flop for CMOS logic |
| US5636173A (en) * | 1995-06-07 | 1997-06-03 | Micron Technology, Inc. | Auto-precharge during bank selection |
| JP3403551B2 (ja) | 1995-07-14 | 2003-05-06 | 沖電気工業株式会社 | クロック分配回路 |
| US5621340A (en) * | 1995-08-02 | 1997-04-15 | Rambus Inc. | Differential comparator for amplifying small swing signals to a full swing output |
| JP3252666B2 (ja) * | 1995-08-14 | 2002-02-04 | 日本電気株式会社 | 半導体記憶装置 |
| US5578941A (en) * | 1995-08-23 | 1996-11-26 | Micron Technology, Inc. | Voltage compensating CMOS input buffer circuit |
| US5692165A (en) * | 1995-09-12 | 1997-11-25 | Micron Electronics Inc. | Memory controller with low skew control signal |
| JP3408030B2 (ja) | 1995-09-21 | 2003-05-19 | 日本プレシジョン・サーキッツ株式会社 | 位相比較器 |
| US5767715A (en) | 1995-09-29 | 1998-06-16 | Siemens Medical Systems, Inc. | Method and apparatus for generating timing pulses accurately skewed relative to clock |
| JP3183321B2 (ja) | 1995-11-10 | 2001-07-09 | 日本電気株式会社 | 半導体記憶装置 |
| US5594690A (en) * | 1995-12-15 | 1997-01-14 | Unisys Corporation | Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator |
| US5636174A (en) * | 1996-01-11 | 1997-06-03 | Cirrus Logic, Inc. | Fast cycle time-low latency dynamic random access memories and systems and methods using the same |
| US5719508A (en) | 1996-02-01 | 1998-02-17 | Northern Telecom, Ltd. | Loss of lock detector for master timing generator |
| US5712580A (en) | 1996-02-14 | 1998-01-27 | International Business Machines Corporation | Linear phase detector for half-speed quadrature clocking architecture |
| US5627791A (en) * | 1996-02-16 | 1997-05-06 | Micron Technology, Inc. | Multiple bank memory with auto refresh to specified bank |
| US5668763A (en) * | 1996-02-26 | 1997-09-16 | Fujitsu Limited | Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks |
| US5621739A (en) * | 1996-05-07 | 1997-04-15 | Intel Corporation | Method and apparatus for buffer self-test and characterization |
| JPH1069769A (ja) | 1996-08-29 | 1998-03-10 | Fujitsu Ltd | 半導体集積回路 |
-
1997
- 1997-07-09 US US08/890,055 patent/US5953284A/en not_active Expired - Lifetime
-
1998
- 1998-07-02 EP EP98934145A patent/EP0995196B1/de not_active Expired - Lifetime
- 1998-07-02 WO PCT/US1998/012656 patent/WO1999003106A1/en active IP Right Grant
- 1998-07-02 DE DE69826863T patent/DE69826863T2/de not_active Expired - Lifetime
- 1998-07-02 AT AT98934145T patent/ATE279007T1/de not_active IP Right Cessation
- 1998-07-02 AU AU83738/98A patent/AU8373898A/en not_active Abandoned
- 1998-07-09 TW TW087111107A patent/TW452682B/zh not_active IP Right Cessation
-
1999
- 1999-02-10 US US09/248,194 patent/US6026050A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| AU8373898A (en) | 1999-02-08 |
| EP0995196B1 (de) | 2004-10-06 |
| EP0995196A1 (de) | 2000-04-26 |
| US5953284A (en) | 1999-09-14 |
| ATE279007T1 (de) | 2004-10-15 |
| US6026050A (en) | 2000-02-15 |
| WO1999003106A1 (en) | 1999-01-21 |
| DE69826863T2 (de) | 2005-10-20 |
| TW452682B (en) | 2001-09-01 |
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