DE69834232D1 - Verfahren zum Verbinden von kristallinen Substraten mit unterschiedlichen Kristallgitter - Google Patents

Verfahren zum Verbinden von kristallinen Substraten mit unterschiedlichen Kristallgitter

Info

Publication number
DE69834232D1
DE69834232D1 DE69834232T DE69834232T DE69834232D1 DE 69834232 D1 DE69834232 D1 DE 69834232D1 DE 69834232 T DE69834232 T DE 69834232T DE 69834232 T DE69834232 T DE 69834232T DE 69834232 D1 DE69834232 D1 DE 69834232D1
Authority
DE
Germany
Prior art keywords
joining
different crystal
crystal lattices
crystalline substrates
crystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69834232T
Other languages
English (en)
Other versions
DE69834232T2 (de
Inventor
Barry Franklin Levine
Christopher James Pinzone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Optoelectronics Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Optoelectronics Guardian Corp filed Critical Agere Systems Optoelectronics Guardian Corp
Application granted granted Critical
Publication of DE69834232D1 publication Critical patent/DE69834232D1/de
Publication of DE69834232T2 publication Critical patent/DE69834232T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
DE69834232T 1997-10-08 1998-09-29 Verfahren zum Verbinden von kristallinen Substraten mit unterschiedlichen Kristallgitter Expired - Lifetime DE69834232T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/947,175 US5966622A (en) 1997-10-08 1997-10-08 Process for bonding crystalline substrates with different crystal lattices
US947175 1997-10-08

Publications (2)

Publication Number Publication Date
DE69834232D1 true DE69834232D1 (de) 2006-05-24
DE69834232T2 DE69834232T2 (de) 2007-03-08

Family

ID=25485666

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69834232T Expired - Lifetime DE69834232T2 (de) 1997-10-08 1998-09-29 Verfahren zum Verbinden von kristallinen Substraten mit unterschiedlichen Kristallgitter

Country Status (6)

Country Link
US (1) US5966622A (de)
EP (1) EP0908933B1 (de)
JP (1) JPH11214732A (de)
KR (1) KR100390670B1 (de)
DE (1) DE69834232T2 (de)
TW (1) TW390040B (de)

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US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
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US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
DE60124766T2 (de) 2000-08-04 2007-10-11 Amberwave Systems Corp. Siliziumwafer mit monolithischen optoelektronischen komponenten
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6940089B2 (en) 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US6897138B2 (en) * 2001-06-25 2005-05-24 Toyoda Gosei Co., Ltd. Method and apparatus for producing group III nitride compound semiconductor
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AU2002366856A1 (en) * 2001-12-21 2003-07-09 Aixtron Ag Method for depositing iii-v semiconductor layers on a non-iii-v substrate
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US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
JP4659732B2 (ja) 2003-01-27 2011-03-30 台湾積體電路製造股▲ふん▼有限公司 半導体層を形成する方法
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US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7895548B2 (en) * 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system
US20090108408A1 (en) * 2007-10-29 2009-04-30 Synopsys, Inc. Method for Trapping Implant Damage in a Semiconductor Substrate
US9472423B2 (en) * 2007-10-30 2016-10-18 Synopsys, Inc. Method for suppressing lattice defects in a semiconductor substrate
KR101199301B1 (ko) 2008-12-05 2012-11-09 한국전자통신연구원 확산 영역을 포함하는 화합물 반도체 소자의 형성 방법
CN102136672B (zh) * 2011-03-15 2012-12-26 上海交通大学 基于碳化硅包层板条的激光器冷却装置
US10543662B2 (en) 2012-02-08 2020-01-28 Corning Incorporated Device modified substrate article and methods for making
CN102769074B (zh) * 2012-08-08 2014-11-05 天津蓝天太阳科技有限公司 基于竖直微气孔的Si与GaInAs低温键合方法
US10086584B2 (en) 2012-12-13 2018-10-02 Corning Incorporated Glass articles and methods for controlled bonding of glass sheets with carriers
US10014177B2 (en) 2012-12-13 2018-07-03 Corning Incorporated Methods for processing electronic devices
US9340443B2 (en) 2012-12-13 2016-05-17 Corning Incorporated Bulk annealing of glass sheets
TWI617437B (zh) 2012-12-13 2018-03-11 康寧公司 促進控制薄片與載體間接合之處理
US10510576B2 (en) 2013-10-14 2019-12-17 Corning Incorporated Carrier-bonding methods and articles for semiconductor and interposer processing
WO2015112958A1 (en) 2014-01-27 2015-07-30 Corning Incorporated Articles and methods for controlled bonding of thin sheets with carriers
EP3129221A1 (de) 2014-04-09 2017-02-15 Corning Incorporated Vorrichtungsmodifizierter substratartikel und herstellungsverfahren
JP2018524201A (ja) 2015-05-19 2018-08-30 コーニング インコーポレイテッド シートをキャリアと結合するための物品および方法
EP3313799B1 (de) 2015-06-26 2022-09-07 Corning Incorporated Verfahren und artikel mit einem bogen und einem träger
FR3043406B1 (fr) * 2015-11-09 2019-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede d'assemblage de substrats par collage de surfaces de phosphure d'indium
TW201825623A (zh) 2016-08-30 2018-07-16 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI821867B (zh) 2016-08-31 2023-11-11 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
WO2019118660A1 (en) 2017-12-15 2019-06-20 Corning Incorporated Method for treating a substrate and method for making articles comprising bonded sheets
US20220238747A1 (en) * 2021-01-28 2022-07-28 Solaero Technologies Corp. Inverted metamorphic multijunction solar cell

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US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
JPH05275332A (ja) * 1992-03-26 1993-10-22 Shimadzu Corp ヘテロエピタキシャル膜の製膜方法
US5346848A (en) * 1993-06-01 1994-09-13 Motorola, Inc. Method of bonding silicon and III-V semiconductor materials
US5391257A (en) * 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
JP2669368B2 (ja) * 1994-03-16 1997-10-27 日本電気株式会社 Ｓｉ基板上化合物半導体積層構造の製造方法

Also Published As

Publication number Publication date
DE69834232T2 (de) 2007-03-08
KR100390670B1 (ko) 2003-08-19
JPH11214732A (ja) 1999-08-06
KR19990036941A (ko) 1999-05-25
US5966622A (en) 1999-10-12
EP0908933A1 (de) 1999-04-14
EP0908933B1 (de) 2006-04-19
TW390040B (en) 2000-05-11

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Legal Events

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