DE69836401D1 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents
Verfahren zur Herstellung einer HalbleiteranordnungInfo
- Publication number
- DE69836401D1 DE69836401D1 DE69836401T DE69836401T DE69836401D1 DE 69836401 D1 DE69836401 D1 DE 69836401D1 DE 69836401 T DE69836401 T DE 69836401T DE 69836401 T DE69836401 T DE 69836401T DE 69836401 D1 DE69836401 D1 DE 69836401D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/902—Capping layer
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US5714897P | 1997-08-28 | 1997-08-28 | |
US57148P | 1997-08-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69836401D1 true DE69836401D1 (de) | 2006-12-28 |
DE69836401T2 DE69836401T2 (de) | 2007-05-24 |
Family
ID=22008797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69836401T Expired - Lifetime DE69836401T2 (de) | 1997-08-28 | 1998-08-27 | Verfahren zur Herstellung einer Halbleiteranordnung |
Country Status (4)
Country | Link |
---|---|
US (1) | US6261887B1 (de) |
EP (1) | EP0899784B1 (de) |
JP (1) | JPH11126829A (de) |
DE (1) | DE69836401T2 (de) |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6066533A (en) * | 1998-09-29 | 2000-05-23 | Advanced Micro Devices, Inc. | MOS transistor with dual metal gate structure |
JP3023355B1 (ja) | 1998-12-25 | 2000-03-21 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP3264264B2 (ja) * | 1999-03-01 | 2002-03-11 | 日本電気株式会社 | 相補型集積回路とその製造方法 |
GB2358737A (en) * | 1999-03-01 | 2001-08-01 | Nec Corp | Methods for manufacturing a complimentary integrated circuit |
JP4491858B2 (ja) * | 1999-07-06 | 2010-06-30 | ソニー株式会社 | 半導体装置の製造方法 |
US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
JP2003523630A (ja) * | 2000-02-17 | 2003-08-05 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | シリコン・ゲルマニウム(Si1−xGex)ゲート電極を有するMOSトランジスタを含むCMOS集積回路を備えた半導体装置とその製造方法 |
JP2001257344A (ja) * | 2000-03-10 | 2001-09-21 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2001284466A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6444512B1 (en) | 2000-06-12 | 2002-09-03 | Motorola, Inc. | Dual metal gate transistors for CMOS process |
US6339001B1 (en) * | 2000-06-16 | 2002-01-15 | International Business Machines Corporation | Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist |
KR100399356B1 (ko) * | 2001-04-11 | 2003-09-26 | 삼성전자주식회사 | 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법 |
US6518106B2 (en) | 2001-05-26 | 2003-02-11 | Motorola, Inc. | Semiconductor device and a method therefor |
US6504214B1 (en) * | 2002-01-11 | 2003-01-07 | Advanced Micro Devices, Inc. | MOSFET device having high-K dielectric layer |
US6794281B2 (en) | 2002-05-20 | 2004-09-21 | Freescale Semiconductor, Inc. | Dual metal gate transistors for CMOS process |
US6713335B2 (en) * | 2002-08-22 | 2004-03-30 | Chartered Semiconductor Manufacturing Ltd. | Method of self-aligning a damascene gate structure to isolation regions |
JP4197607B2 (ja) * | 2002-11-06 | 2008-12-17 | 株式会社東芝 | 絶縁ゲート型電界効果トランジスタを含む半導体装置の製造方法 |
US6656824B1 (en) * | 2002-11-08 | 2003-12-02 | International Business Machines Corporation | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch |
US6858483B2 (en) * | 2002-12-20 | 2005-02-22 | Intel Corporation | Integrating n-type and p-type metal gate transistors |
US6828181B2 (en) * | 2003-05-08 | 2004-12-07 | International Business Machines Corporation | Dual gate material process for CMOS technologies |
US7030430B2 (en) | 2003-08-15 | 2006-04-18 | Intel Corporation | Transition metal alloys for use as a gate electrode and devices incorporating these alloys |
TWI258811B (en) * | 2003-11-12 | 2006-07-21 | Samsung Electronics Co Ltd | Semiconductor devices having different gate dielectrics and methods for manufacturing the same |
US7064050B2 (en) * | 2003-11-28 | 2006-06-20 | International Business Machines Corporation | Metal carbide gate structure and method of fabrication |
US7160767B2 (en) | 2003-12-18 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US7220635B2 (en) | 2003-12-19 | 2007-05-22 | Intel Corporation | Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer |
US7217611B2 (en) * | 2003-12-29 | 2007-05-15 | Intel Corporation | Methods for integrating replacement metal gate structures |
US7183184B2 (en) | 2003-12-29 | 2007-02-27 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US7153734B2 (en) | 2003-12-29 | 2006-12-26 | Intel Corporation | CMOS device with metal and silicide gate electrodes and a method for making it |
US7005333B2 (en) * | 2003-12-30 | 2006-02-28 | Infineon Technologies Ag | Transistor with silicon and carbon layer in the channel region |
US7208361B2 (en) | 2004-03-24 | 2007-04-24 | Intel Corporation | Replacement gate process for making a semiconductor device that includes a metal gate electrode |
US7153784B2 (en) | 2004-04-20 | 2006-12-26 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US7045428B2 (en) | 2004-05-26 | 2006-05-16 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction |
US6887800B1 (en) | 2004-06-04 | 2005-05-03 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction |
US7060568B2 (en) * | 2004-06-30 | 2006-06-13 | Intel Corporation | Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit |
US7157378B2 (en) | 2004-07-06 | 2007-01-02 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US7148548B2 (en) | 2004-07-20 | 2006-12-12 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
JP2006041339A (ja) * | 2004-07-29 | 2006-02-09 | Fujitsu Ltd | Cmos集積回路 |
US7074680B2 (en) | 2004-09-07 | 2006-07-11 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US7176090B2 (en) | 2004-09-07 | 2007-02-13 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
US7390709B2 (en) | 2004-09-08 | 2008-06-24 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US7384880B2 (en) | 2004-10-12 | 2008-06-10 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
DE102004052581B4 (de) | 2004-10-29 | 2008-11-20 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer CMOS-Gatestruktur mit einem vordotierten Halbleitergatematerial |
US7381608B2 (en) | 2004-12-07 | 2008-06-03 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode |
US7064066B1 (en) | 2004-12-07 | 2006-06-20 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode |
US7160779B2 (en) | 2005-02-23 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US7598545B2 (en) * | 2005-04-21 | 2009-10-06 | International Business Machines Corporation | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices |
US20060252191A1 (en) * | 2005-05-03 | 2006-11-09 | Advanced Micro Devices, Inc. | Methodology for deposition of doped SEG for raised source/drain regions |
JP2006344836A (ja) * | 2005-06-09 | 2006-12-21 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US7449756B2 (en) | 2005-06-13 | 2008-11-11 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
US7501336B2 (en) | 2005-06-21 | 2009-03-10 | Intel Corporation | Metal gate device with reduced oxidation of a high-k gate dielectric |
US7226831B1 (en) | 2005-12-27 | 2007-06-05 | Intel Corporation | Device with scavenging spacer layer |
US7691693B2 (en) * | 2007-06-01 | 2010-04-06 | Synopsys, Inc. | Method for suppressing layout sensitivity of threshold voltage in a transistor array |
JP5253797B2 (ja) * | 2007-12-07 | 2013-07-31 | 株式会社東芝 | 半導体装置 |
JP5147471B2 (ja) * | 2008-03-13 | 2013-02-20 | パナソニック株式会社 | 半導体装置 |
DE102011004320B4 (de) | 2011-02-17 | 2016-02-04 | Globalfoundries Dresden Module One Llc & Co. Kg | Verfahren zur Herstellung komplementärer Transistoren mit Metallgateelektrodenstrukturen mit großem ε und epitaktisch hergestellten Halbleitermaterialien in den Drain- und Sourcebereichen |
JP5390654B2 (ja) * | 2012-03-08 | 2014-01-15 | 株式会社東芝 | 半導体装置の製造方法 |
US9224655B2 (en) | 2013-03-11 | 2015-12-29 | Globalfoundries Inc. | Methods of removing gate cap layers in CMOS applications |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6045053A (ja) | 1983-08-22 | 1985-03-11 | Mitsubishi Electric Corp | 半導体装置 |
US4948745A (en) | 1989-05-22 | 1990-08-14 | Motorola, Inc. | Process for elevated source/drain field effect structure |
US5021354A (en) | 1989-12-04 | 1991-06-04 | Motorola, Inc. | Process for manufacturing a semiconductor device |
US5168072A (en) * | 1990-10-12 | 1992-12-01 | Texas Instruments Incorporated | Method of fabricating an high-performance insulated-gate field-effect transistor |
KR100274555B1 (ko) * | 1991-06-26 | 2000-12-15 | 윌리엄 비. 켐플러 | 절연 게이트 전계 효과 트랜지스터 구조물 및 이의 제조 방법 |
US5384729A (en) | 1991-10-28 | 1995-01-24 | Rohm Co., Ltd. | Semiconductor storage device having ferroelectric film |
JPH08153804A (ja) | 1994-09-28 | 1996-06-11 | Sony Corp | ゲート電極の形成方法 |
US5656519A (en) | 1995-02-14 | 1997-08-12 | Nec Corporation | Method for manufacturing salicide semiconductor device |
US5956591A (en) * | 1997-02-25 | 1999-09-21 | Advanced Micro Devices, Inc. | Method of making NMOS and PMOS devices having LDD structures using separate drive-in steps |
US5976924A (en) * | 1997-12-30 | 1999-11-02 | Advanced Micro Devices, Inc. | Method of making a self-aligned disposable gate electrode for advanced CMOS design |
US6118163A (en) * | 1998-02-04 | 2000-09-12 | Advanced Micro Devices, Inc. | Transistor with integrated poly/metal gate electrode |
-
1998
- 1998-08-19 US US09/136,333 patent/US6261887B1/en not_active Expired - Lifetime
- 1998-08-27 JP JP10242059A patent/JPH11126829A/ja active Pending
- 1998-08-27 DE DE69836401T patent/DE69836401T2/de not_active Expired - Lifetime
- 1998-08-27 EP EP98116186A patent/EP0899784B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69836401T2 (de) | 2007-05-24 |
EP0899784A2 (de) | 1999-03-03 |
US6261887B1 (en) | 2001-07-17 |
JPH11126829A (ja) | 1999-05-11 |
EP0899784B1 (de) | 2006-11-15 |
EP0899784A3 (de) | 1999-05-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |