DE69900797T2 - Cache-Speicherkohärenzprotokoll mit unabhängiger Implementierung von optimierten Cache-Speicheroperationen - Google Patents

Cache-Speicherkohärenzprotokoll mit unabhängiger Implementierung von optimierten Cache-Speicheroperationen

Info

Publication number
DE69900797T2
DE69900797T2 DE69900797T DE69900797T DE69900797T2 DE 69900797 T2 DE69900797 T2 DE 69900797T2 DE 69900797 T DE69900797 T DE 69900797T DE 69900797 T DE69900797 T DE 69900797T DE 69900797 T2 DE69900797 T2 DE 69900797T2
Authority
DE
Germany
Prior art keywords
cache
optimized
coherency protocol
operations
independent implementation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69900797T
Other languages
English (en)
Other versions
DE69900797D1 (de
Inventor
Ravi Kumar Arimilli
John Steven Dodson
Jerry Don Lewis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69900797D1 publication Critical patent/DE69900797D1/de
Application granted granted Critical
Publication of DE69900797T2 publication Critical patent/DE69900797T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
DE69900797T 1998-02-17 1999-02-15 Cache-Speicherkohärenzprotokoll mit unabhängiger Implementierung von optimierten Cache-Speicheroperationen Expired - Fee Related DE69900797T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/024,306 US6141733A (en) 1998-02-17 1998-02-17 Cache coherency protocol with independent implementation of optimized cache operations

Publications (2)

Publication Number Publication Date
DE69900797D1 DE69900797D1 (de) 2002-03-14
DE69900797T2 true DE69900797T2 (de) 2002-09-19

Family

ID=21819913

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69900797T Expired - Fee Related DE69900797T2 (de) 1998-02-17 1999-02-15 Cache-Speicherkohärenzprotokoll mit unabhängiger Implementierung von optimierten Cache-Speicheroperationen

Country Status (7)

Country Link
US (1) US6141733A (de)
EP (1) EP0936555B1 (de)
JP (1) JPH11272557A (de)
KR (1) KR100330935B1 (de)
CN (1) CN1143227C (de)
DE (1) DE69900797T2 (de)
TW (1) TW400478B (de)

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US6826619B1 (en) 2000-08-21 2004-11-30 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
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US6487643B1 (en) 2000-09-29 2002-11-26 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6772298B2 (en) 2000-12-20 2004-08-03 Intel Corporation Method and apparatus for invalidating a cache line without data return in a multi-node architecture
US7234029B2 (en) * 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US7500036B2 (en) * 2000-12-28 2009-03-03 International Business Machines Corporation Quad aware locking primitive
US6791412B2 (en) 2000-12-28 2004-09-14 Intel Corporation Differential amplifier output stage
US6721918B2 (en) 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US7206879B2 (en) * 2001-11-20 2007-04-17 Broadcom Corporation Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
US6748479B2 (en) 2001-11-20 2004-06-08 Broadcom Corporation System having interfaces and switch that separates coherent and packet traffic
US7394823B2 (en) 2001-11-20 2008-07-01 Broadcom Corporation System having configurable interfaces for flexible system configurations
US6807586B2 (en) * 2002-01-09 2004-10-19 International Business Machines Corporation Increased computer peripheral throughput by using data available withholding
KR100469360B1 (ko) * 2002-02-22 2005-02-02 엘지.필립스 엘시디 주식회사 액정표시소자의 제조 장비용 진공 합착 장치 및 구동 방법
US6965973B2 (en) 2002-05-15 2005-11-15 Broadcom Corporation Remote line directory which covers subset of shareable CC-NUMA memory space
US6993631B2 (en) 2002-05-15 2006-01-31 Broadcom Corporation L2 cache maintaining local ownership of remote coherency blocks
US7003631B2 (en) 2002-05-15 2006-02-21 Broadcom Corporation System having address-based intranode coherency and data-based internode coherency
US7266587B2 (en) 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US7469321B2 (en) * 2003-06-25 2008-12-23 International Business Machines Corporation Software process migration between coherency regions without cache purges
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US7584331B2 (en) * 2005-06-06 2009-09-01 International Business Machines Corporation Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout
US20070094450A1 (en) * 2005-10-26 2007-04-26 International Business Machines Corporation Multi-level cache architecture having a selective victim cache
JP4335298B2 (ja) 2006-02-24 2009-09-30 富士通株式会社 スヌープ制御方法および情報処理装置
US7451277B2 (en) * 2006-03-23 2008-11-11 International Business Machines Corporation Data processing system, cache system and method for updating an invalid coherency state in response to snooping an operation
US9311085B2 (en) * 2007-12-30 2016-04-12 Intel Corporation Compiler assisted low power and high performance load handling based on load types
DE112013003723B4 (de) * 2012-10-22 2018-09-13 Intel Corporation Hochleistungsfähige physikalische Kopplungsstrukturschicht
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Also Published As

Publication number Publication date
CN1143227C (zh) 2004-03-24
US6141733A (en) 2000-10-31
KR100330935B1 (ko) 2002-04-01
JPH11272557A (ja) 1999-10-08
KR19990072598A (ko) 1999-09-27
EP0936555B1 (de) 2002-01-23
CN1226705A (zh) 1999-08-25
EP0936555A3 (de) 1999-09-22
TW400478B (en) 2000-08-01
DE69900797D1 (de) 2002-03-14
EP0936555A2 (de) 1999-08-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee