DE69907250D1 - Verfahren und anordnung zur verlängerung der verfügbaren auffrischungszeit eines 1-t sram-kompatibelspeichers - Google Patents

Verfahren und anordnung zur verlängerung der verfügbaren auffrischungszeit eines 1-t sram-kompatibelspeichers

Info

Publication number
DE69907250D1
DE69907250D1 DE69907250T DE69907250T DE69907250D1 DE 69907250 D1 DE69907250 D1 DE 69907250D1 DE 69907250 T DE69907250 T DE 69907250T DE 69907250 T DE69907250 T DE 69907250T DE 69907250 D1 DE69907250 D1 DE 69907250D1
Authority
DE
Germany
Prior art keywords
arrangement
extending
compatible memory
refreshing time
sram compatible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69907250T
Other languages
English (en)
Other versions
DE69907250T2 (de
Inventor
Wingyu Leung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peraso Inc
Original Assignee
Monolithic System Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Monolithic System Technology Inc filed Critical Monolithic System Technology Inc
Publication of DE69907250D1 publication Critical patent/DE69907250D1/de
Application granted granted Critical
Publication of DE69907250T2 publication Critical patent/DE69907250T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
DE69907250T 1998-10-27 1999-10-18 Verfahren und anordnung zur verlängerung der verfügbaren auffrischungszeit eines 1-t sram-kompatibelspeichers Expired - Lifetime DE69907250T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/181,840 US6075740A (en) 1998-10-27 1998-10-27 Method and apparatus for increasing the time available for refresh for 1-t SRAM compatible devices
PCT/US1999/024310 WO2000025317A1 (en) 1998-10-27 1999-10-18 Method and apparatus for increasing the time available for refresh for 1-t sram compatible devices

Publications (2)

Publication Number Publication Date
DE69907250D1 true DE69907250D1 (de) 2003-05-28
DE69907250T2 DE69907250T2 (de) 2003-10-30

Family

ID=22666033

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69907250T Expired - Lifetime DE69907250T2 (de) 1998-10-27 1999-10-18 Verfahren und anordnung zur verlängerung der verfügbaren auffrischungszeit eines 1-t sram-kompatibelspeichers

Country Status (5)

Country Link
US (2) US6075740A (de)
EP (1) EP1125300B1 (de)
JP (1) JP2002528844A (de)
DE (1) DE69907250T2 (de)
WO (1) WO2000025317A1 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9007790D0 (en) 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
US6286062B1 (en) 1997-07-01 2001-09-04 Micron Technology, Inc. Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus
US6707743B2 (en) * 1998-10-01 2004-03-16 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
US6898140B2 (en) 1998-10-01 2005-05-24 Monolithic System Technology, Inc. Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
US6504780B2 (en) * 1998-10-01 2003-01-07 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a dram device using clock division
US6496437B2 (en) 1999-01-20 2002-12-17 Monolithic Systems Technology, Inc. Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory
US6425062B1 (en) * 1999-09-14 2002-07-23 Intel Corporation Controlling burst sequence in synchronous memories
JP2001118383A (ja) 1999-10-20 2001-04-27 Fujitsu Ltd リフレッシュを自動で行うダイナミックメモリ回路
US6275437B1 (en) * 2000-06-30 2001-08-14 Samsung Electronics Co., Ltd. Refresh-type memory with zero write recovery time and no maximum cycle time
JP4000242B2 (ja) * 2000-08-31 2007-10-31 富士通株式会社 半導体記憶装置
JP3938842B2 (ja) * 2000-12-04 2007-06-27 富士通株式会社 半導体記憶装置
GB0031733D0 (en) 2000-12-28 2001-02-07 Power X Ltd Method and device for operating a ram memory
US6556498B2 (en) * 2001-01-19 2003-04-29 Pien Chien Operation method of a SRAM device
CA2340804A1 (en) 2001-03-14 2002-09-14 Atmos Corporation Sram emulator
JP3985889B2 (ja) 2001-08-08 2007-10-03 株式会社ルネサステクノロジ 半導体装置
JP2003196977A (ja) * 2001-12-27 2003-07-11 Fujitsu Ltd 半導体記憶装置のデータアクセス方法、及び半導体記憶装置
US6880044B2 (en) * 2001-12-31 2005-04-12 Intel Corporation Distributed memory module cache tag look-up
US7389387B2 (en) * 2001-12-31 2008-06-17 Intel Corporation Distributed memory module cache writeback
JP4078119B2 (ja) 2002-04-15 2008-04-23 富士通株式会社 半導体メモリ
US6682982B1 (en) 2002-10-03 2004-01-27 Taiwan Semiconductor Manufacturing Company Process method for 1T-SRAM
US6795364B1 (en) * 2003-02-28 2004-09-21 Monolithic System Technology, Inc. Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode
JP4241175B2 (ja) 2003-05-09 2009-03-18 株式会社日立製作所 半導体装置
US20050010726A1 (en) * 2003-07-10 2005-01-13 Rai Barinder Singh Low overhead read buffer
US6949785B2 (en) * 2004-01-14 2005-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes
US6902975B2 (en) * 2003-10-15 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory technology compatible with 1T-RAM process
US6833578B1 (en) 2003-12-11 2004-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure improving isolation between memory cell passing gate and capacitor
US7019348B2 (en) * 2004-02-26 2006-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded semiconductor product with dual depth isolation regions
US7195970B2 (en) * 2004-03-26 2007-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insulator-metal capacitors
US7068024B1 (en) 2004-12-30 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Voltage regulator having positive temperature coefficient for self-compensation and related method of regulating voltage
US7342835B2 (en) * 2005-04-14 2008-03-11 Winbond Electronics Corp. Memory device with pre-fetch circuit and pre-fetch method
US7274618B2 (en) * 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
KR100670665B1 (ko) 2005-06-30 2007-01-17 주식회사 하이닉스반도체 반도체 메모리 장치의 레이턴시 제어 회로
US20070168536A1 (en) * 2006-01-17 2007-07-19 International Business Machines Corporation Network protocol stack isolation
US7382658B2 (en) * 2006-01-26 2008-06-03 Mosys, Inc. Non-volatile memory embedded in a conventional logic process and methods for operating same
US20070170489A1 (en) * 2006-01-26 2007-07-26 Fang Gang-Feng Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
JP4674865B2 (ja) * 2006-10-30 2011-04-20 株式会社日立製作所 半導体集積回路
US7518934B2 (en) * 2007-03-23 2009-04-14 Intel Corporation Phase change memory with program/verify function
US20090157946A1 (en) * 2007-12-12 2009-06-18 Siamak Arya Memory having improved read capability
US8332876B2 (en) * 2008-11-20 2012-12-11 Ati Technologies Ulc Method, system and apparatus for tri-stating unused data bytes during DDR DRAM writes
TWI425508B (zh) * 2009-04-23 2014-02-01 Orise Technology Co Ltd 具隱藏更新及雙埠能力之ｓｒａｍ相容嵌入式ｄｒａｍ裝置
KR20140030962A (ko) * 2012-09-04 2014-03-12 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
US9384136B2 (en) * 2013-04-12 2016-07-05 International Business Machines Corporation Modification of prefetch depth based on high latency event
GB2522057B (en) 2014-01-13 2021-02-24 Advanced Risc Mach Ltd A data processing system and method for handling multiple transactions
US11139270B2 (en) 2019-03-18 2021-10-05 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
US11043472B1 (en) 2019-05-31 2021-06-22 Kepler Compute Inc. 3D integrated ultra high-bandwidth memory
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330852A (en) * 1979-11-23 1982-05-18 Texas Instruments Incorporated Semiconductor read/write memory array having serial access
JPH0612616B2 (ja) * 1986-08-13 1994-02-16 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
DE69324508T2 (de) * 1992-01-22 1999-12-23 Enhanced Memory Systems Inc DRAM mit integrierten Registern
US5450364A (en) * 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices
JPH08129882A (ja) * 1994-10-31 1996-05-21 Mitsubishi Electric Corp 半導体記憶装置
TW358907B (en) * 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
JP3352577B2 (ja) * 1995-12-21 2002-12-03 インターナショナル・ビジネス・マシーンズ・コーポレーション 記憶装置
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US5784705A (en) * 1996-07-15 1998-07-21 Mosys, Incorporated Method and structure for performing pipeline burst accesses in a semiconductor memory

Also Published As

Publication number Publication date
US6256248B1 (en) 2001-07-03
US6075740A (en) 2000-06-13
DE69907250T2 (de) 2003-10-30
EP1125300B1 (de) 2003-04-23
JP2002528844A (ja) 2002-09-03
EP1125300A1 (de) 2001-08-22
WO2000025317A1 (en) 2000-05-04

Similar Documents

Publication Publication Date Title
DE69907250T2 (de) Verfahren und anordnung zur verlängerung der verfügbaren auffrischungszeit eines 1-t sram-kompatibelspeichers
DE69932875D1 (de) Verfahren und Anordnung zur Benutzung eines 1-T SRAM-Kompatibelspeichers
DE69936018D1 (de) Verpackung für lange Gegenstände und Verfahren zum Verpacken
DE60033873D1 (de) Ein DRAM fähig zur selektiven Ausführung eines Selbstauffrischvorgangs
DE50009293D1 (de) Verfahren und anordnung zur fern-zugangssteuerung
DE69802980D1 (de) Verfahren und Anordnung zur räumliche Lokalisierung eines Objekts
DE69535231D1 (de) VERFAHREN ZUR INTEGRATION EINES Bildtextursignalspeicher UND INTERPOLATIONSLOGIK
DE19851813B4 (de) System und Verfahren zum Bewerten der Abnutzung eines Flash-Speichers
DE69732085D1 (de) Anordnung und Verfahren zur Phasenmessung
DE60036449D1 (de) Verfahren zur hestellung eines dünnschichtfeldeffekttransistors
DE59910851D1 (de) Verfahren und einrichtung zur ermittlung der masse eines fahrzeuges
DE69913304D1 (de) Verfahren zum Verwenden eines Aerosolbehälters
DE69923067D1 (de) Stentplazierinstrument und verfahren zum beladen
DE19983582T1 (de) Entastungsvorrichtung und ein Verfahren für eine Entastungsvorrichtung
DE69924681D1 (de) Probenhalterungselement und Verfahren zu dessen Herstellung
DE69825110D1 (de) Verfahren und Anordnung zur Generierung mindestens eines Alarmsignals für den Füllstand eines Lagertanks
DE69618857D1 (de) Verfahren zur Prüfung eines Direktzugriffspeichers
DE59906517D1 (de) Verfahren und anordnung zur messung von strukturen eines objekts
DE59913231D1 (de) Verfahren und anordnung zur fehlerverdeckung
DE69936530D1 (de) Anordnung und verfahren zur interferenzunterdrückung
DE50114974D1 (de) Verfahren und anordnung zur füllstandsmessung
DE69820246D1 (de) Schaltung und Verfahren zum Lesen eines nichtflüchtigen Speichers
DE19983089T1 (de) Verfahren und Anordnung bei Doppelspulung
DE69512456D1 (de) Verfahren und Schaltungen zur Löschung eines Speichers
DE69942246D1 (de) Verfahren zum Auffrischen eines dynamischen Speichers

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
R082 Change of representative

Ref document number: 1125300

Country of ref document: EP

Representative=s name: WILHELMS, KILIAN & PARTNER, 81541 MUENCHEN, DE