DE69907955D1 - Globale und locale registersegmentierung in einem vliw prozessor - Google Patents
Globale und locale registersegmentierung in einem vliw prozessorInfo
- Publication number
- DE69907955D1 DE69907955D1 DE69907955T DE69907955T DE69907955D1 DE 69907955 D1 DE69907955 D1 DE 69907955D1 DE 69907955 T DE69907955 T DE 69907955T DE 69907955 T DE69907955 T DE 69907955T DE 69907955 D1 DE69907955 D1 DE 69907955D1
- Authority
- DE
- Germany
- Prior art keywords
- global
- local register
- vliw processor
- segmentation
- register segmentation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000011218 segmentation Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US204585 | 1988-06-09 | ||
US09/204,585 US7114056B2 (en) | 1998-12-03 | 1998-12-03 | Local and global register partitioning in a VLIW processor |
PCT/US1999/028820 WO2000033178A1 (en) | 1998-12-03 | 1999-12-03 | Local and global register partitioning in a vliw processor |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69907955D1 true DE69907955D1 (de) | 2003-06-18 |
DE69907955T2 DE69907955T2 (de) | 2004-05-19 |
Family
ID=22758540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69907955T Expired - Fee Related DE69907955T2 (de) | 1998-12-03 | 1999-12-03 | Globale und locale registersegmentierung in einem vliw prozessor |
Country Status (4)
Country | Link |
---|---|
US (2) | US7114056B2 (de) |
EP (1) | EP1137982B1 (de) |
DE (1) | DE69907955T2 (de) |
WO (1) | WO2000033178A1 (de) |
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-
1998
- 1998-12-03 US US09/204,585 patent/US7114056B2/en not_active Expired - Lifetime
-
1999
- 1999-12-03 EP EP99965130A patent/EP1137982B1/de not_active Expired - Lifetime
- 1999-12-03 WO PCT/US1999/028820 patent/WO2000033178A1/en active IP Right Grant
- 1999-12-03 DE DE69907955T patent/DE69907955T2/de not_active Expired - Fee Related
-
2006
- 2006-09-19 US US11/533,314 patent/US7437534B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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WO2000033178A1 (en) | 2000-06-08 |
EP1137982B1 (de) | 2003-05-14 |
US20070016758A1 (en) | 2007-01-18 |
US20010042190A1 (en) | 2001-11-15 |
EP1137982A1 (de) | 2001-10-04 |
DE69907955T2 (de) | 2004-05-19 |
US7437534B2 (en) | 2008-10-14 |
US7114056B2 (en) | 2006-09-26 |
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