EP0036494A2 - Integrated MOS semiconductor circuit - Google Patents

Integrated MOS semiconductor circuit Download PDF

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Publication number
EP0036494A2
EP0036494A2 EP81101324A EP81101324A EP0036494A2 EP 0036494 A2 EP0036494 A2 EP 0036494A2 EP 81101324 A EP81101324 A EP 81101324A EP 81101324 A EP81101324 A EP 81101324A EP 0036494 A2 EP0036494 A2 EP 0036494A2
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EP
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Prior art keywords
substrate bias
clock generator
voltage
circuit
generator
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Granted
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EP81101324A
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German (de)
French (fr)
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EP0036494B1 (en
EP0036494A3 (en
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Kurt Dr. Hoffmann
Dieter Dipl.-Ing. Kantz
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • the invention relates to a monolithically integrated digital semiconductor circuit with capacitively controlled field-effect transistors and with a clock generator which supplies the clock pulses required for controlling the operation of the actual digital semiconductor circuit, in which supply connections to which the actual digital semiconductor circuit together with the clock generator acted upon by a potential supplied by a DC voltage source receiving semiconductor plates are provided and with at least one conductive connection to the actual digital semiconductor circuit and to the clock generator.
  • digital semiconductor circuits often require not only two operating potentials but also a further operating potential which is used to produce a substrate bias lying between the rear side of the semiconductor die and the circuit parts on the front side thereof. If a clock is then provided in the circuit, it should be in the interest of avoiding destruction the integrated semiconductor circuit of the clock generator can only be switched on after the substrate bias voltage V BB has been built up. Furthermore, many digital circuits, for example dynamic memories, are interested in an auxiliary voltage V z which exceeds the voltage difference between the two connections of the semiconductor body being available, in particular if the circuit is provided with varactor capacitors to be charged. It is an object of the invention to provide a suitable circuit option.
  • an oscillator for controlling a substrate bias generator and this for controlling the clock generator is provided in such a way that the clock generator only comes into operation after the substrate bias voltage V BB has been completed .
  • This is done in particular by means of a converter which acts as a comparator and which activates the clock generator when the final value of the substrate bias is reached.
  • said oscillator is provided for controlling a voltage multiplication circuit which supplies an additional further operating potential V Z , for example a voltage doubling circuit.
  • This further operating potential is preferably used to apply MOS capacitors, that is to say the said varactor capacitors, which are used, for example, as storage capacitors.
  • MOS capacitors that is to say the said varactor capacitors, which are used, for example, as storage capacitors.
  • it can also form the second operating potential required to operate the actual integrated digital circuit ES instead of V cc .
  • the two supply connections of the semiconductor chip receiving the circuit are supplied with the operating potentials V CC and G ND , which are then supplied to the individual circuit parts in the manner shown in the drawing.
  • the presentation of the cable routes has not been carried out.
  • the following circuit parts are also provided:
  • the voltage multiplier is SV, the substrate bias generator SE.
  • a clocked substrate bias generator SE in which an oscillator 0 is provided as a clock generator, is described in DE-OS 28 12 378 (title: “Semiconductor circuit with at least two field-effect transistors combined in a semiconductor crystal” (VPA 78 P 1043)).
  • the circuit of a substrate bias generator shown in Fig. 1 of this OS can be applied directly.
  • the clock generator TG which is responsible for the actual integrated digital semiconductor circuit ES is in turn supplied with rectangular pulses from an external pulse source via an input TE. It has the task of operating the actual Lichen digital semiconductor circuit to derive necessary clock signals from the primary pulses obtained via the input TE.
  • the supply potentials V CC and G ND are provided both for the clock generator TG and for the substrate bias generator SE, which incidentally also applies to the converter provided between the two.
  • This converter or converter U is also supplied by the two operating potentials V 00 and G ND . It has the task of emitting an activation signal to the clock generator TG as soon as the substrate bias voltage supplied by the substrate bias generator SE is fully built up. It is therefore the purpose of the voltage supplied by the converter V to only start the clock generator TG when the substrate bias voltage V BB has reached its desired value.
  • the converter U thus acts as a comparator and can be given, for example, by a differential amplifier. The presence of the converter U prevents the actual digital semiconductor circuit ES, for example a semiconductor memory, from being put into operation before the substrate bias is built up and the short-circuit current which then occurs being damaged.
  • the circuit principle described there can also be used for DC voltage multipliers with a different integer ratio between input and output voltage.
  • the oscillator provided there can easily be replaced by the clock oscillator 0 provided to supply the substrate bias generator SE.
  • the task of the voltage multiplier SV is to generate an increased operational DC voltage required for operating the actual digital semiconductor circuit ES, as is required, for example, for charging storage capacities.
  • the output of the voltage multiplier SV is connected to the ground potential G ND via a limiter circuit BS. It is also connected directly to a further supply input of the actual digital semiconductor circuit ES and leads the increased additional operating potential U z required for operating selected circuit parts, for example for charging storage capacitors.
  • the substrate bias V BB which is provided by the substrate bias generator SE, on the other hand, benefits all the circuit parts provided in the semiconductor die.
  • the actual operating potential V CC is made available to the circuit parts 0, SE, U, TG and SV. It also serves as the main operating potential for the actual integrated circuit ES. The same applies to the reference potential G ND .
  • the limiter circuit BS can consist, for example, of two or more MOS field-effect transistors t connected in series, which are connected as resistors by connecting their gates to their drains.
  • the source of the last of these transistors t is at the reference potential G ND .
  • the number of transistors t lying in series depends on the number of field effect transistors connected in series in the voltage multiplication circuit SV with respect to the two operating potentials V CC and G ND .
  • the transistors t can also be connected as diodes in the reverse direction.

Abstract

Bei monolithisch integrierten digitalen Halbleiterschaltungen auf MOS-Basis mit einem Taktgeber und zwei durch je ein extern zugeführtes Betriebspotential beaufschlagten Versorgungsanschlüssen ist es wünschenswert, wenn der Taktgeber erst nach dem Aufbau der Substratvorspannung aktiviert wird. Die Erfindung befaßt sich mit der Aufgabe, eine hierzu geeignete Schaltung anzugeben. Die Erfindung betrifft eine integrierte MOS-Schaltung der genannten Art, bei der durch je ein von einer Gleichspannungsquelle geliefertes Betriebspotential beaufschlagte Versorgungsanschlüsse mit wenigstens je einer leitenden Verbindung an die eigentliche digitale Halbleiterschaltung (ES) und an den Taktgeber (TG) gelegt sind, wobei erfindungsgemäß ein Oszillator (O) zur Steuerung eines. Substratvorspannungsgenerators (SE) vorgesehen ist. Dieser Substratvorspannungsgenerator hat neben dem Aufbau der Substratvorspannung die Aufgabe, den Betrieb des Taktgebers (TG) so zu steuern, daß die Aktivierung des Taktgebers (TG) erst nach Vollendung des Aufbaus der Substratvorspannung (VBB) erfolgt.In the case of monolithically integrated digital semiconductor circuits based on MOS, with a clock generator and two supply connections, each of which is supplied with an externally supplied operating potential, it is desirable if the clock generator is only activated after the substrate bias has been built up. The invention is concerned with the task of specifying a circuit suitable for this purpose. The invention relates to an integrated MOS circuit of the type mentioned, in which supply connections with at least one conductive connection, each supplied with an operating potential supplied by a DC voltage source, are connected to the actual digital semiconductor circuit (ES) and to the clock generator (TG), according to the invention an oscillator (O) for controlling a. Substrate bias generator (SE) is provided. In addition to the construction of the substrate bias, this substrate bias generator has the task of controlling the operation of the clock generator (TG) in such a way that the activation of the clock generator (TG) takes place only after the construction of the substrate bias voltage (VBB) has been completed.

Description

Die Erfindung betrifft eine monolithisch integrierte digitale Halbleiterschaltung mit kapazitiv gesteuerten Feldeffekttransistoren sowie mit einem die zur Steuerung des Betriebs der eigentlichen digitalen Halbleiterschaltung erforderlichen Taktimpulse liefernden Taktgeber, bei der durch je ein von einer Gleichspannungsquelle geliefertes Potential beaufschlagte Versorgungsanschlüsse an dem die eigentliche digitale Halbleiterschaltung samt dem Taktgeber aufnehmenden Halbleiterplättchen vorgesehen und mit wenigstens je einer leitenden Verbindung an die eigentliche digitale Halbleiterschaltung und an den Taktgeber gelegt sind.The invention relates to a monolithically integrated digital semiconductor circuit with capacitively controlled field-effect transistors and with a clock generator which supplies the clock pulses required for controlling the operation of the actual digital semiconductor circuit, in which supply connections to which the actual digital semiconductor circuit together with the clock generator acted upon by a potential supplied by a DC voltage source receiving semiconductor plates are provided and with at least one conductive connection to the actual digital semiconductor circuit and to the clock generator.

Nun sind bei digitalen Halbleiterschaltungen häufig nicht nur zwei Betriebspotentiale sondern noch ein weiteres Betriebspotential erforderlich, das zur Erzeugang einer zwischen der Rückseite des Halbleiterplättchens und den Schaltungsteilen an der Vorderseite desselben liegenden Substratvorspannung gebraucht wird. Ist bei der Schaltung dann ein Taktgeber vorgesehen, so soll im Interesse der Vermeidung einer Zerstörung der integrierten Halbleiterschaltung der Taktgeber erst nach dem Aufbau der Substratvorspannung VBB eingeschaltet werden. Ferner ist man bei vielen Digitalschaltungen, z.B. bei dynamischen Speichern, daran interessiert, daß eine die zwischen den beiden Anschlüssen des Halbleiterkörpers liegende Spannungsdifferenz übertreffende Hilfsspannung Vz zur Verfügung steht, insbesondere dann, wenn die Schaltung mit aufzuladenden Varaktorkondensatoren versehen ist. Es ist nun Aufgabe der Erfindung, eine geeignete Schaltungsmöglichkeit anzugeben.Now, digital semiconductor circuits often require not only two operating potentials but also a further operating potential which is used to produce a substrate bias lying between the rear side of the semiconductor die and the circuit parts on the front side thereof. If a clock is then provided in the circuit, it should be in the interest of avoiding destruction the integrated semiconductor circuit of the clock generator can only be switched on after the substrate bias voltage V BB has been built up. Furthermore, many digital circuits, for example dynamic memories, are interested in an auxiliary voltage V z which exceeds the voltage difference between the two connections of the semiconductor body being available, in particular if the circuit is provided with varactor capacitors to be charged. It is an object of the invention to provide a suitable circuit option.

Erfindungsgemäß ist vorgesehen, daß ein Oszillator zur Steuerung eines Substratvorspannungsgenerators und dieser zur Steuerung des Taktgebers derart vorgesehen ist, daß der Taktgeber erst nach Vollendung des Aufbaus der Substratvorspannung VBB in Tätigkeit tritt. Dies geschieht insbesondere unter Vermittlung eines als Komparator wirkenden Umformers, der mit dem Erreichen des Endwertes der Substratvorspannung den Taktgeber aktiviert.According to the invention it is provided that an oscillator for controlling a substrate bias generator and this for controlling the clock generator is provided in such a way that the clock generator only comes into operation after the substrate bias voltage V BB has been completed . This is done in particular by means of a converter which acts as a comparator and which activates the clock generator when the final value of the substrate bias is reached.

Gemäß einer weiteren Ausbildung der Erfindung ist der besagte Oszillator zur Steuerung einer - ein zusätzliches weiteres Betriebspotential VZ liefernden -Spannungsvervielfachungsschaltung , z.B. einer Spannungsverdopplungsschaltung, vorgesehen. Dieses weitere Betriebspotential dient vorzugsweise zur Beaufschlagung von MOS-Kondensatoren, also den besagten Varaktorkondensatoren, die z.B. als Speicherkondensatoren eingesetzt sind. Sie kann aber auch das zum Betrieb der eigentlichen integrierten Digitalaschaltung ES benötigte zweite Betriebspotential anstelle von Vcc bilden.According to a further embodiment of the invention, said oscillator is provided for controlling a voltage multiplication circuit which supplies an additional further operating potential V Z , for example a voltage doubling circuit. This further operating potential is preferably used to apply MOS capacitors, that is to say the said varactor capacitors, which are used, for example, as storage capacitors. However, it can also form the second operating potential required to operate the actual integrated digital circuit ES instead of V cc .

Es kann vorteilhaft sein, wenn die Substratvorspannung VBB und/oder die vom Spannungsvervielfacher SV gelieferte Spannung VZ unter Vermittlung eines Regelkreises stabilisiert wird.It can be advantageous if the substrate bias V BB and / or the voltage V Z supplied by the voltage multiplier SV is stabilized by means of a control loop.

Eine der Erfindung entsprechende integrierte digitale Halbleiterschaltung ist im Blockschaltbild in der Zeichnung dargestellt. Auf diese soll nun eingegangen werden.An integrated digital semiconductor circuit according to the invention is shown in the block diagram in the drawing. This will now be dealt with.

Die beiden Versorgungsanschlüsse des die Schaltung aufnehmenden Halbleiterplättchens sind mit den Betriebspotentialen VCC und GND beaufschlagt, die dann den einzelnen Schaltungsteilen in der aus der Zeichnung ersichtlichen Weise zugeführt werden. Von der Darstellung der Leitungswege ist dabei abgesehen worden. Als Schaltungsteile sind, neben der eigentlichen digitalen Halbleiterschaltung ES, noch vorgesehen:The two supply connections of the semiconductor chip receiving the circuit are supplied with the operating potentials V CC and G ND , which are then supplied to the individual circuit parts in the manner shown in the drawing. The presentation of the cable routes has not been carried out. In addition to the actual digital semiconductor circuit ES, the following circuit parts are also provided:

Ein durch die von den beiden Betriebspotentialen VCC und GND (= Bezugspotential = Masse) gegeben Betriebsspannung beaufschlagter Oszillator 0, der insbesondere als RC-Oszillator ausgebildet ist. Er liefert periodische Rechteckimpulse gleicher Amplitude, die zur Steuerung des Substratvorspannungserzeugers und des Spannungsvervielfachers, z.B. Spannungsverdopplers dienen. Der Spannungsvervielfacher ist mit SV, der Substratvorspannungsgenerator mit SE bezeichnet.An oscillator 0 acted upon by the operating voltage given by the two operating potentials V CC and G ND (= reference potential = ground), which is designed in particular as an RC oscillator. It delivers periodic square-wave pulses of the same amplitude, which are used to control the substrate bias generator and the voltage multiplier, eg voltage doubler. The voltage multiplier is SV, the substrate bias generator SE.

Ein getakteter Substratvorspannungserzeuger SE, bei dem ein Oszillator 0 als Taktgeber vorgesehen ist, ist aus der DE-OS 28 12 378 (Titel:"Halbleiterschaltung mit mindestens zwei in einem Halbleiterkristall vereinigten Feldeffekttransistoren" (VPA 78 P 1043)) beschrieben. Die in Fig. 1 dieser OS dargestellte Schaltung eines Substratvorspannungserzeugers kann unmittelbar angewendet werden.A clocked substrate bias generator SE, in which an oscillator 0 is provided as a clock generator, is described in DE-OS 28 12 378 (title: "Semiconductor circuit with at least two field-effect transistors combined in a semiconductor crystal" (VPA 78 P 1043)). The circuit of a substrate bias generator shown in Fig. 1 of this OS can be applied directly.

Der für die eigentliche integrierte digitale Halbleiterschaltung ES zuständige Taktgeber TG wird seinerseits über einen Eingang TE mit Rechteckimpulsen von einer externen Impulsquelle her beaufschlagt. Er hat die Aufgabe, die zum Betrieb der eigentlichen digitalen Halbleiterschaltung erforderlichen Taktsignale aus den über den Eingang TE erhaltenen Primärimpulsen abzuleiten. Sowohl für den Taktgeber TG als auch für den Substratvorspannungsgenerator SE sind die Versorgungspotentiale VCC und GND vorgesehen, was übrigens auch für den zwischen beiden vorgesehenen Umformer gilt..The clock generator TG which is responsible for the actual integrated digital semiconductor circuit ES is in turn supplied with rectangular pulses from an external pulse source via an input TE. It has the task of operating the actual Lichen digital semiconductor circuit to derive necessary clock signals from the primary pulses obtained via the input TE. The supply potentials V CC and G ND are provided both for the clock generator TG and for the substrate bias generator SE, which incidentally also applies to the converter provided between the two.

Dieser Umformer oder Umwandler U wird ebenfalls durch die beiden Betriebspotentiale V00 und GND versorgt. Er hat die Aufgabe, an den Taktgeber TG ein Aktivierungssignal abzugeben, sobald die vom Substratvorspannungsgenerator SE gelieferte Substratvorspannung voll aufgebaut ist. Somit ist es Zweck der vom Umwandler V gelieferten Spannung, erst dann den Taktgeber TG in Betrieb zu setzen, wenn die Substratvorspannung VBB ihren Sollwert erreicht hat. Der Umwandler U wirkt somit als Komparator und kann z.B. durch einen Differenzverstärker gegeben sein. Durch die Anwesenheit des Umwandlers U wird vermieden, daß die eigentliche digitale Halbleiterschaltung ES, z.B. ein Halbleiterspeicher, vor dem Aufbau der Substratvorspannung in Betrieb gesetzt und den dann auftretenden Kurzschlußstrom beschädigt wird.This converter or converter U is also supplied by the two operating potentials V 00 and G ND . It has the task of emitting an activation signal to the clock generator TG as soon as the substrate bias voltage supplied by the substrate bias generator SE is fully built up. It is therefore the purpose of the voltage supplied by the converter V to only start the clock generator TG when the substrate bias voltage V BB has reached its desired value. The converter U thus acts as a comparator and can be given, for example, by a differential amplifier. The presence of the converter U prevents the actual digital semiconductor circuit ES, for example a semiconductor memory, from being put into operation before the substrate bias is built up and the short-circuit current which then occurs being damaged.

Ein getakteter Spannungsverdoppler SV ist in der DE-OS 28 11 418 (Titel: "Taktgesteuerter Gleichspannungswandler" (= VPA 78 P 1069)) beschrieben. Das dort beschriebene Schaltungsprinzip läßt sich auch Gleichspannungsvervielfacher mit einem anderen ganzzahligen Verhältnis zwischen Eingangs- und Ausgangsspannung verwenden. Der dort vorgesehene Oszillator kann ohne weiteres durch den zur Versorgung des Substratvorspannungsgenerators SE vorgesehenen Taktosillator 0 ersetzt werden. Aufgabe des Spannungsvervielfachers SV ist es, eine zum Betrieb der eigentlichen digitalen Halbleiterschaltung ES benötigte erhöhte Betriebsgleichspannung zu erzeugen, wie sie z.B. zum Aufladen von Speicherkapazitäten benötigt wird.A clocked voltage doubler SV is described in DE-OS 28 11 418 (title: "Clock-controlled DC-DC converter" (= VPA 78 P 1069)). The circuit principle described there can also be used for DC voltage multipliers with a different integer ratio between input and output voltage. The oscillator provided there can easily be replaced by the clock oscillator 0 provided to supply the substrate bias generator SE. The task of the voltage multiplier SV is to generate an increased operational DC voltage required for operating the actual digital semiconductor circuit ES, as is required, for example, for charging storage capacities.

Der Ausgang des Spannungsvervielfachers SV ist über eine Begrenzerschaltung BS an das Massenpotential GND gelegt. Er ist außerdem unmittelbar an einen weiteren Versorgungseingang der eigentlichen digitaöen Halbleiterschaltung ES geschaltet und führt das zum Betrieb auserwählter Schaltungsteile, z.B. zum Aufladen von Speicherkondensatoren, benötigte erhöhte zusätzliche Betriebspotential Uz.The output of the voltage multiplier SV is connected to the ground potential G ND via a limiter circuit BS. It is also connected directly to a further supply input of the actual digital semiconductor circuit ES and leads the increased additional operating potential U z required for operating selected circuit parts, for example for charging storage capacitors.

Die Substratvorspannung VBB, die vom Substratvorspannungsgenerator SE zur Verfügung gestellt wird, kommt hingegen allen im Halbleiterplättchen vorgesehenen Schaltungsteilen zugute. Das eigentliche Betriebspotential VCC ist, wie bereits festgestellt, den Schaltungsteilen 0, SE, U, TG und SV zur Verfügung gestellt. Es dient außerdem als Hauptbetriebspotential für die eigentliche integrierte Schaltung ES. Dasselbe gilt für das Bezugspotential GND.The substrate bias V BB , which is provided by the substrate bias generator SE, on the other hand, benefits all the circuit parts provided in the semiconductor die. As already stated, the actual operating potential V CC is made available to the circuit parts 0, SE, U, TG and SV. It also serves as the main operating potential for the actual integrated circuit ES. The same applies to the reference potential G ND .

Die Begrenzerschaltung BS kann z.B. aus zwei oder mehreren hintereinandergeschalteten MOS-Feldeffekttransistoren t bestehen, die durch Verbindung ihrer Gates mit ihren Drains als Widerstände geschaltet sind. Die Source des letzten dieser Transistoren t liegt am Bezugspotential GND. Die Anzahl der in Reihe liegenden Transistoren t richtet sich nach der Anzahl der in der Spannungsvervielfachungsschaltung SV bezüglich der beiden Betriebspotentiale VCC und GND hintereinandergeschalteten Feldeffekttransistoren. Die Transistoren t können übrigens auch als in Sperrichtung liegende Dioden geschaltet sein.The limiter circuit BS can consist, for example, of two or more MOS field-effect transistors t connected in series, which are connected as resistors by connecting their gates to their drains. The source of the last of these transistors t is at the reference potential G ND . The number of transistors t lying in series depends on the number of field effect transistors connected in series in the voltage multiplication circuit SV with respect to the two operating potentials V CC and G ND . The transistors t can also be connected as diodes in the reverse direction.

Claims (7)

1. Monolithisch integrierte digitale Halbleiterschaltung mit kapazitiv gesteuerten Feldeffekttransistoren sowie mit einem die zur Steuerung des Betriebes der eigentlichen digitalen Halbleiterschaltung erforderlichen Taktimpulse liefernden Taktgeber, bei der durch je ein von einer Gleichspannungsquelle geliefertes Potential (VCC, GND) beaufschlagte Versorgungsanschlüsse an dem die eigentliche digitale Halbleiterschaltung (ES) samt dem Taktgeber (TG) aufnehmenden Halbleiterplättchen vorgesehen und mit wenigstens je einer leitenden Verbindung an die eigentliche digitale Halbleiterschaltung (ES) und an den Taktgeber (TG) gelegt sind, dadurch gekennzeichnet, daß ein Oszillator (0) zur Steuerung eines Substratvorspannungsgenerators (SE) und dieser zur Steuerung des Taktgebers (TG) derart vorgesehen ist, daß der Taktgeber (TG) erst nach Vollendung des Aufbaus der Substratvorspannung (VBB) in Tätigkeit tritt.1.Monolithically integrated digital semiconductor circuit with capacitively controlled field-effect transistors and with a clock generator which supplies the clock pulses required for controlling the operation of the actual digital semiconductor circuit, in which the actual connections are acted upon by a potential supplied by a DC voltage source (V CC , G ND ) digital semiconductor circuit (ES) including the semiconductor chip receiving the clock generator (TG) are provided and are connected to the actual digital semiconductor circuit (ES) and to the clock generator (TG) with at least one conductive connection each, characterized in that an oscillator (0) for control a substrate bias generator (SE) and this is provided for controlling the clock generator (TG) in such a way that the clock generator (TG) only comes into action after completion of the build-up of the substrate bias voltage (V BB ). 2. Monolithisch integrierte Schaltung nach Anspruch 1, dadurch gekennzeichnet, daß zwischen dem die Substratvorspannung (VBB) liefernden Ausgang des Substratvorspannungserzeugers (SE) und einem der Aktivierung des Taktgebers (TG) dienenden Eingang desselben ein als Komparator wirkender Umformer (U) derart vorgesehen ist, daß der Umformer (U) mit Vollendung des Aufbaus der Substratvorspannung (VBB) ein Aktivierungssignal an den Taktgeber (TG) abgibt.2. A monolithically integrated circuit according to claim 1, characterized in that between the substrate bias voltage (V BB ) supplying output of the substrate bias voltage generator (SE) and one of the activation of the clock generator (TG) serving the same serving as a comparator converter (U) is provided is that the converter (U) emits an activation signal to the clock generator (TG) upon completion of the build-up of the substrate bias (V BB ). 3. Monolithisch integrierte Schaltung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Oszillator (0) zur Steuerung einer ein zusätzliches Betriebspotential (VZ) liefernden Spannungsvervielfachungsschaltung (SV) vorgesehen ist.3. Monolithically integrated circuit according to claim 1 or 2, characterized in that the oscillator (0) for controlling an additional operating potential (V Z ) supplying voltage multiplication circuit (SV) is provided. 4. Monolithisch integrierte Schaltung nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß der das erhöhte Betriebspotential (V ) liefernde Ausgang der Spannungsvervielfachungsschaltung (SV) über eine Begrenzerschaltung (BS) an das Bezugspotential GND, das von dem einen Anschluß des die Schaltung aufnehmenden Halbleiterkörpers geliefert wird, gelegt ist.4. Monolithically integrated circuit according to one of claims 1 to 3, characterized in that the output of the voltage multiplication circuit (SV) delivering the increased operating potential (V) via a limiter circuit (BS) to the reference potential G ND , which from the one connection of the Circuit receiving semiconductor body is supplied is laid. 5. Monolithisch integrierte Schaltung nach Anspruch 4, dadurch gekennzeichnet, daß die Begrenzerschaltung (BS) aus in Serie liegenden MOS-Feldeffekttransistoren (t) besteht, die in gleicher Weise als Widerstände geschaltet sind.5. Monolithically integrated circuit according to claim 4, characterized in that the limiter circuit (BS) consists of series-connected MOS field effect transistors (t) which are connected in the same way as resistors. 6. Monolithisch integrierte Schaltung nach Anspruch 4, dadurch gekennzeichnet, daß die Begrenzerschaltung (BS) aus in Serie liegenden MOS-Feldeffekttransistoren (t) besteht, die in gleicher Weise als in Sperrichtung liegende Dioden geschaltet sind.6. A monolithically integrated circuit according to claim 4, characterized in that the limiter circuit (BS) consists of series-connected MOS field effect transistors (t) which are connected in the same way as diodes in the reverse direction. 7. Monolithisch integrierte Schaltung nach einem der Ansprüche 4 bis 6, dadurch gekennzeichnet, daß die vom Spannungsvervielfacher (SV) gelieferte Spannung (Vz) und/oder die vom Substratvorspannungsgenerator (SE) gelieferte Spannung (VBB) stabilisiert ist.7. Monolithically integrated circuit according to one of claims 4 to 6, characterized in that the voltage multiplier (SV) supplied voltage (V z ) and / or the voltage supplied by the substrate bias generator (SE) (V BB ) is stabilized.
EP81101324A 1980-03-11 1981-02-24 Integrated mos semiconductor circuit Expired EP0036494B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3009303 1980-03-11
DE19803009303 DE3009303A1 (en) 1980-03-11 1980-03-11 MONOLITHICALLY INTEGRATED DIGITAL SEMICONDUCTOR CIRCUIT

Publications (3)

Publication Number Publication Date
EP0036494A2 true EP0036494A2 (en) 1981-09-30
EP0036494A3 EP0036494A3 (en) 1981-11-25
EP0036494B1 EP0036494B1 (en) 1984-07-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP81101324A Expired EP0036494B1 (en) 1980-03-11 1981-02-24 Integrated mos semiconductor circuit

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US (1) US4454431A (en)
EP (1) EP0036494B1 (en)
JP (1) JPS56142663A (en)
DE (2) DE3009303A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175152A2 (en) * 1984-08-21 1986-03-26 Lattice Semiconductor Corporation A method and an apparatus to prevent latchup in a CMOS device
EP0217065A1 (en) * 1985-08-26 1987-04-08 Siemens Aktiengesellschaft Integrated circuit of the complementary technique having a substrate bias generator

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618249B2 (en) * 1984-10-17 1994-03-09 富士通株式会社 Semiconductor integrated circuit
US4794278A (en) * 1987-12-30 1988-12-27 Intel Corporation Stable substrate bias generator for MOS circuits
KR950002015B1 (en) * 1991-12-23 1995-03-08 삼성전자주식회사 Static source voltage generating circuit operated by an oscillator
CN105024674B (en) * 2015-03-13 2018-06-12 苏州迈瑞微电子有限公司 A kind of asynchronous reset

Citations (4)

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FR2333296A1 (en) * 1975-11-28 1977-06-24 Honeywell Inf Systems SUBSTRATE POLARIZATION TENSION GENERATED BY REGENERATION OSCILLATOR
US4061929A (en) * 1975-09-22 1977-12-06 Kabushiki Kaisha Daini Seikosha Circuit for obtaining DC voltage higher than power source voltage
JPS53130990A (en) * 1977-04-20 1978-11-15 Toshiba Corp Integrated circuit device
US4142114A (en) * 1977-07-18 1979-02-27 Mostek Corporation Integrated circuit with threshold regulation

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US3794862A (en) * 1972-04-05 1974-02-26 Rockwell International Corp Substrate bias circuit
US3838357A (en) * 1973-10-25 1974-09-24 Honeywell Inf Systems Apparatus for using start-up of a crystal oscillator to synchronize power turn-on in various portions of a system
DE2812378C2 (en) * 1978-03-21 1982-04-29 Siemens AG, 1000 Berlin und 8000 München Substrate bias generator for MIS integrated circuits
JPS5525220A (en) * 1978-08-11 1980-02-22 Oki Electric Ind Co Ltd Substrate bias generation circuit
US4229667A (en) * 1978-08-23 1980-10-21 Rockwell International Corporation Voltage boosting substrate bias generator
JPS5951750B2 (en) * 1978-11-24 1984-12-15 富士通株式会社 Substrate bias generation circuit
US4296340A (en) * 1979-08-27 1981-10-20 Intel Corporation Initializing circuit for MOS integrated circuits

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US4061929A (en) * 1975-09-22 1977-12-06 Kabushiki Kaisha Daini Seikosha Circuit for obtaining DC voltage higher than power source voltage
FR2333296A1 (en) * 1975-11-28 1977-06-24 Honeywell Inf Systems SUBSTRATE POLARIZATION TENSION GENERATED BY REGENERATION OSCILLATOR
JPS53130990A (en) * 1977-04-20 1978-11-15 Toshiba Corp Integrated circuit device
US4142114A (en) * 1977-07-18 1979-02-27 Mostek Corporation Integrated circuit with threshold regulation

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE International Solid-State Circuits Conference, 13. Februar 1980 New York (US) A.C. GRAHAM et al.: "Battery Backup Circuits for Memories", seiten 58 und 59. * ganzes dokument * *
IEEE Journal of Solid-State Circuits, Band SC-15, Nr. 5, Oktober 1980 New York (US) J.Y. CHAN: "A 100ns 5 V only 64 K x 1 MOS Dynamic RAM", seiten 839-846. * seite 842, figur 6; Abschnitt "Cell Plate Generation Circuit" * *
PATENTS ABSTRACTS OF JAPAN, Band 3, Nr. 2, 13. Januar 1979 seite 164E83 & JP-A-53 130 990 (Tokyo Shibaura Denki K.K.) (15.11.1978) * zusammenfassung * *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175152A2 (en) * 1984-08-21 1986-03-26 Lattice Semiconductor Corporation A method and an apparatus to prevent latchup in a CMOS device
EP0175152A3 (en) * 1984-08-21 1986-11-20 Lattice Semiconductor Corporation A method and an apparatus to prevent latchup in a cmos device
EP0217065A1 (en) * 1985-08-26 1987-04-08 Siemens Aktiengesellschaft Integrated circuit of the complementary technique having a substrate bias generator

Also Published As

Publication number Publication date
US4454431A (en) 1984-06-12
DE3009303A1 (en) 1981-09-24
EP0036494B1 (en) 1984-07-25
EP0036494A3 (en) 1981-11-25
JPH0213821B2 (en) 1990-04-05
DE3164950D1 (en) 1984-08-30
JPS56142663A (en) 1981-11-07

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