EP0100943A3 - Hierarchical memory system - Google Patents

Hierarchical memory system Download PDF

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Publication number
EP0100943A3
EP0100943A3 EP83107191A EP83107191A EP0100943A3 EP 0100943 A3 EP0100943 A3 EP 0100943A3 EP 83107191 A EP83107191 A EP 83107191A EP 83107191 A EP83107191 A EP 83107191A EP 0100943 A3 EP0100943 A3 EP 0100943A3
Authority
EP
European Patent Office
Prior art keywords
memory system
hierarchical memory
hierarchical
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP83107191A
Other versions
EP0100943A2 (en
EP0100943B1 (en
Inventor
Russell William Lavallee
Philip Meade Ryan
Vincent Francis Sollitto, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0100943A2 publication Critical patent/EP0100943A2/en
Publication of EP0100943A3 publication Critical patent/EP0100943A3/en
Application granted granted Critical
Publication of EP0100943B1 publication Critical patent/EP0100943B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
EP83107191A 1982-08-06 1983-07-22 Hierarchical memory system Expired - Lifetime EP0100943B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US405812 1982-08-06
US06/405,812 US4489381A (en) 1982-08-06 1982-08-06 Hierarchical memories having two ports at each subordinate memory level

Publications (3)

Publication Number Publication Date
EP0100943A2 EP0100943A2 (en) 1984-02-22
EP0100943A3 true EP0100943A3 (en) 1986-10-01
EP0100943B1 EP0100943B1 (en) 1990-06-13

Family

ID=23605346

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83107191A Expired - Lifetime EP0100943B1 (en) 1982-08-06 1983-07-22 Hierarchical memory system

Country Status (4)

Country Link
US (1) US4489381A (en)
EP (1) EP0100943B1 (en)
JP (1) JPS5930289A (en)
DE (1) DE3381653D1 (en)

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JPH0652530B2 (en) * 1982-10-25 1994-07-06 株式会社日立製作所 Vector processor
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4755928A (en) * 1984-03-05 1988-07-05 Storage Technology Corporation Outboard back-up and recovery system with transfer of randomly accessible data sets between cache and host and cache and tape simultaneously
US4823259A (en) * 1984-06-29 1989-04-18 International Business Machines Corporation High speed buffer store arrangement for quick wide transfer of data
EP0166192B1 (en) * 1984-06-29 1991-10-09 International Business Machines Corporation High-speed buffer store arrangement for fast transfer of data
US4718039A (en) * 1984-06-29 1988-01-05 International Business Machines Intermediate memory array with a parallel port and a buffered serial port
US4633440A (en) * 1984-12-31 1986-12-30 International Business Machines Multi-port memory chip in a hierarchical memory
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
JPS6221357A (en) * 1985-07-22 1987-01-29 Toshiba Corp Memory system
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4881163A (en) * 1986-09-19 1989-11-14 Amdahl Corporation Computer system architecture employing cache data line move-out queue buffer
EP0280954B1 (en) * 1987-02-16 1991-04-24 Siemens Aktiengesellschaft Data exchange control method between processing units and a memory arrangement including a cache in data-processing systems, as well as a cache operating according to this method
EP0310446A3 (en) * 1987-10-02 1990-08-16 COMPUTER CONSOLES INCORPORATED (a Delaware corporation) Cache memory management method
US4905188A (en) * 1988-02-22 1990-02-27 International Business Machines Corporation Functional cache memory chip architecture for improved cache access
JPH0743676B2 (en) * 1988-03-11 1995-05-15 株式会社日立製作所 Back-up data dump control method and device
JPH01280860A (en) * 1988-05-06 1989-11-13 Hitachi Ltd Multiprocessor system with multiport cache memory
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
WO1990004235A1 (en) * 1988-10-07 1990-04-19 Martin Marietta Corporation Parallel data processor
US5166903A (en) * 1988-10-25 1992-11-24 International Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5150328A (en) * 1988-10-25 1992-09-22 Internation Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5526487A (en) * 1989-02-09 1996-06-11 Cray Research, Inc. System for multiprocessor communication
US4951246A (en) * 1989-08-08 1990-08-21 Cray Research, Inc. Nibble-mode dram solid state storage device
US5224213A (en) * 1989-09-05 1993-06-29 International Business Machines Corporation Ping-pong data buffer for transferring data from one data bus to another data bus
US5247637A (en) * 1990-06-01 1993-09-21 Cray Research, Inc. Method and apparatus for sharing memory in a multiprocessor system
EP0552426A1 (en) * 1992-01-24 1993-07-28 International Business Machines Corporation Multilevel memory system
US6073185A (en) * 1993-08-27 2000-06-06 Teranex, Inc. Parallel data processor
US6173388B1 (en) 1998-04-09 2001-01-09 Teranex Inc. Directly accessing local memories of array processors for improved real-time corner turning processing
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6185667B1 (en) 1998-04-09 2001-02-06 Teranex, Inc. Input/output support for processing in a mesh connected computer
US6212628B1 (en) 1998-04-09 2001-04-03 Teranex, Inc. Mesh connected computer
US6661421B1 (en) 1998-05-21 2003-12-09 Mitsubishi Electric & Electronics Usa, Inc. Methods for operation of semiconductor memory
US6504550B1 (en) 1998-05-21 2003-01-07 Mitsubishi Electric & Electronics Usa, Inc. System for graphics processing employing semiconductor device
US6559851B1 (en) 1998-05-21 2003-05-06 Mitsubishi Electric & Electronics Usa, Inc. Methods for semiconductor systems for graphics processing
US6535218B1 (en) 1998-05-21 2003-03-18 Mitsubishi Electric & Electronics Usa, Inc. Frame buffer memory for graphic processing
US6920510B2 (en) * 2002-06-05 2005-07-19 Lsi Logic Corporation Time sharing a single port memory among a plurality of ports
US7739460B1 (en) 2004-08-30 2010-06-15 Integrated Device Technology, Inc. Integrated circuit memory systems having write-back buffers therein that support read-write-modify (RWM) operations within high capacity memory devices

Citations (3)

* Cited by examiner, † Cited by third party
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US4020466A (en) * 1974-07-05 1977-04-26 Ibm Corporation Memory hierarchy system with journaling and copy back
EP0029517A2 (en) * 1979-11-23 1981-06-03 International Business Machines Corporation Store-in-cache mode data processing apparatus
WO1982002615A1 (en) * 1981-01-19 1982-08-05 Western Electric Co Random access memory system having high-speed serial data paths

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US3471838A (en) * 1965-06-21 1969-10-07 Magnavox Co Simultaneous read and write memory configuration
US3675218A (en) * 1970-01-15 1972-07-04 Ibm Independent read-write monolithic memory array
JPS4830168A (en) * 1971-08-23 1973-04-20
US3806888A (en) * 1972-12-04 1974-04-23 Ibm Hierarchial memory system
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
US4253144A (en) * 1978-12-21 1981-02-24 Burroughs Corporation Multi-processor communication network
US4193127A (en) * 1979-01-02 1980-03-11 International Business Machines Corporation Simultaneous read/write cell
JPS5837633B2 (en) * 1979-07-23 1983-08-17 富士通株式会社 Buffer memory storage control method
DE2948159C2 (en) * 1979-11-29 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Integrated memory module with selectable operating functions
JPS5750381A (en) * 1980-09-12 1982-03-24 Nec Corp Information processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4020466A (en) * 1974-07-05 1977-04-26 Ibm Corporation Memory hierarchy system with journaling and copy back
EP0029517A2 (en) * 1979-11-23 1981-06-03 International Business Machines Corporation Store-in-cache mode data processing apparatus
WO1982002615A1 (en) * 1981-01-19 1982-08-05 Western Electric Co Random access memory system having high-speed serial data paths

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 7B, December 1980, pages 3461-3463, New York, US; J. YAMOUR: "Odd/even interleave cache with optimal hardware array cost, cycle time and variable data port width" *
PATENTS ABSTRACTS OF JAPAN, vol. 6, no. 125 (P-127)[1003], 10th July 1982; & JP-A-57 050 381 (NIPPON DENKI K.K.) 24-03-1982 *

Also Published As

Publication number Publication date
DE3381653D1 (en) 1990-07-19
EP0100943A2 (en) 1984-02-22
JPS5930289A (en) 1984-02-17
US4489381A (en) 1984-12-18
EP0100943B1 (en) 1990-06-13

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