EP0531599B1 - Configurable gigabit/s switch adapter - Google Patents
Configurable gigabit/s switch adapter Download PDFInfo
- Publication number
- EP0531599B1 EP0531599B1 EP91810728A EP91810728A EP0531599B1 EP 0531599 B1 EP0531599 B1 EP 0531599B1 EP 91810728 A EP91810728 A EP 91810728A EP 91810728 A EP91810728 A EP 91810728A EP 0531599 B1 EP0531599 B1 EP 0531599B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- payload
- storage
- fixed length
- header
- buffer memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3063—Pipelined operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
- H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Description
- FIG. 1
- shows a global block diagram of a switching subsystem comprising a hardware implementation of the present invention.
- FIG. 2A
- shows a detailed block diagram of the transmitter part of a protocol adapter.
- FIG. 2B
- shows a detailed block diagram of the receiver part of a protocol adapter.
- FIG. 3
- shows fixed length cells with fixed length headers.
- FIG. 4
- shows a detailed block diagram of the receiver part of the protocol adapter.
- FIG. 5
- is a schematic diagram of the header processor internal data structure.
- FIG. 6
- shows a time diagram of a re-alignment and pipelining example.
- FIG. 7A - C
- shows a header processor cycle diagram.
- Segmentation and re-assembly,
- Error detection and recovery,
- Support of user frames with different priority,
- Data buffering,
- Buffer management,
- Support of multiple virtual channels.
- CONTROL
- FIRST
- MIDDLE
- LAST
- ONLY
- ATM
- 1.) done
- 2.) wait_next
- 3.) buf_full
- 4.) end
Claims (15)
- Method for transforming fixed length cells carrying payload preceded by a fixed size header into user frames, said payload and said fixed size header being processed separately, said method being characterized by the following steps:feeding said fixed length cells into a parallel bus (54),separating said payload from said fixed size header, said payload being transmitted along said parallel bus (54) via a re-alignment unit (47) to a buffer memory (52),processing said fixed size header separately to determine a storage address of a storage section in said buffer memory (52),putting storage addresses of storage sections in said buffer memory (52) in queuing means to support at least one virtual channel, the payload of said virtual channel being accessible by reading the respective storage addresses from said queuing means,shifting said payload to the boundary of said parallel bus by means of said re-alignment unit (47) after said fixed size header has been separated, and thenbuffering said payload in said storage section of said buffer memory (52) made accessible by said storage address,
- The method of claim 1, wherein said fixed length cell is transformed into a user frame byprocessing said fixed size header which has been separated from said payload, while transmitting said payload along said parallel bus (54) and shifting said payload to the boundary of said parallel bus (54), to determine if space for said payload is available in said buffer memory (52), by employing system state variables of said buffer memory (52),using said determined storage address of a storage section for writing said payload into said storage section of said buffer memory (52) if said space is available,reading said payload from said storage section, using said storage address,forming a user frame according to a defined data transmission protocol, andtransmitting said user frame.
- The method of claim 2, wherein said storage address of a storage section is determined after a fixed number of bus cycles such that said payload which has been delayed during these bus cycles, can be stored in the storage section corresponding to said storage address.
- The method of claim 2, wherein the storage addresses of storage sections are kept in queues such that the payload stored in these storage sections can be retrieved for the generation of said user frames by successively reading the storage addresses of the storage sections from said queues.
- The method of claim 2, wherein fixed length cells of different priority are supported by storing the storage addresses of the storage sections where the payload of said fixed length cells has been stored in respective queues such that for the generation of user frames the payload with the highest priority can be taken from the corresponding storage section prior to any payload with lower priority.
- Method for segmenting user frames into fixed length cells, said fixed length cells carrying payload taken from said user frames being preceded by a fixed size header, characterized in that it comprises the steps of:buffering payload of said user frames in a storage section of a buffer memory (24') using a corresponding storage address,keeping said corresponding storage address in a queue (28.1', 28.2') such that said payload can be retrieved from said buffer memory (24') by taking said corresponding storage address from said queue (28.1', 28.2'),generating and processing said fixed size header separately prior to attaching part of said payload to said fixed size header, this step being carried out concurrently, i.e. while taking part of said payload from said storage section,taking part of said payload out of said buffer memory (24') using said corresponding storage address and inserting said payload into a fixed length cell, andtransmitting said fixed length cell consisting of said payload attached to said fixed size header.
- The method of claim 6, wherein said payload is read from said storage section by taking its storage address from said queue (28.1', 28.2') and the payload is delayed during the generation of said fixed size header which is presented after a fixed number of clock cycles.
- The method of claim 6, wherein said payload is re-aligned to a fixed length cell prior to the re-assembly of said fixed length cell such that said payload can be inserted into said fixed length cell directly adjacent to said fixed size header without wasting transmission capacity.
- The method of claim 6, wherein user frames of different priority are supported by storing the storage addresses of the storage sections where each payload is stored in at least one queue (28.1', 28.2') such that for the generation of said fixed length cells the payload with the highest priority can be taken from the storage section where it has been stored by taking the storage address of said storage section from said queue (28.1', 28.2') prior to taking the storage address of the storage section of the next payload with lower priority from said queue (28.1', 28.2').
- Apparatus for transforming fixed length cells into user frames, said fixed length cells carrying payload being preceded by a fixed size header, characterized by:means for receiving a fixed length cell and feeding it into a parallel bus,means (23) for separating said payload from said fixed size header fed into said parallel bus,a header processor (22), connected to said parallel bus, for separately processing said fixed size header, to determine a storage address of a storage section in a buffer memory (24),re-alignment means for shifting said payload, received via said parallel bus, to the boundary of said parallel busmeans (23.3, 23.4) for delaying said payload being separated from said fixed size header and being re-aligned until said storage address is available,means (24, 26) for storing said payload in a storage section of said buffer memory (24) made accessible by said storage address,queuing means (25) for keeping said storage address corresponding to said payload in a queue,means for retrieving said payload from said storage section by successively taking the respective storage addresses from the queue of said queuing means (25),means for the formation of said user frame, carrying said retrieved payload, in accordance with a given data transmission protocol defined by the environment, andmeans for the transmission of said user frames.
- The apparatus of claim 10, further comprising queuing means (28.1, 28.2) for supporting the transmission of fixed length cells with different priority by keeping the respective storage address in a queue of said queueing means such that the payload with highest priority can be retrieved from said storage section of said buffer memory (24) by taking its storage address from said queue prior to any storage address of payload with lower priority.
- Apparatus for transforming user frames which carry payload into fixed length cells, said fixed length cells comprising part of said payload being preceded by a fixed size header, characterized by:means for buffering said payload in a storage section of a buffer memory (24'),queuing means (28.1', 28.2') for keeping the storage address of said storage section in a queue being part of said queuing means,a header processor (22') taking said storage address from the queue of said queuing means (28.1', 28.2') and generating a fixed size header,means for forming said fixed length cell by attaching a part of said payload taken from said buffer memory (24'), which has been retrieved using said storage address taken from said queue, to said header, andmeans for transmitting said fixed length cell.
- The apparatus of claim 12, wherein said header processor (22') takes a storage address corresponding to payload with highest priority from the queue of said queuing means (28.1', 28.2') prior to storage addresses of payload with lower priority.
- The apparatus of claim 12, further comprising a re-align unit (23') for re-aligning part of said payload taken from a storage section of said buffer memory (24') prior to attaching it to said fixed size header such that the part of said payload can be inserted into said fixed length cell directly adjacent to said fixed size header.
- A data transmission network at least comprising a switch fabric (11) for switching fixed lengths cells, the apparatus of claim 12 for transforming user frames into said fixed length cells and transmitting said fixed length cells to said switch fabric (11), or the apparatus of claim 10 for receiving said fixed length cells being routed through said switch fabric and for transforming said received fixed length cells into user frames prior to transmitting them.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69129851T DE69129851T2 (en) | 1991-09-13 | 1991-09-13 | Configurable gigabit / s switch adapter |
EP91810728A EP0531599B1 (en) | 1991-09-13 | 1991-09-13 | Configurable gigabit/s switch adapter |
US07/832,127 US5311509A (en) | 1991-09-13 | 1992-02-06 | Configurable gigabits switch adapter |
JP19860092A JP2788577B2 (en) | 1991-09-13 | 1992-07-24 | Frame conversion method and apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP91810728A EP0531599B1 (en) | 1991-09-13 | 1991-09-13 | Configurable gigabit/s switch adapter |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0531599A1 EP0531599A1 (en) | 1993-03-17 |
EP0531599B1 true EP0531599B1 (en) | 1998-07-22 |
Family
ID=8208879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91810728A Expired - Lifetime EP0531599B1 (en) | 1991-09-13 | 1991-09-13 | Configurable gigabit/s switch adapter |
Country Status (4)
Country | Link |
---|---|
US (1) | US5311509A (en) |
EP (1) | EP0531599B1 (en) |
JP (1) | JP2788577B2 (en) |
DE (1) | DE69129851T2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2015569A1 (en) * | 2006-05-02 | 2009-01-14 | Media Global Links Co., Ltd. | Video signal switching system |
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1992
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EP0531599A1 (en) | 1993-03-17 |
JP2788577B2 (en) | 1998-08-20 |
DE69129851D1 (en) | 1998-08-27 |
DE69129851T2 (en) | 1999-03-25 |
JPH05219098A (en) | 1993-08-27 |
US5311509A (en) | 1994-05-10 |
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