EP0572168A2 - Method for matching symbol rates in a communications network - Google Patents
Method for matching symbol rates in a communications network Download PDFInfo
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- EP0572168A2 EP0572168A2 EP93303903A EP93303903A EP0572168A2 EP 0572168 A2 EP0572168 A2 EP 0572168A2 EP 93303903 A EP93303903 A EP 93303903A EP 93303903 A EP93303903 A EP 93303903A EP 0572168 A2 EP0572168 A2 EP 0572168A2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/345—Modifications of the signal space to allow the transmission of additional information
- H04L27/3455—Modifications of the signal space to allow the transmission of additional information in order to facilitate carrier recovery at the receiver end, e.g. by transmitting a pilot or by using additional signal points to allow the detection of rotations
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- the present invention relates to communications systems and, more particularly, to such systems which couple data supplied to the system at a rate controlled by the customer or data supplier.
- a customer supplies data for transport through a modem or transceiver to a communications system at a data rate that is controlled by the communications system.
- the data supplied by the customer is typically synchronized with a clock signal coupled from the communications system to the customer.
- the customer supplies data to the communications system at a rate which is customer-controlled.
- Such systems can utilize either two or four conductors. In two-conductor systems, bidirectional communications are provided through a single conductor pair while in four-conductor systems the signals coupled in each direction are transported by different conductor pairs. In either case, the data rates in both directions, each controlled by the customer at each system end, can be the same or different from one another.
- Echoes or crosstalk is a problem in communications systems which can often be substantially eliminated by the use of echo cancellers.
- Such cancellers can be implemented within an analog "front end" interpolator of the transceiver.
- A/D analog-to-digital
- the echo canceller then subtracts the synthesized echo from the digital samples provided by the converter using the transmit symbols provided by the transceiver's transmitter.
- the echo-free samples are then converted back to an analog signal by a digital-to-analog converter (D/A), passed through a low-pass filter and supplied to a second A/D converter.
- D/A digital-to-analog converter
- This second A/D converter provides digital samples to a conventional receiver which outputs the received data.
- the transmitter provides the transmit symbols which are pulse shaped by shaping circuitry and thence converted into an analog signal by a D/A converter.
- the first A/D converter in the receiver and both D/A converters are strobed by the transmit clock while the second A/D converter is strobed by the receive clock.
- the challenge in implementing this front end is to provide precision converters on a single integrated circuit with asynchronous transmit and receive clocks. This is often difficult, if not impossible, to achieve.
- transceivers utilize A/D and D/A converters respectively disposed in the receiver and transmitter of the transceiver which are strobed by a common sample clock.
- the A/D converter forms samples of the incoming signal received from a remote location while the D/A converter in the transmitter forms samples of the signal to be transmitted to the remote location.
- the output of the A/D converter is coupled through the echo canceller to a digital interpolator.
- the digital interpolator alters the sample values it receives in response to a control signal generated by a timing recovery circuit.
- the control signal is representative of any asynchronism between the common sample clock and the remote transmitter clock.
- the effect of the interpolator therefore, is to alter the timing phase of the common sample clock source and provide the samples which would have been formed had the common sample clock been synchronized to the transmitter clock at the remote location. While this solution provides satisfactory results in many applications, the cost of implementing a digital interpolator for high-speed, i.e., ⁇ .5 megabits/second cannot be provided within the desired cost objectives.
- a synchronization scheme is proposed for bidirectional data applications where the customer supplies data for transmission at a rate which is customer-controlled.
- the customer data in each transmission direction, is converted into data symbols in a predetermined signal constellation.
- additional symbols are added to raise the symbol rate to one that is higher than that provided by the data symbols alone.
- the additional symbols are those lying outside of the signal constellation and are not used to represent customer data.
- the higher symbol rate in each transmission direction is the same, or the higher symbol rates in the two directions are related to one another by a rational number.
- these additional symbols are removed and the customer data is recovered from its representative data symbols.
- the present invention solves the prior art problem associated with echo or crosstalk cancellation, avoids the need for a digital interpolator and can be readily implemented on a semiconductor device.
- System 100 transports customer data received from a first transceiver 101 to a second transceiver 102 and vice versa via a four-conductor communications path 103.
- This customer data may be representative of a variety of data signals including digitized speech and/or video, ASCII characters, etc.
- each transceiver utilizes carrierless amplitude/phase (AM/PM) modulation.
- AM/PM carrierless amplitude/phase
- Path 103 includes a first conductor pair 104 for transporting data from transceiver 101 to transceiver 102 and a second conductor pair 105 for transporting data from transceiver 102 to transceiver 101.
- Transceivers 101 and 102 each convert the customer data bits into signals which can be coupled through the communications path.
- transceiver 101 customer data bits received at a rate controlled by the customer are scrambled using conventional apparatus (not shown) and supplied to transmitter portion 106. These scrambled customer data bits may be arranged into a particular frame format or may be unstructured, i.e., not arranged into any particular frame format, since the operation of applicants' invention does not rely on the presence or absence of a frame format.
- encoder 107 maps each of a plurality of m successive scrambled customer data bits, where m is a predetermined integer, into one data symbol in a signal constellation.
- the signal constellation includes a plurality of data symbols and each different combination of m successive scrambled data bits is mapped into a different data symbol.
- the signal constellation also includes additional symbols which are not used to represent customer data bits but are added as required to increase the symbol rate over that provided by the conversion of customer data bits into data symbols by encoder 107.
- Constellation 200 includes 32 data symbols, designated by reference numeral 201, which are representative of customer data bits. Each of these data symbols is representative of a different combination of five consecutive customer data bits and has two symbol components designated by a n and b n . Symbol components a n and b n can take on the values of ⁇ 1, ⁇ 3, and ⁇ 5 .
- the additional symbols designated by reference numeral 202 are those inserted to increase the symbol rate over that provided by encoder 107. In the illustrative signal constellation there are four such additional symbols and the a n and b n values for these symbols are ⁇ 5. The particular one of the four symbols 202 inserted at any time may be determined randomly or may follow a predetermined sequential order.
- the rate of data symbols outputted from encoder 107 is f2, where f2 is a submultiple of the rate of customer supplied data bits and the particular submultiple is determined by the number of bits, m, mapped into each symbol. More specifically, in the illustrative embodiment of FIG. 2, five bits are mapped into one data symbol and f2 is 1 5 of the customer-controlled data bit rate.
- Rate converter 108 receives each data symbol outputted by encoder 107 and selectively adds additional symbols. These additional symbols raise the symbol rate from f2 to f1.
- Rate f1 is selected to be higher than the maximum value of f2, it being understood that as the customer-controlled data bit rate can vary up to some predefined maximum limit, it follows that f2 can also vary to 1 m times this limit.
- Rate f1 can be a predetermined fixed or a variable quantity.
- the outputted data symbols from encoder 107 are represented by dots and the additional symbols are represented by "Xs" interposed between the dots.
- the sequence of data and additional symbols provided by rate converter 108 are then passed through shaping filter 109, D/A converter 110 and low-pass filter 111 before being coupled to first conductor pair 104.
- D/A converter 110 is strobed by a sampling clock signal set to ⁇ f1, where ⁇ is a predefined scalar quantity typically equal to 3 or 4 and f1 is the transmit symbol clock of the communications system.
- the communications path 103 is characterized as being one wherein a portion of the signal transmitted through first conductor pair 104 is coupled into second conductor pair 105 and vice versa. This coupling is represented by arrows 115. Such coupling produces what is generically referred to as near-end crosstalk in four-conductor systems and near-end echoes in two-conductor systems.
- the receiver portion of each of transceivers 101 and 102 incorporates a near-end crosstalk (NEXT) canceller.
- the NEXT canceller synthesizes the crosstalk in a transceiver's received signal using that transceiver's transmitted signal. This synthesized crosstalk can then be subtracted from the transceiver's received signal so as to eliminate the crosstalk portion thereof.
- the received analog signal is coupled to low-pass filter 121 within receiver portion 120 of transceiver 102.
- the filtered signal is then supplied to A/D converter 122 which samples the analog signal and outputs a digital representation of each sample.
- A/D converter is strobed by clock signal set to ⁇ f1.
- Equalizer 123 removes the distortion from these digital representations of each sample in well-known fashion.
- NEXT canceller 131 synthesizes the crosstalk portion of the equalizer output signal using the symbols to be transmitted by the transmitter portion 130 of transceiver 102. Such symbols, including the symbols 201 and 202 of FIG. 2, are provided by rate converter 108 within transmitter portion 130. Adder 124 then digitally subtracts this synthesized crosstalk from the output of equalizer 123.
- Decision device 125 maps each of the "crosstalk-free,” equalized digital representations into one of a plurality of permissible symbols which in the illustrative embodiment are the symbols 201 and 202 in FIG. 2.
- the output of decision device 125 is at a rate f1 since it includes the additional symbols 202.
- Rate converter 126 detects and extracts each additional symbol from the symbols provided by decision device 125.
- the rate converter also maps each of the data symbols 201 into its corresponding data bits.
- the bits representative of each data symbol 201 are outputted in parallel.
- Parallel-in, serial-out (PI/SO) converter 127 forms a serial stream of data bits at a rate of mf2 on lead 128.
- scrambled customer data bits are received by transmitter 130 at a customer-controlled rate.
- This customer may be the same or different from the customer supplying data bits to transmitter 106.
- the rate of customer data bits supplied in each of the opposite directions of communications can vary independently of one another but in no event can exceed some predetermined limit.
- the data communications from transmit portion 130 of transceiver 102 through second conductor pair 105 to receiver portion 140 of transceiver 101 is substantially identical to that already described. Accordingly, the structure of transmitter portion 130 and that of receiver portion 140 are respectively identical to transmitter portion 106 and receiver portion 120 except for the addition of timing recovery circuit 129. As a result, the same reference numerals are used to designate identical circuitry within both transmitters and receivers.
- Timing recovery circuit 129 recovers the symbol clock f1 from the digital samples provided by A/D converter 122 in well-known fashion. Circuit 129 then forms the sampling clock ⁇ f1 which strobes A/D converter 122 and D/A converter 110 and recovers a transmit clock f1 which is coupled to rate converter 126. It should be noted that in the disclosed embodiment the rate f1 from transmitter 130 to receiver 140 is synchronized with the rate f1 in the opposite direction.
- the symbol rate transmitted in each direction is the same and is at a rate f1 which is higher than that provided by the conversion of customer data bits into symbols.
- FIG. 3 shows a more detailed schematic drawing of the circuitry within a preferred implementation of rate converter 126.
- this embodiment greatly reduces the jitter introduced by the removal of the additional symbols from the recovered symbol stream provided by the decision device.
- the outputted symbols from decision device 125 are coupled to detector and decoder 303 which detects the occurrence of each of the additional symbols 202 of FIG. 2 and couples an output pulse to bandpass filter (BPF) 302 on each detected occurrence.
- BPF bandpass filter
- This output pulse is also used to inhibit the write clock for first-in first-out (FIFO) device 304. This inhibiting of the FIFO write clock by detector and decoder 303 effectively extracts the symbols 202 from the sequence of symbols 201 and 202.
- detector and decoder 303 also converts each of the data symbols 201 into their respective bit representations.
- the bit representations of each of the data symbols 201 outputted from decision device 125 are written into FIFO 304.
- a BPF designated by numeral 301 filters the recovered line symbol clock f1 provided by timing recovery circuit 129.
- the sinusoids generated by BPFs 301 and 302 are respectively coupled to Hilbert transform filters 305 and 306 which shift each received sinusoid by 90 degrees.
- Multiplier 307 forms the product of the outputs of Hilbert filters 305 and 306 which may be respectively represented by sin (2 ⁇ f1t) sin (2 ⁇ f0t).
- Multiplier 308 forms the product of the outputs of BPFs 301 and 302 which may be respectively represented by cos (2 ⁇ f1t) cos (2 ⁇ f0t).
- the outputs of multipliers 307 and 308 are combined via adder 309. This combination may be represented by cos ((2 ⁇ f1 -2 ⁇ f0)t) which is equal to cos (2 ⁇ f2t), a sinusoid having the frequency of the symbols representative of the encoded customer data bits.
- the symbol clock f2 is shaped into a square wave by reshaper 310 and used as a read clock for FIFO 304.
- the frequency of this square wave is also multiplied by m via frequency multiplier 311 to recover a clock synchronous with the customer data bits supplied to transmitter 106.
- m 5.
- This clock signal is used to strobe parallel-in, serial-out (PI/SO) shift register 127 of FIG. 1.
- the parallel output of FIFO 304 is the scrambled customer data bits representative of one symbol 201. These bits are converted into serial form by PI/SO converter 127.
- additional symbols designated by reference numeral 202 and not used to represent customer data are utilized, such additional symbols could be a combination of data symbols 201 which combination has a virtual zero probability of occurring from the encoding of customer data bits.
- the symbol rate f1 is the same in each transmission direction, this need not be so. Indeed, the symbol rates may be different so long as they are related to one another by a rational number and the corresponding sampling rates for the A/D and D/A converters satisfy the Nyquist criterion.
- the customer data bits supplied to each transmitter are scrambled, they can also be coded after scrambling using, for example, a convolutional code. In such case, encoder 107 would be a trellis encoder.
Abstract
Description
- The present invention relates to communications systems and, more particularly, to such systems which couple data supplied to the system at a rate controlled by the customer or data supplier.
- In some data system applications, a customer supplies data for transport through a modem or transceiver to a communications system at a data rate that is controlled by the communications system. In such applications, the data supplied by the customer is typically synchronized with a clock signal coupled from the communications system to the customer. In other data system applications, the customer supplies data to the communications system at a rate which is customer-controlled. Such systems can utilize either two or four conductors. In two-conductor systems, bidirectional communications are provided through a single conductor pair while in four-conductor systems the signals coupled in each direction are transported by different conductor pairs. In either case, the data rates in both directions, each controlled by the customer at each system end, can be the same or different from one another.
- Echoes or crosstalk is a problem in communications systems which can often be substantially eliminated by the use of echo cancellers. Such cancellers can be implemented within an analog "front end" interpolator of the transceiver. In this implementation, in the transceiver's receiver, the incoming line signal from a two- or four-wire communications system is sampled by a first analog-to-digital (A/D) converter. The echo canceller then subtracts the synthesized echo from the digital samples provided by the converter using the transmit symbols provided by the transceiver's transmitter. The echo-free samples are then converted back to an analog signal by a digital-to-analog converter (D/A), passed through a low-pass filter and supplied to a second A/D converter. This second A/D converter provides digital samples to a conventional receiver which outputs the received data. In the transmit direction, the transmitter provides the transmit symbols which are pulse shaped by shaping circuitry and thence converted into an analog signal by a D/A converter. For proper operation of the echo canceller, the first A/D converter in the receiver and both D/A converters are strobed by the transmit clock while the second A/D converter is strobed by the receive clock. The challenge in implementing this front end is to provide precision converters on a single integrated circuit with asynchronous transmit and receive clocks. This is often difficult, if not impossible, to achieve.
- To eliminate this problem, more recently developed transceivers utilize A/D and D/A converters respectively disposed in the receiver and transmitter of the transceiver which are strobed by a common sample clock. The A/D converter forms samples of the incoming signal received from a remote location while the D/A converter in the transmitter forms samples of the signal to be transmitted to the remote location. To compensate for the fact that the A/D converter in the receiver is not synchronized to the transmitter clock at the remote location, the output of the A/D converter is coupled through the echo canceller to a digital interpolator. The digital interpolator alters the sample values it receives in response to a control signal generated by a timing recovery circuit. The control signal is representative of any asynchronism between the common sample clock and the remote transmitter clock. The effect of the interpolator, therefore, is to alter the timing phase of the common sample clock source and provide the samples which would have been formed had the common sample clock been synchronized to the transmitter clock at the remote location. While this solution provides satisfactory results in many applications, the cost of implementing a digital interpolator for high-speed, i.e., ≧ .5 megabits/second cannot be provided within the desired cost objectives.
- It would therefore be desirable if a synchronization scheme could be developed which is suitable for high-speed data applications which could be readily implemented at low cost in an integrated circuit.
- A synchronization scheme is proposed for bidirectional data applications where the customer supplies data for transmission at a rate which is customer-controlled. In accordance with the present invention, in each transmission direction, the customer data is converted into data symbols in a predetermined signal constellation. In response to these data symbols, additional symbols are added to raise the symbol rate to one that is higher than that provided by the data symbols alone. In the disclosed embodiment, the additional symbols are those lying outside of the signal constellation and are not used to represent customer data.
- The higher symbol rate in each transmission direction is the same, or the higher symbol rates in the two directions are related to one another by a rational number. At the receiver, these additional symbols are removed and the customer data is recovered from its representative data symbols.
- Advantageously, the present invention solves the prior art problem associated with echo or crosstalk cancellation, avoids the need for a digital interpolator and can be readily implemented on a semiconductor device.
-
- FIG. 1 is a block-schematic diagram of an illustrative communications system incorporating an embodiment of the present invention;
- FIG. 2 is a diagram of an illustrative signal constellation which incorporates the principles of the present invention; and
- FIG. 3 is a block-schematic diagram of an embodiment of the
rate converter 126 of FIG. 1. - An
illustrative communications system 100 incorporating the present invention is shown in FIG. 1.System 100 transports customer data received from afirst transceiver 101 to asecond transceiver 102 and vice versa via a four-conductor communications path 103. This customer data may be representative of a variety of data signals including digitized speech and/or video, ASCII characters, etc. For purposes of illustration, it is assumed that each transceiver utilizes carrierless amplitude/phase (AM/PM) modulation. It is, of course, understood that the present invention is not limited to any particular modulation format and, indeed, can be used with virtually any modulation scheme which maps customer data bits into symbols.Path 103 includes afirst conductor pair 104 for transporting data fromtransceiver 101 totransceiver 102 and asecond conductor pair 105 for transporting data fromtransceiver 102 totransceiver 101.Transceivers - In
transceiver 101, customer data bits received at a rate controlled by the customer are scrambled using conventional apparatus (not shown) and supplied totransmitter portion 106. These scrambled customer data bits may be arranged into a particular frame format or may be unstructured, i.e., not arranged into any particular frame format, since the operation of applicants' invention does not rely on the presence or absence of a frame format. Within the transmitter portion,encoder 107 maps each of a plurality of m successive scrambled customer data bits, where m is a predetermined integer, into one data symbol in a signal constellation. The signal constellation, as will be discussed, includes a plurality of data symbols and each different combination of m successive scrambled data bits is mapped into a different data symbol. In accordance with the present invention, the signal constellation also includes additional symbols which are not used to represent customer data bits but are added as required to increase the symbol rate over that provided by the conversion of customer data bits into data symbols byencoder 107. - Refer now to FIG. 2 which shows an
illustrative signal constellation 200 for use withinsystem 100. Constellation 200, as shown, includes 32 data symbols, designated byreference numeral 201, which are representative of customer data bits. Each of these data symbols is representative of a different combination of five consecutive customer data bits and has two symbol components designated by an and bn. Symbol components an and bn can take on the values of ±1, ±3, and ±5 . The additional symbols designated byreference numeral 202 are those inserted to increase the symbol rate over that provided byencoder 107. In the illustrative signal constellation there are four such additional symbols and the an and bn values for these symbols are ±5. The particular one of the foursymbols 202 inserted at any time may be determined randomly or may follow a predetermined sequential order. - Refer back now to FIG. 1. The rate of data symbols outputted from
encoder 107 is f₂, where f₂ is a submultiple of the rate of customer supplied data bits and the particular submultiple is determined by the number of bits, m, mapped into each symbol. More specifically, in the illustrative embodiment of FIG. 2, five bits are mapped into one data symbol and f₂ isRate converter 108 receives each data symbol outputted byencoder 107 and selectively adds additional symbols. These additional symbols raise the symbol rate from f₂ to f₁. Rate f₁ is selected to be higher than the maximum value of f₂, it being understood that as the customer-controlled data bit rate can vary up to some predefined maximum limit, it follows that f₂ can also vary toencoder 107 are represented by dots and the additional symbols are represented by "Xs" interposed between the dots. The sequence of data and additional symbols provided byrate converter 108 are then passed through shapingfilter 109, D/Aconverter 110 and low-pass filter 111 before being coupled tofirst conductor pair 104. D/A converter 110 is strobed by a sampling clock signal set to λf₁, where λ is a predefined scalar quantity typically equal to 3 or 4 and f₁ is the transmit symbol clock of the communications system. - The
communications path 103 is characterized as being one wherein a portion of the signal transmitted throughfirst conductor pair 104 is coupled intosecond conductor pair 105 and vice versa. This coupling is represented byarrows 115. Such coupling produces what is generically referred to as near-end crosstalk in four-conductor systems and near-end echoes in two-conductor systems. In the illustrative embodiment four-conductor communications system of FIG. 1, the receiver portion of each oftransceivers - As shown in FIG. 1, after propagating through
conductor pair 103 to a remote location, the received analog signal is coupled to low-pass filter 121 withinreceiver portion 120 oftransceiver 102. The filtered signal is then supplied to A/D converter 122 which samples the analog signal and outputs a digital representation of each sample. A/D converter is strobed by clock signal set to λf₁.Equalizer 123 removes the distortion from these digital representations of each sample in well-known fashion. -
NEXT canceller 131 synthesizes the crosstalk portion of the equalizer output signal using the symbols to be transmitted by thetransmitter portion 130 oftransceiver 102. Such symbols, including thesymbols rate converter 108 withintransmitter portion 130.Adder 124 then digitally subtracts this synthesized crosstalk from the output ofequalizer 123. -
Decision device 125 maps each of the "crosstalk-free," equalized digital representations into one of a plurality of permissible symbols which in the illustrative embodiment are thesymbols decision device 125 is at a rate f₁ since it includes theadditional symbols 202.Rate converter 126 detects and extracts each additional symbol from the symbols provided bydecision device 125. The rate converter also maps each of thedata symbols 201 into its corresponding data bits. The bits representative of eachdata symbol 201 are outputted in parallel. Parallel-in, serial-out (PI/SO)converter 127 forms a serial stream of data bits at a rate of mf₂ onlead 128. - In the opposite direction, scrambled customer data bits are received by
transmitter 130 at a customer-controlled rate. This customer may be the same or different from the customer supplying data bits totransmitter 106. The rate of customer data bits supplied in each of the opposite directions of communications can vary independently of one another but in no event can exceed some predetermined limit. Aside from this fact, the data communications from transmitportion 130 oftransceiver 102 throughsecond conductor pair 105 toreceiver portion 140 oftransceiver 101, is substantially identical to that already described. Accordingly, the structure oftransmitter portion 130 and that ofreceiver portion 140 are respectively identical totransmitter portion 106 andreceiver portion 120 except for the addition of timingrecovery circuit 129. As a result, the same reference numerals are used to designate identical circuitry within both transmitters and receivers. Timingrecovery circuit 129 recovers the symbol clock f₁ from the digital samples provided by A/D converter 122 in well-known fashion.Circuit 129 then forms the sampling clock λf₁ which strobes A/D converter 122 and D/A converter 110 and recovers a transmit clock f₁ which is coupled torate converter 126. It should be noted that in the disclosed embodiment the rate f₁ fromtransmitter 130 toreceiver 140 is synchronized with the rate f₁ in the opposite direction. - It should be noted that in
communications systems 100 the symbol rate transmitted in each direction is the same and is at a rate f₁ which is higher than that provided by the conversion of customer data bits into symbols. This advantageously allows the use of a common sample clock, referenced as λf₁, for the A/D and D/A converters of a transceiver and also avoids the need to incorporate a digital interpolator in each receiver portion. - Refer now to FIG. 3 which shows a more detailed schematic drawing of the circuitry within a preferred implementation of
rate converter 126. Advantageously, this embodiment greatly reduces the jitter introduced by the removal of the additional symbols from the recovered symbol stream provided by the decision device. The outputted symbols fromdecision device 125 are coupled to detector anddecoder 303 which detects the occurrence of each of theadditional symbols 202 of FIG. 2 and couples an output pulse to bandpass filter (BPF) 302 on each detected occurrence. This output pulse is also used to inhibit the write clock for first-in first-out (FIFO)device 304. This inhibiting of the FIFO write clock by detector anddecoder 303 effectively extracts thesymbols 202 from the sequence ofsymbols decoder 303 also converts each of thedata symbols 201 into their respective bit representations. The bit representations of each of thedata symbols 201 outputted fromdecision device 125 are written intoFIFO 304. - A BPF designated by numeral 301 filters the recovered line symbol clock f₁ provided by timing
recovery circuit 129. The sinusoids generated byBPFs filters BPFs additional symbols 202. Using these representations, we may represent the outputs of Hilbert filters 305 and 306 respectively by sin (2πf₁t) and sin (2πf₀t).Multiplier 307 forms the product of the outputs of Hilbert filters 305 and 306 which may be respectively represented by sin (2πf₁t) sin (2πf₀t).Multiplier 308 forms the product of the outputs ofBPFs multipliers adder 309. This combination may be represented by cos ((2πf₁ -2πf₀)t) which is equal to cos (2πf₂t), a sinusoid having the frequency of the symbols representative of the encoded customer data bits. - The symbol clock f₂ is shaped into a square wave by
reshaper 310 and used as a read clock forFIFO 304. The frequency of this square wave is also multiplied by m viafrequency multiplier 311 to recover a clock synchronous with the customer data bits supplied totransmitter 106. In the illustrative embodiment m = 5. This clock signal is used to strobe parallel-in, serial-out (PI/SO)shift register 127 of FIG. 1. The parallel output ofFIFO 304 is the scrambled customer data bits representative of onesymbol 201. These bits are converted into serial form by PI/SO converter 127. - It should, of course, be noted that while the present invention has been described in terms of an illustrative embodiment, other arrangements will be apparent to those of ordinary skill in the art. First, for example, while the embodiments of the present invention have been described in reference to discrete functional elements, the function of one or more of these elements can be provided by one or more appropriately programmed general-purpose processors, or special-purpose integrated circuits, or digital signal processors, or an analog or hybrid counterpart of any of these devices. Second, while the present invention has been described in reference to a four-conductor communications system, it is also applicable to a two-conductor system. Third, while in the disclosed embodiment additional symbols, designated by
reference numeral 202 and not used to represent customer data are utilized, such additional symbols could be a combination ofdata symbols 201 which combination has a virtual zero probability of occurring from the encoding of customer data bits. Fourth, while in the disclosed embodiment the symbol rate f₁ is the same in each transmission direction, this need not be so. Indeed, the symbol rates may be different so long as they are related to one another by a rational number and the corresponding sampling rates for the A/D and D/A converters satisfy the Nyquist criterion. Lastly, while the customer data bits supplied to each transmitter are scrambled, they can also be coded after scrambling using, for example, a convolutional code. In such case,encoder 107 would be a trellis encoder.
Claims (10)
- Apparatus for use in a communications system wherein data is transmitted through a communications facility, said apparatus comprising
means (107) responsive to digital signals for forming data symbols (201) at a first symbol rate, each data symbol being representative of a plurality of digital signals and lying in a signal constellation including a plurality of data symbols;
means (108) responsive to the formed data symbols for providing additional symbols (202) so as to raise the symbol rate to a second symbol rate higher than said first rate; and
means (109, 110, 111) for transmitting said data symbols and additional symbols at said second symbol rate to said communications facility. - The apparatus of claim 1 wherein said additional symbols lie outside of said signal constellation and are not used to represent said digital signals.
- The apparatus of claim 1 wherein said additional symbols lie within said signal constellation and individually are used to represent said digital signal, said providing means inserting a plurality of additional symbols between two data symbols formed by said forming means.
- The apparatus of any of the preceding claims further including
means (121, 122, 123) for receiving a sequence of said data symbols and said additional symbols from said communications facility; and
means (126) for extracting said additional symbols from said sequence and for mapping each data symbol into its representative digital signal. - The apparatus of claim 4 wherein said data symbols and said additional symbols are received at a third rate from said communications facility, said third rate being equal to said second rate or related thereto by a rational multiple.
- Apparatus for use in a communications system wherein data is transmitted through a communications facility, said apparatus comprising
means for receiving a sequence of data symbols and additional symbols as transmitted by apparatus of any of the preceding claims from said communications facility at said second symbol rate, each data symbol being representative of a plurality of digital signals and lying in a signal constellation including a plurality of data symbols; and
means for extracting said additional symbols from said sequence and for mapping each data symbol into its representative digital signal, said extracted additional symbols not being used for any processing of the representative digital signals mapped from the data symbols. - A method for use in a communications system wherein data is transmitted through a communications facility, said method comprising the steps of
forming data symbols representative of digital signals at a first symbol rate, each data symbol being representative of a plurality of digital signals and lying in a signal constellation including a plurality of data symbols;
providing additional symbols so as to raise said first symbol rate to a second symbol rate higher than said first rate; and
transmitting said data symbols and additional symbols at said second symbol rate to said communications facility. - A method for use in a communications system wherein data is transmitted through a communications facility, said method comprising the steps of
receiving a sequence of data symbols and additional symbols from said communications facility at a first symbol rate, each data symbol being representative of a plurality of digital signals and lying in a signal constellation including a plurality of data symbols; and
extracting said additional symbols from said sequence and for mapping each data symbol into its representative digital signal said extracted additional symbols not being used for any processing of the representative digital signals mapped from the data symbols. - A communication system comprising a transmitter and a receiver, said transmitter including
means responsive to digital signals for forming data symbols at a first symbol rate, each data symbol being representative of a plurality of digital signals and lying in a signal constellation including a plurality of data symbols;
means responsive to the formed data symbols for providing additional symbols so as to raise said first symbol rate to a second symbol rate higher than said first rate; and
means for transmitting said data symbols and additional symbols at said second symbol rate to said communications facility and
said receiver including
means for receiving a sequence of said data symbols and additional symbols from said communications facility at a third symbol rate; and
means for extracting said additional symbols from said sequence and for mapping each data symbol into its representative digital signal. - The system of claim 9 wherein said second and third symbol rates are equal or related by a rational multiple.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/891,500 US5521949A (en) | 1992-05-29 | 1992-05-29 | Synchronization scheme for digital communications systems transporting data at a customer-controlled rate |
US891500 | 1992-05-29 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0572168A2 true EP0572168A2 (en) | 1993-12-01 |
EP0572168A3 EP0572168A3 (en) | 1994-08-03 |
EP0572168B1 EP0572168B1 (en) | 2001-09-12 |
Family
ID=25398296
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93303903A Expired - Lifetime EP0572168B1 (en) | 1992-05-29 | 1993-05-20 | Method for matching symbol rates in a communications network |
Country Status (4)
Country | Link |
---|---|
US (1) | US5521949A (en) |
EP (1) | EP0572168B1 (en) |
JP (1) | JP3305424B2 (en) |
DE (1) | DE69330729T2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998044690A1 (en) * | 1997-03-27 | 1998-10-08 | Thomson Consumer Electronics, Inc. | Symbol timing recovery network for a carrierless amplitude phase (cap) signal |
FR2808361A1 (en) * | 2000-04-27 | 2001-11-02 | Canon Kk | Method and device for digital signal coding for transmission by modulation of at least one carrier, for use in protected telecommunication system |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5970088A (en) * | 1996-05-09 | 1999-10-19 | Texas Instruments Incorporated | Reverse channel next cancellation for MDSL modem pool |
US5790658A (en) * | 1996-10-28 | 1998-08-04 | Advanced Micro Devices, Inc. | High performance echo canceller for high speed modem |
US6246716B1 (en) * | 1997-01-31 | 2001-06-12 | Adtran, Inc. | Information communication system |
US6233287B1 (en) * | 1997-04-04 | 2001-05-15 | Motorola, Inc. | Method and apparatus for mixing signals |
US6212228B1 (en) * | 1997-09-10 | 2001-04-03 | Nortel Networks Limited | Apparatus for modulation and demodulating digital data |
US6144695A (en) * | 1997-12-23 | 2000-11-07 | At&T Corp. | Method and apparatus for reducing near-end crosstalk (NEXT) in discrete multi-tone modulator/demodulators |
DE69839814D1 (en) * | 1997-12-29 | 2008-09-11 | Motorola Inc | METHOD AND APPARATUS FOR SELECTING A CONSTELLATION POINT FOR EACH GROUP OF DATA BITS WHICH SHOULD BE TRANSMITTED BY AN ANALOG PCM MODEM |
US6658049B1 (en) * | 1999-01-12 | 2003-12-02 | Cisco Technology, Inc. | xDSL repeater system and method |
US6707868B1 (en) * | 1999-04-12 | 2004-03-16 | Intel Corporation | Apparatus for recovering timing of a digital signal for a transceiver |
CN100391122C (en) * | 1999-07-08 | 2008-05-28 | 三星电子株式会社 | Appts. and method for controlling demultiplexer and multiplexer used for rate machine in mobile communication system |
US7921290B2 (en) * | 2001-04-18 | 2011-04-05 | Ipass Inc. | Method and system for securely authenticating network access credentials for users |
US7469341B2 (en) * | 2001-04-18 | 2008-12-23 | Ipass Inc. | Method and system for associating a plurality of transaction data records generated in a service access system |
US20030065919A1 (en) * | 2001-04-18 | 2003-04-03 | Albert Roy David | Method and system for identifying a replay attack by an access device to a computer system |
US7349486B2 (en) * | 2001-07-19 | 2008-03-25 | Agere Systems Guardian Corporation | System and method for recognizing zero-amplitude symbols in a QAM signal and digital receiver incorporating the same |
US7406117B2 (en) * | 2002-03-21 | 2008-07-29 | Westell Technologies, Inc. | XDSL multi-hybrid modem with power spectral density shaping |
US8606885B2 (en) * | 2003-06-05 | 2013-12-10 | Ipass Inc. | Method and system of providing access point data associated with a network access point |
US7539862B2 (en) * | 2004-04-08 | 2009-05-26 | Ipass Inc. | Method and system for verifying and updating the configuration of an access device during authentication |
US8027279B2 (en) * | 2007-09-17 | 2011-09-27 | Lantiq Deutschland Gmbh | Echo cancellation |
JP4474532B2 (en) * | 2007-12-27 | 2010-06-09 | テクトロニクス・インターナショナル・セールス・ゲーエムベーハー | Signal generation system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3680051A (en) * | 1970-07-29 | 1972-07-25 | Honeywell Inf Systems | Apparatus for maintaining character synchronization in a data communication system |
GB1479313A (en) * | 1975-03-26 | 1977-07-13 | Marconi Co Ltd | Digital data rate converters |
EP0459058A2 (en) * | 1990-05-29 | 1991-12-04 | AT&T Corp. | Inband coding of secondary data |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3825899A (en) * | 1971-08-11 | 1974-07-23 | Communications Satellite Corp | Expansion/compression and elastic buffer combination |
GB1581521A (en) * | 1978-05-31 | 1980-12-17 | Digital Communications Corp | Tdma multiplexer-demultiplexer with multiple ports |
US4644537A (en) * | 1984-12-24 | 1987-02-17 | American Telephone And Telegraph Company | Inband coding of secondary data |
US4651320A (en) * | 1984-12-24 | 1987-03-17 | American Telephone And Telegraph Company | Inband coding of secondary data |
US4993046A (en) * | 1988-06-24 | 1991-02-12 | Nippon Telegraph And Telephone Corporation | Coded modulation communication system |
US4941154A (en) * | 1989-05-30 | 1990-07-10 | At&T Bell Laboratories | Trellis coding method and arrangement for fractional bit rates |
US5134633A (en) * | 1990-11-30 | 1992-07-28 | At&T Bell Laboratories | Digital communications synchronization scheme |
US5251236A (en) * | 1991-04-05 | 1993-10-05 | At&T Paradyne Corporation | Fractional rate modem with trellis |
US5173900A (en) * | 1991-05-17 | 1992-12-22 | General Instrument Corporation | Method and apparatus for communicating different categories of data in a single data stream |
-
1992
- 1992-05-29 US US07/891,500 patent/US5521949A/en not_active Expired - Lifetime
-
1993
- 1993-05-20 DE DE69330729T patent/DE69330729T2/en not_active Expired - Lifetime
- 1993-05-20 EP EP93303903A patent/EP0572168B1/en not_active Expired - Lifetime
- 1993-05-28 JP JP14837393A patent/JP3305424B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3680051A (en) * | 1970-07-29 | 1972-07-25 | Honeywell Inf Systems | Apparatus for maintaining character synchronization in a data communication system |
GB1479313A (en) * | 1975-03-26 | 1977-07-13 | Marconi Co Ltd | Digital data rate converters |
EP0459058A2 (en) * | 1990-05-29 | 1991-12-04 | AT&T Corp. | Inband coding of secondary data |
Non-Patent Citations (2)
Title |
---|
BELL SYSTEM TECHNICAL JOURNAL, vol.49, no.3, March 1970, NEW YORK, US pages 379 - 398 BUCHNER M. M., JR.: 'AN ASYMMETRIC ENCODING SCHEME FOR WORD STUFFING' * |
IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, vol.16, no.2, April 1968 pages 252 - 254 BUTMAN S.: 'SYNCHRONIZATION OF PCM CHANNELS BY THE METHOD OF WORD STUFFING' * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998044690A1 (en) * | 1997-03-27 | 1998-10-08 | Thomson Consumer Electronics, Inc. | Symbol timing recovery network for a carrierless amplitude phase (cap) signal |
FR2808361A1 (en) * | 2000-04-27 | 2001-11-02 | Canon Kk | Method and device for digital signal coding for transmission by modulation of at least one carrier, for use in protected telecommunication system |
Also Published As
Publication number | Publication date |
---|---|
JP3305424B2 (en) | 2002-07-22 |
DE69330729D1 (en) | 2001-10-18 |
JPH0637836A (en) | 1994-02-10 |
EP0572168B1 (en) | 2001-09-12 |
US5521949A (en) | 1996-05-28 |
EP0572168A3 (en) | 1994-08-03 |
DE69330729T2 (en) | 2002-07-11 |
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