EP0716447A3 - Metal layers formed as a composite of sub-layers and devices including same - Google Patents
Metal layers formed as a composite of sub-layers and devices including same Download PDFInfo
- Publication number
- EP0716447A3 EP0716447A3 EP95308537A EP95308537A EP0716447A3 EP 0716447 A3 EP0716447 A3 EP 0716447A3 EP 95308537 A EP95308537 A EP 95308537A EP 95308537 A EP95308537 A EP 95308537A EP 0716447 A3 EP0716447 A3 EP 0716447A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- composite
- sub
- devices including
- layers
- including same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000002131 composite material Substances 0.000 title 1
- 239000002184 metal Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/349,649 US5523259A (en) | 1994-12-05 | 1994-12-05 | Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer |
US349649 | 1994-12-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0716447A2 EP0716447A2 (en) | 1996-06-12 |
EP0716447A3 true EP0716447A3 (en) | 1997-01-08 |
Family
ID=23373361
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95308537A Withdrawn EP0716447A3 (en) | 1994-12-05 | 1995-11-28 | Metal layers formed as a composite of sub-layers and devices including same |
Country Status (4)
Country | Link |
---|---|
US (1) | US5523259A (en) |
EP (1) | EP0716447A3 (en) |
JP (1) | JP3707627B2 (en) |
KR (1) | KR960026265A (en) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3401843B2 (en) * | 1993-06-21 | 2003-04-28 | ソニー株式会社 | Method for forming multilayer wiring in semiconductor device |
US5580823A (en) * | 1994-12-15 | 1996-12-03 | Motorola, Inc. | Process for fabricating a collimated metal layer and contact structure in a semiconductor device |
JPH08176823A (en) * | 1994-12-26 | 1996-07-09 | Sony Corp | Formation of thin film of high melting point metal |
US5691571A (en) * | 1994-12-28 | 1997-11-25 | Nec Corporation | Semiconductor device having fine contact hole with high aspect ratio |
US5561083A (en) * | 1994-12-29 | 1996-10-01 | Lucent Technologies Inc. | Method of making multilayered Al-alloy structure for metal conductors |
US6285082B1 (en) * | 1995-01-03 | 2001-09-04 | International Business Machines Corporation | Soft metal conductor |
KR0161116B1 (en) * | 1995-01-06 | 1999-02-01 | 문정환 | Formation method of metal layer in semiconductor |
US5738917A (en) * | 1995-02-24 | 1998-04-14 | Advanced Micro Devices, Inc. | Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer |
KR100425655B1 (en) * | 1995-03-28 | 2004-06-26 | 텍사스 인스트루먼츠 인코포레이티드 | Diffusion Prevention Triple Layer and Manufacturing Method to Minimize Reaction Between Metallized Layers of Integrated Circuits |
EP0793268A3 (en) * | 1995-05-23 | 1999-03-03 | Texas Instruments Incorporated | Process for filling a cavity in a semiconductor device |
KR0179827B1 (en) * | 1995-05-27 | 1999-04-15 | 문정환 | Method of forming metal interconnector in semiconductor device |
US5962923A (en) * | 1995-08-07 | 1999-10-05 | Applied Materials, Inc. | Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches |
JPH09115829A (en) * | 1995-10-17 | 1997-05-02 | Nissan Motor Co Ltd | Semiconductor device with aluminium wiring part and method of manufacturing |
US5918149A (en) * | 1996-02-16 | 1999-06-29 | Advanced Micro Devices, Inc. | Deposition of a conductor in a via hole or trench |
US6291336B1 (en) * | 1996-05-20 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | AlCu metal deposition for robust Rc via performance |
US5856236A (en) * | 1996-06-14 | 1999-01-05 | Micron Technology, Inc. | Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer |
KR100223332B1 (en) * | 1996-06-17 | 1999-10-15 | 김영환 | Forming method for metalization of semiconductor device |
US6309971B1 (en) | 1996-08-01 | 2001-10-30 | Cypress Semiconductor Corporation | Hot metallization process |
GB9619461D0 (en) * | 1996-09-18 | 1996-10-30 | Electrotech Ltd | Method of processing a workpiece |
US5926736A (en) | 1996-10-30 | 1999-07-20 | Stmicroelectronics, Inc. | Low temperature aluminum reflow for multilevel metallization |
TW417178B (en) * | 1996-12-12 | 2001-01-01 | Asahi Chemical Ind | Method for making semiconductor device |
US6110828A (en) * | 1996-12-30 | 2000-08-29 | Applied Materials, Inc. | In-situ capped aluminum plug (CAP) process using selective CVD AL for integrated plug/interconnect metallization |
US6139905A (en) * | 1997-04-11 | 2000-10-31 | Applied Materials, Inc. | Integrated CVD/PVD Al planarization using ultra-thin nucleation layers |
US5943601A (en) * | 1997-04-30 | 1999-08-24 | International Business Machines Corporation | Process for fabricating a metallization structure |
JP3085247B2 (en) * | 1997-07-07 | 2000-09-04 | 日本電気株式会社 | Metal thin film forming method |
US5882399A (en) * | 1997-08-23 | 1999-03-16 | Applied Materials, Inc. | Method of forming a barrier layer which enables a consistently highly oriented crystalline structure in a metallic interconnect |
US6365514B1 (en) * | 1997-12-23 | 2002-04-02 | Intel Corporation | Two chamber metal reflow process |
JPH11186190A (en) * | 1997-12-25 | 1999-07-09 | Sharp Corp | Fabrication of semiconductor device |
US5981382A (en) * | 1998-03-13 | 1999-11-09 | Texas Instruments Incorporated | PVD deposition process for CVD aluminum liner processing |
US6638856B1 (en) * | 1998-09-11 | 2003-10-28 | Cypress Semiconductor Corporation | Method of depositing metal onto a substrate |
US6187670B1 (en) * | 1998-12-02 | 2001-02-13 | Advanced Micro Devices, Inc. | Multi-stage method for forming optimized semiconductor seed layers |
TW409356B (en) * | 1999-03-11 | 2000-10-21 | United Microelectronics Corp | Manufacture method of inner connects |
GB2349392B (en) * | 1999-04-20 | 2003-10-22 | Trikon Holdings Ltd | A method of depositing a layer |
JP2000315687A (en) * | 1999-04-30 | 2000-11-14 | Mitsubishi Electric Corp | Semiconductor device and manufacture of the same |
JP3358587B2 (en) * | 1999-05-26 | 2002-12-24 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US6627542B1 (en) * | 1999-07-12 | 2003-09-30 | Applied Materials, Inc. | Continuous, non-agglomerated adhesion of a seed layer to a barrier layer |
KR100326253B1 (en) * | 1999-12-28 | 2002-03-08 | 박종섭 | Method for forming capacitor in semiconductor device |
JP3480416B2 (en) * | 2000-03-27 | 2003-12-22 | セイコーエプソン株式会社 | Semiconductor device |
JP3449333B2 (en) * | 2000-03-27 | 2003-09-22 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
AU2001247109A1 (en) * | 2000-04-27 | 2001-11-12 | Nutool, Inc. | Conductive structure for use in multi-level metallization and process |
DE10053915C2 (en) * | 2000-10-31 | 2002-11-14 | Infineon Technologies Ag | Manufacturing process for an integrated circuit |
US6943105B2 (en) * | 2002-01-18 | 2005-09-13 | International Business Machines Corporation | Soft metal conductor and method of making |
KR100455380B1 (en) * | 2002-02-27 | 2004-11-06 | 삼성전자주식회사 | Semiconductor device having multilevel interconnections and method for manufacturing the same |
KR100555514B1 (en) * | 2003-08-22 | 2006-03-03 | 삼성전자주식회사 | Semiconductor memory device having tungsten line with low resistance and method for manufacturing the same |
JP2010165989A (en) * | 2009-01-19 | 2010-07-29 | Elpida Memory Inc | Method of manufacturing semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5108951A (en) * | 1990-11-05 | 1992-04-28 | Sgs-Thomson Microelectronics, Inc. | Method for forming a metal contact |
EP0488264A2 (en) * | 1990-11-30 | 1992-06-03 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device with improved electromigration resistance |
US5356836A (en) * | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
US5371042A (en) * | 1992-06-16 | 1994-12-06 | Applied Materials, Inc. | Method of filling contacts in semiconductor devices |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4631804A (en) * | 1984-12-10 | 1986-12-30 | At&T Bell Laboratories | Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer |
US4742020A (en) * | 1985-02-01 | 1988-05-03 | American Telephone And Telegraph Company, At&T Bell Laboratories | Multilayering process for stress accommodation in deposited polysilicon |
KR920005701B1 (en) * | 1989-07-20 | 1992-07-13 | 현대전자산업 주식회사 | Metal barrier layer for semiconductor integrated circuit |
US4970176A (en) * | 1989-09-29 | 1990-11-13 | Motorola, Inc. | Multiple step metallization process |
JP2811131B2 (en) * | 1991-04-26 | 1998-10-15 | 三菱電機株式会社 | Wiring connection structure of semiconductor device and method of manufacturing the same |
US5147820A (en) * | 1991-08-26 | 1992-09-15 | At&T Bell Laboratories | Silicide formation on polysilicon |
KR970009976B1 (en) * | 1991-08-26 | 1997-06-19 | 아메리칸 텔리폰 앤드 텔레그라프 캄파니 | Improved dielectrics formed on a deposited semiconductor |
US5300307A (en) * | 1992-09-14 | 1994-04-05 | The United States Of America As Represented By The United States Department Of Energy | Microstructure control of Al-Cu films for improved electromigration resistance |
EP0594300B1 (en) * | 1992-09-22 | 1998-07-29 | STMicroelectronics, Inc. | Method for forming a metal contact |
JPH06268083A (en) * | 1993-03-11 | 1994-09-22 | Sony Corp | Wiring of semiconductor device |
-
1994
- 1994-12-05 US US08/349,649 patent/US5523259A/en not_active Expired - Lifetime
-
1995
- 1995-11-28 EP EP95308537A patent/EP0716447A3/en not_active Withdrawn
- 1995-12-04 JP JP33769495A patent/JP3707627B2/en not_active Expired - Lifetime
- 1995-12-05 KR KR1019950046636A patent/KR960026265A/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5108951A (en) * | 1990-11-05 | 1992-04-28 | Sgs-Thomson Microelectronics, Inc. | Method for forming a metal contact |
EP0485130A2 (en) * | 1990-11-05 | 1992-05-13 | STMicroelectronics, Inc. | Method for forming a metal contact |
EP0488264A2 (en) * | 1990-11-30 | 1992-06-03 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device with improved electromigration resistance |
US5371042A (en) * | 1992-06-16 | 1994-12-06 | Applied Materials, Inc. | Method of filling contacts in semiconductor devices |
US5356836A (en) * | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
Non-Patent Citations (2)
Title |
---|
HIDEKI SHIBATA ET AL: "THE EFFECTS OF A1(111) CRYSTAL ORIENTATION ON ELECTROMIGRATION IN HALF-MICRON LAYERED A1 INTERCONNECTS", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 32, no. 10, PART 01, 1 October 1993 (1993-10-01), pages 4479 - 4484, XP000487511 * |
JAWARANI D ET AL: "INTERMETALLIC COMPOUND FORMATION IN TI/AL ALLOY THIN FILM COUPLES AND ITS ROLE IN ELECTROMIGRATION LIFETIME", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 141, no. 1, 1 January 1994 (1994-01-01), pages 302 - 306, XP000445663 * |
Also Published As
Publication number | Publication date |
---|---|
KR960026265A (en) | 1996-07-22 |
US5523259A (en) | 1996-06-04 |
EP0716447A2 (en) | 1996-06-12 |
JP3707627B2 (en) | 2005-10-19 |
JPH08255836A (en) | 1996-10-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB IT |
|
17P | Request for examination filed |
Effective date: 19970625 |
|
17Q | First examination report despatched |
Effective date: 19981008 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Withdrawal date: 20020129 |