EP0757372A1

EP0757372A1 - Field emission display fabrication method

Info

Publication number: EP0757372A1
Application number: EP96302725A
Authority: EP
Inventors: Guy Dubois
Original assignee: SGS Thomson Microelectronics Inc
Current assignee: STMicroelectronics lnc USA
Priority date: 1995-07-31
Filing date: 1996-04-18
Publication date: 1997-02-05
Also published as: JPH09106774A

Abstract

A process for fabricating vacuum microelectronic devices (especially field-emission displays) using a maskless self-aligned dense patterning step to define the emitter locations. This maskless patterning step is performed by applying charged particles to a pattern-transfer layer. Coulombic repulsion provides some self-regulating control of spacing, to approximate uniform density. Once the particles have thus been deposited, they can be used as the mask for an etching technique which will form the pointed cathode structures used for field emission displays. Thus, the present invention provides maskless patterning of one key step, and a corresponding reduction in cost.

Description

The present application relates to vacuum microelectronic devices, and more particularly to field emission displays.
The present application discloses an improvement in fabricating Field Emission displays. Before the describing the claimed improvement, the technical context in the art of Field Emission displays (especially as developed by Micron Display Technologies) will be reviewed.
Vacuum tube technology, which was the dominant technology for three-terminal gain devices from 1920 to about 1960, was almost entirely replaced by solid-state technology during the 1960s and 1970s. (Transistors did not begin to achieve real commercial impact until the late 1950s, although they were invented much earlier. Tubes survived in high-power-high-frequency and other specialty applications, but these applications were a relatively small dollar fraction of the market for semiconductor devices.)
However, since the 1980s there has been an upsurge of interest in vacuum microelectronic devices. These devices use microelectronic fabrication techniques to fabricate a cathode+grid structure which provided pointed microscopic emitter structures self-aligned to a thin film metallic grid. Thus, such structures provide two elements of a cold cathode triode with a precise and very small cathode-to-grid spacing. Since the cutoff frequency of any triode is limited by the cathode-to-grid spacing, these devices were immediately studied for their possible application to microwave frequencies, but it has since become apparent that such devices are also very attractive for display applications.
Substantial progress has been made in this technology, and many of the developments have been conveniently reported in the IEEE International Vacuum Microelectronics Conferences from 1988 on. (The proceedings of all of these conferences are hereby incorporated by reference.)
A particularly attractive application of vacuum microelectronics is for display fabrication. Various vacuum display technologies have long been known, but the adaptation of vacuum microelectronic technology to displays has produced a very active and promising field of technology, known as "Field Emission Displays".
Flat panel displays such as Active Matrix Liquid Crystal Displays (AMLCD), which have a greatly reduced bulk and weight relative to the venerable CRT display, have provided a means of employing displays in devices, locations and applications never before possible, such as laptop computers and portable hand-held color television sets. Clearly AMLCD technology is the best high quality portable display technology in production; but AMLCDs still suffer from significant limitations in the area of cost, power consumption, angle of view, smearing of fast moving video images, temperature range of operation, ad the environmental concerns of employing mercury vapor in the AMLCD's backlight.
Field Emission Displays (FEDs) offer the possibility of circumventing the limitations of AMLCDs, particularly in the area of small, high-resolution displays (e.g. for use in camcorder viewfinders, HMDs, and virtual reality headware). The display has characteristics which make it superior to the present LCDs which dominate the small color display market. The history of this display development, its advantages, and the display characteristics are discussed here. In addition, as FEDs move from prototypes into production, it becomes necessary to develop new technologies which enable production-level testing of these devices.
Typical camcorder viewfinders use displays that range from 0.55" to 0.7 in diagonal. The color displays, which are entirely AMLCDs, generally have from 96,000 to 180,000 dots, or 32,000 to 60,000 full-color pixels. Commercial viewfinder displays usually emit around 15 ft-L. At 15 ft-L the typical 0.55" black and white CRT viewfinder draws around 0.9 W. The 0.7" AMLCDs, with backlight, draw 0.5 W. By contrast, it has been demonstrated that a FED display with 100,800 dots, or 33,600 full-color pixels, can operate with a power of only about 0.1 W. This is a major advantage in camcorders and HMDs, where power consumption can be crucial to battery lifetime. In addition, AMLCDs do not respond fast enough in some video applications. A particular example is in the panning of a camcorder during live imaging. The slow response of the LCD causes a "smearing" effect in the video image. The FED does not have this problem.
The well known concept of an emissive flat panel display operates on the principles of cathodoluminescent phosphors excited by cold cathode field emission electrons as shown in Figures 1 and 2. (Figure 1 shows a sectional view, and Figure 2 shows a perspective view.) A faceplate having a cathodoluminescent phosphor coating similar to that of a cathode ray tube receives patterned electron bombardment which can be seen by a viewer. The faceplate is separated from the baseplate by a vacuum gap, and outside atmospheric pressure is prevented from collapsing the two plates together by physical standoffs between them, often referred to as spacers. Arrays of electron emission sites (emitters) are typically sharp cones that produce electron emission in the presence of an intense electric field. In the case of Figure 1, and most field emission displays, a positive voltage is applied to an extraction grid relative to the sharp emitters to provide the intense electric field required for generating cold cathode electron emission.
The Fowler-Nordheim equation is generally considered to accurately describe the emission process of Figure 1 when a field is applied to the emitter by generating a voltage differential between the extraction grid and the emitter tip. The Fowler-Nordheim equation is thoroughly discussed in the literature, and one useful explanation of it as directly applied to vacuum microelectronics can be found in Spindt et al., "Physical Properties of Thin Film Field Emission Cathodes with Molybdenum Cones," 47 J. APPLIED PHYSICS 5248 (1976), which is hereby incorporated by reference.
The concept of a video capable color FED display was first taught by Crost et al. in U.S patent 3,500,102. Following the work of Crost et al., recent developmental efforts have produced the world's first two color video FED displays. The work of LET/PIXEL in France has demonstrated color sequential FED prototypes, and the work of Micron Display has demonstrated spatial color FED prototypes in the United States.
The baseplate of a field emission display includes arrays of emission sites, and connections for addressing and activating the generation of electron beams from those sites. Many techniques are available for creating the emission from arrays, addressing the emission arrays, and activating the emission sites. Furthermore, a technique must be employed to achieve variations in display brightness (gray scales) when the sites are activated.
Several approaches are available including variation of the electron charge delivered to the phosphor by each emission array in each frame update of the image.
Varying the charge which is delivered to the phosphor in a given frame from an emission array will vary the light output of the pixel associated with it. Increasing the total electron charge delivered to the phosphor of an individual pixel within a frame results in increased brightness of that pixel. In many cases the brightness charge will be nearly proportional to the increase in the delivered charge. Cathodoluminescent phosphors have a property known as persistence, i.e. the phosphors continue to emit photons even after electron bombardment excitation has ceased. The duration of the persistence is a materials property which can be varied and controlled by the selection and synthesis of the phosphor materials used. The persistence of phosphors provides for a high degree of latitude in how charge variation may be implemented during frame updates of a display, and allows for production of a bright, high quality image without requiring pixel activation throughout the frame time, as is required by an AMLCD display. (Frame time is the duration between refreshes of a display's image, and is generally required to be no more than 1/60 second to avoid flicker of fast random image movements as perceived by a human viewer.)
Two techniques for varying the charge delivered by an emission array in a given frame are to vary either the time period within the frame that the site is activated or alternatively to vary the emission current produced during activation.
One means of addressing field emission arrays for use in video displays is taught in the Crost et al. patent cited above. In this technique, emitters are electrically connected in rows, and the extraction grids are connected in parallel columns which are orthogonal to the emitter rows. The emitter array associated with each pixel is uniquely defined by the intersection point of a specific emitter row and a specific extraction grid column. Electrically addressing a row while simultaneously addressing a column activates any specific pixel in a frame. (The term "pixel" is used in various ways in the display industry, especially when discussing spatial color displays using three light emitting dots, one each of red, green and blue for producing a combing full color display element. In the present application, the term "pixel" is used to refer to one discrete light emitting element or dot.)
The emission structures of the baseplate have been a primary subject of investigations and development in the art of field-emission displays. In the late 1960s, prior to dramatic advances in a wide array of micro-machining and thin film processing techniques driven by the semiconductor and flat panel industries, a new and enabling procedure was developed by Spindt and S.R.I. for the fabrication of gated emitters, as described in the Spindt et al. papers referenced above.
The technique employs high resolution lithography and etching to create openings in a metal dielectric sandwich which are generally on the order of about one micron in diameter with the dielectric layer being of nearly equal thickness to the diameter. A subsequent directional molylbdenum deposition of about one micron in thickness is then employed at an angle to the openings in the dielectric with thin film vacuum evaporation processing equipment. As the thickness of the deposition increases, the openings in the original metal-dielectric sandwich are reduced and finally closed off. This results in the formation of a pointed molybdenum cone which is self aligned to the openings in the original metal-dielectric sandwich. The molybdenum atop the first metal pinches the openings shut, and is selectively removed with an electrochemical etchback (thus providing emitters with self aligned extraction grids). This technique is commonly referred to as the "Spindt Technique" and the resultant structures as "Spindt emitters."
The classic Spindt technique has provided a vehicle for advancing FED developments for many years and is still used today. A number of alternative techniques have been investigated by Henry Gray and others for producing self aligned emitter processes involving plasma etch back planarization, lift off processing, fiber growth, etc.
Alignment of the extraction grid to the emission site is a key factor. If alignment is not achieved, emitted electrons which would ordinarily be accelerated towards and collected by the faceplate would be collected by the grid electrode. Collection of a large amount of emission current by the nearby grid electrode would result in power inefficiency, image degradation, and an increase in the probability of failures.
Another approach for forming self-aligned extraction grids utilizes the combination of deposition, polishing and wet etching. In this technique, a silicon dioxide dielectric layer is deposited over the emitter tips, with a thickness less than the emitter height. A conductive layer for forming the extraction grid is then deposited over the silicon dioxide layer, with a thickness such that the sum of the conductive layers thickness with the previously deposited dielectric thickness was greater than the tip height. The surface of the deposited conductive material is then removed by a wet polishing process with an aqueous based slurry and a conformal polishing pad. During polishing, the rate of material removal atop the emitter tips is much faster than that of material deposited to the sides of the emitter tips. The difference in material removal rates can be attributed to the local pressure and contact difference between the polishing pad with the film stack on top of the emitter and that of the film stack on the topographical lower surface surrounding the emitters. When the conductive material above the emitters has been polished to nearly the same height as the surrounding local topology the removal reduces dramatically. This self limiting effect of the material removal during processing provides the process margin required to scale to large area panels. Without this self limiting effect, the uniformity of a bulk removal process would be difficult to manage. At this point in the process, the self-aligned extraction grid is formed relative to the emitters. The tips remain buried and surrounded in silicon dioxide until a wet chemical etch is employed to remove the silicon dioxide surrounding the tip. The resulting void exposes the tip so that it will be capable of emitting electrons into the vacuum cavity of an assembled FED.
This polishing process has the advantages of: self alignment; wide process window; definition of grid diameter by deposition rather than lithography; avoids the need for thick angularly evaporated molybdenuml and capability of being scaled up for use with large area tip formation processes. A further advantage of the polishing process is the ability to incorporate the use of a flowable dielectric between the silicon dioxide and conductive grid materials. The combination results in the fabrication of structures with a large standoff distance between the base of the emitters and the extraction grid for reducing parasitic capacitance. The combination simultaneously results in a small grid diameter which reduces the applied voltage required for emission. Finally, both of the dimensions are determined by a deposition thickness which enables large area dimensional control.
Emitters across the same substrate and even within the same array with the same applied voltage differential to their respective extraction grids can produce significantly different emission current as a result of small variations in tip diameter and surface morphology because of the effects to the electrical field imposed by the extraction grid. Small variations in the final atomic make-up and structure of the outer most surface can also generate significant differences in emission current as a result of their influence on the work function of the surface. These effects are easily explained in reviewing the effect of field strength and work function in the Fowler-Nordheim theory of cold cathode electron emission.
Variations in emission current between tips result in a corresponding effect on image quality. The variation at the image is partly reduced by employing large numbers of emitters operating electrically in parallel at each pixel site. Further improvements of imperfectly uniform emitters can be achieved electrically, by operating the emitters in the display with a grid voltage capable of producing higher than the desired electron emission current, while limiting the electron current supplied to the emitters. A very wide selection of passive and active current limiting approaches are shown in the literature. This form of regulated emitter operation is also beneficial in preventing very high performance emitters in an array from generating very large currents and being physically destroyed. When high performance emitters in an array are allowed to emit high enough currents to cause thermal ablation or other dramatic deterioration, the charged and neutral particles from them can contribute to electrical arcs which further damage display components or cause shorts.
The value of current limiting during the operation of field emitters has been recognized for some time. One straightforward approach for achieving current limiting of field emitters is the use of series electrical resistance to both individual emitters and arrays of emitters. One approach (developed by NASA and described in patent 3,671,798 of Wayne L. Lees entitled "Method and Apparatus Limiting Field Emission Current") employs microscopic discrete resistors integrated with each emitter tip.
Another resistance based current limiting approach was pioneered at the Georgia Institute of Technology and is described in a thesis by Dr. Kon Jiun Lee, which is available through the Georgia Institute of Technology library and which is hereby incorporated by reference. (K. Lee, "Current Limiting of Field Emitter Array Cathodes," Ph.D. thesis in Materials Engineering, Georgia Institute of Technology, August 1986, U.M. order no.86-28,359.) One of the techniques taught in that thesis is the implementation of a deposited resistive layer comprising silicon for limiting current through field emission cathodes.
The faceplate of a field emission display operates on the principle of cathodoluminescent emission of light by the same qualitative principles of physics as that of a conventional CRT. As with a CRT, a color image can be obtained using a color sequential approach (sometimes referred to as frame sequential or temporal integration), or with a spatial color approach (sometimes referred to as spatial integration). See generally the paper by David L. Post at 2210 PROC. SPIE 2 (1994); and Tannas, "Color in electronic displays," 45 PHYSICS TODAY no. 12, Dec. 1992, p. 52; both of which are hereby incorporated by reference.
Nearly all commercially successful displays today employ spatial integration to provide a color image to the view including those employed in home television sets, desk top computer monitors, laptop computers and color camcorder viewfinders. A common way to employ spatial integration is to provide red, green, and blue pixels which are addressed in the form of R/G/B triads. The intensities of the color dots within each triad are adjusted relative to one another to produce a range of colors within the triangular boundary formed by the CIE color coordinates of the R, G, and B dots. The human eye is then relied upon for integrating the spatially separated R/G/B dots into a perceived color image.
Spatial color displays generally employ a black region separating the red, green, and blue patterned dots. One conventional major advantage to the black region, referred to as the black matrix, is to improve the contrast of a display in ambient light. Some of the ambient light that falls on the face of a display is reflected back toward the viewer, mixed with the imaged color light pattern produced by the display. The reflected ambient light reduces the contrast performance of the display and tends to ''wash out' the image. When a black matrix is employed on the faceplate it will absorb ambient light falling upon it, thereby improving the contrast performance of the display.
As shown in Figures 1 and 2, field emission displays employ physical support spacers between the faceplate and the baseplate to prevent collapse from the forces of atmospheric pressure. In the case of moderate and large FED displays, the spacers must be distributed across the viewable and active region of the display sot that thin light weight faceplates and baseplates can be used. The black matrix regions of the display provide an excellent location in which to place support spacers so that they are invisible to the user.
Although the qualitative physics of an FED faceplate are very similar to those of CRT faceplates, there are significant quantitative and engineering differences. FEDs are less tolerant to particle shedding from the faceplate than CRTs, and so excellent and repeatable adhesion and faceplate integrity are required. The cathodes of the field emission display are in very close proximity to the faceplate and are sensitive to any electronegative chemicals arriving on the cold cathode emitter surfaces which could absorb and increase the value of the work function. Because of the sensitivity just mentioned, some phosphor materials which are suitable for use in CRTs, most notably sulfides of cadmium or zinc, are not recommended for use in FEDs. In fact, the release of sulfur and sulfur compounds from sulfide phosphors under electron bombardment has been shown to poison even the sub red emitter wires in vacuum florescent displays.
Typically, FEDs are operated at anode voltages well below those of conventional CRTs. Spacer technology will be discussed later in the paper and is a major factor determining the maximum allowable anode voltage. The maximum voltage between two nodes in a vacuum which can be maintained across a solid surface is generally lower than that which can be maintained across a vacuum gap of equal distance in high vacuum devices. The material properties of the surface, distance along the surface, and changes in the orientation of the surface relative to a straight line between the two voltage nodes determine the voltage at which flash over will occur. Another factor which tends to limit the anode operating voltage is the use of simple proximity focus single grid structures. Increasing the space between the faceplate and the baseplate results in greater lateral beam spread. Increasing anode voltage helps reduce the spot size of the beams by accelerating them more rapidly, however, it less than compensates for increased spreading of the beams from increased spacing.
The processes used to pattern phosphors on the faceplate bind the phosphors to the faceplate and prepare and treat the phosphor materials prior to application to the faceplate are critical in the fabrication of FEDs. With the important exceptions of storage tube CRTs, which have anode operating voltages of several hundred volts, and vacuum fluorescent displays, which operate well below that, conventional CRTs operate at anode voltages well above FEDs. The phosphor material treatments, and screening and binding of the phosphors to the faceplate result in the formation of thin, non-luminescent coatings on the phosphor referred to as the dead layer. In high voltage CRTs a significant amount of dead layer can be tolerated as the electrons are accelerated to high energies and can easily pass through the dead layer and excite the phosphors within them. Because FEDs employ lower anode voltages, phosphor material screening and binding processes have to be optimized and tightly controlled to minimize the dead layer and allow for effective excitation of the phosphor.
In the course of synthesizing and handling phosphor materials, the crystal lattices along the surface of the phosphor particles are often damaged or degraded. The effect of the damage reduces the light producing efficiency of the phosphor surface. In the case of most CRTs this is not a significant problem because once again high anode voltages can accelerate electrons past the damaged surface. Significant advances in material science, materials handling, and processing have occurred since the last major industrial push of phosphor synthesis which was driven by the development of color television. These advances are employed in the production of quality phosphors optimized for use in FEDs.
The materials used in the construction of spacers for FEDs cannot outgas and contaminate the deployed sensitive high vacuum environment. The spacer materials must also be designed to withstand some stray electron bombardment without suffering from flash over, degradation, or secondary electron generation.
Spacer architectures employing a series of individual posts provide the greatest protection against local pressure build up which can result in destructive arcing damage by providing an unencumbered interstices between the faceplate and baseplate. This type of structure, however, dictates the use of spacer materials with high compressive strengths.
Various approaches appear in the literature as potential spacer solutions. Patterned deposited polyamide layers have been shown by S.R.I. to be somewhat successful. Challenges in the area of vacuum compatibility and carbonization from reduction by stray electrons may need to be met with the polyamide approach. The use of glass spheres has been discussed in the industry and has been employed in prototype displays produced by LETI. (See the paper by Meyer in the PROC. INTERNATIONAL VACUUM MICROELECTRONICS CONFERENCE 6 (1991).) Glass spheres are a simple low cost way of meeting the major material requirements for FED spacers. Another advantage of spacers with curved sides is that because it does not provide a straight line path between the faceplate and the baseplate it will yield a higher voltage stand-off than an equivalent line of site path across the same material. Low resolution FEDs can readily accommodate spheres as spacer supports because of the relatively large spacing between phosphor patterns in which to hide them.
High resolution FEDs will provide very little distance between phosphor patterns to accommodate spacers. This requirement can be met with small diameter spheres. These smaller spacers provide a challenge in providing a practical working distance between the faceplate and the baseplate. Phosphor powders are often times on the order of seven microns in diameter and are typically deposited at a minimum of two particles deep. Smaller particle sizes are readily achievable, but generally result in lower phosphor efficiencies. A 25 micron diameter sphere could be placed with some alignment tolerance between phosphor patterns on many high resolution displays and provide a surface leakage path of 39 microns. The resultant narrow gap between the faceplate and baseplate produced by the use of these small diameter spheres generates a challenge in the area of display evacuation, voltage stand-off, and relative tolerance to the size of the phosphor particles.
While the light output from many phosphors is power dependent and increased current can compensate for reduced anode voltage, most phosphor lifetimes are largely determined by the total accumulated charge delivered per unit area through the life of the display. This coulumbic aging of the phosphor can be reduced through faceplate and phosphor materials considerations, but can most dramatically be impacted by increasing the standoff capability of the spacers.
The following publications, all of which are hereby incorporated by reference, show the state of the art in field emission displays, as well as some of the development of that technology and some possible alternatives: Curtin, "The field emission display: a new fiat panel technology," CONFERENCE RECORD OF THE 1991 INTERNATIONAL DISPLAY RESEARCH CONFERENCE 12 (1991); Derbyshire, "Beyond AMLCDs: field emission displays?" 37 SOLID STATE TECHNOLOGY no.11 p.55 (Nov. 1994); Ghis et al., "Sealed vacuum devices: fluorescent microtip displays," 38 IEEE TRANS'NS ELECTRON DEVICES 2320 (1991); Hunt et al., "Structure and Electrical Characteristics of Silicon Field-Emission Microelectronic Devices", 38 IEEE TRANS'NS ELECTRON DEVICES 2309 (1991); Kesling and Hunt, "Beam focusing for field-emission flat-panel displays," 42 IEEE TRANS'NS ELECTRON DEVICES 340 (1995); Labrunie and Meyer, "Novel type of emissive flat panel display: the matrixed cold-cathode microtip fluorescent display," 8 DISPLAYS, TECHNOLOGY AND APPLICATIONS no.1 37 (1987); Levine, "Statistical analysis of field emitter emissivity: application to flat displays," 13 J. VACUUM SCIENCE & TECHNOLOGY B 553 (1995); Marcus et al., "Formation of Silicon Tips with 1 nm Radius", 56 APPL. PHYSICS LETTER (1990); McGruer et al., "Oxidation-Sharpened Gated Field Emitter Array Process", 38 IEEE TRANS'NS ELECTRON DEVICES 2389 (1991); Ravi et al., "Oxidation Sharpening of Silicon Tips", 9 J. VAC. SCI. TECHNOL. B 2733 (1991); Spindt et al., "Field-emitter arrays to vacuum fluorescent display," 36 IEEE TRANS'NS ELECTRON DEVICES 225 (1989); Spindt et al., "Field emitter arrays applied to a vacuum fluorescent display," in 49 JOURNAL DE PHYSIQUE COLLOQUE C-6 153 (1988); Trujillo et al., "Fabrication of Silicon Field Emission Points for Vacuum Microelectronics by Wet Chemical Etching", 6 SEMICOND. SCI. TECHNOL. 223 (1991); Urayama et al., "Fabrication of Cone-Like field Emitters", EXTENDED ABSTRACTS of the 53rd Autumn Meeting of the Japan Society of Applied Physics, No. 2, 19 a-ZM-6, p.553 (1992); Vaudaine and Meyer, "'Microtips' fluorescent display," 1991 IEDM TECHNICAL DIGEST 197; Yokoo et al., "Active control of the emission current of field emitter arrays," 13 J. VACUUM SCIENCE & TECHNOLOGY B 491 (1995).
Additional background, and additional detail regarding fabrication techniques, may be found in the following patents and applications, all of which are hereby incorporated by reference: 3,665,241 of Spindt et al.; 3,755,704 of Spindt et al.; 3,812,559 of Spindt et al.; 3,843,427 of Esdonk et al.; 3,875,442 of Wasa et al.; 3,921,022 of Levine; 3,953,756 of Monfroy et al.; 3,970,887 of Smith et al.; 3,998,678 of Fukase et al.; 4,006,383 of Luo et al.; 4,008,412 of Yuito et al.,; 4,042,854 of Luo et al.; 4,091,305 of Poley et al.; 4,114,070 of Asars; 4,168,213 of Hoeberechts; 4,183,125 of Meyer et al.; 4,193,226 of Gill, Jr. et al.; 4,196,041 of Baghdadi et al.; 4,310,380 of Flamm et al.; 4,372,033 of Chiao; 4,419,811 of Rice; 4,422,731 of Droguet et al.; 4,451,759 of Heynisch et al.; 4,498,952 of Christensen; 4,513,308 of Greene et al.,; 4,639,288 of Price et al.; 4,666,553 of Blumenfeld et al.; 4,670,097 of Abdalla et al.; 4,671,851 of Beyer et al.; 4,741,799 of Chen et al.; 4,746,629 of Hanagassaki; 4,857,478 of Niwano et al.; 4,859,063 of Fay et al.; 4,874,981 of Spindt; 4,923,421 of Brodie et al.; 4,943,343 of Bardai et al.; 4,950,569 of May; 4,964,946 of Gray et al.; 4,968,382 of Jacobson et al.; 4,968,585 of Albrecht et al.; 4,983,878 of Lee et al.; 4,986,876 of Zeto et al.; 4,986,877 of Tachi et al.; 4,988,637 of Dhong et al.; 4,997,780 of Szluk et al.; 5,036,015 of Sandhu et al.; 5,051,379 of Bayer et al.; 5,055,158 of Gallagher et al.; 5,063,323 of Longo et al.; 5,064,396 of Spindt et al.; 5,066,358 of Quate et al.; 5,070,282 of Epsztein et al.; 5,081,421 of Miller et al.; 5,082,524 of Cathey; 5,083,958 of Longo et al.; 5,094,712 of Becker et al.; 5,100,355 of Marcus et al.; 5,104,517 of Scott; 5,143,820 of Kotecha et al.; 5,151,061; 5,186,670 of Doan et al.; 5,194,780 of Meyer; 5,199,917 of MacDonald et al.; 5,201,992 of Marcus et al.; 5,205,770 of Lowrey et al.; 5,217,401 of Watanabe et al.; 5,229,331 of Doan et al.; 5,232,549 of Cathey et al.; 5,232,549 of Cathey et al.; 5,246,468 of Takahashi et al.; 5,259,799 of Doan et al.; 5,266,530 of Bagley et al.; 5,302,239; 5,329,207 of Cathey et al.; 5,342,477 of Cathey; 5,358,908; 5,372,901; 5,372,973; 5,374,868; EPC laid-open app'n 416625 (3/1991); GB laid-open app'n 2209432 (5/1989); JP 56-160740 (12/1981); JP 60-49626 (3/1985); JP 1-220330 (9/1989); JP 2-165540 (6/1990); JP 2-260412 (10/1990); JP 3-144453 (6/1991); JP 3-179630 (8/1991).
A key innovative point is that an unpatterned self-aligned dense pattern for field-emission devices (especially field-emission displays), is provided by applying charged particles to a pattern-transfer layer. Coulombic repulsion provides some self-regulating control of spacing, to get some approximation to uniform density. Once the particles have thus been deposited, they can be used as the mask for an etching technique which will form the pointed cathode structures used for field emission displays. Thus, the present invention provides maskless patterning of one key step, and a corresponding reduction in cost.
In a vacuum microelectronic FED display, each individual cathode operates efficiently, but contributes only a very small increment of current. It is therefore desirable to pack the cathodes very tightly (consistent with fabrication requirements, and with the spacing required to avoid lateral breakdown), e.g. to a pitch on the order of microns. However, all or most of the other patterning steps require merely geometries comparable to the pixel pitch, e.g. with geometries on the order of hundreds of microns.
Thus the present invention permits use of VLSI processing techniques for fabrication of the microstructures, while minimizing the use of expensive VLSI lithographic procedures.
By using charged particles, coulombic repulsion provides self-regulating control of spacing. Coulombic repulsion also reduces the likelihood of particles gluing together to form agglomerates (which would disrupt the process, since the size of the tips is regulated by the size of the balls).
Note that various low-cost mechanisms for depositing charged particles are used in xerographic copies, and in the way the painting particles (powder) are used in the so called "electrostatic painting" processes now widely used for painting frames, cars, etc.
The deposited particles can be used directly as a mask, or may be used as a counter mask for pattern transfer into a photoresist layer.
The surface onto which the particles are deposited may not itself be conductive, but the electrostatic potential can be controlled by making a connection to the underlying conductive silicon layer.
According to the present invention there is provided a method for fabricating an array of vacuum-microelectronic grid+emitter devices, comprising the steps of:

(a) providing a first conductive thin film layer;
(b) providing a second dielectric layer over said first conductive layer;
(c) depositing electrostatically charged particles, above said second layer, in a random pattern;
(d) transferring said random pattern into said second layer; and
(e) patterning said first and second layers, and forming and patterning a third conductive layer over said second layer, to form an array of emitters in locations defined by said random pattern, and a gate structure in said second conductive layer which is self-aligned to said array of emitters and has apertures over each one of said array of emitters.

The first conductive layer may comprise silicon.
The particles may carry a net charge, with respect to said first conductive layer, during said step (c).
Step (c) may deposit said charged particles directly onto said second layer.
Step (c) may deposit said charged particles onto a photoresist layer which overlies said second layer.
The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:

Figure 1 and 2 show an example of a field-emission display which operates on the principles of cathodoluminescent phosphors excited by cold cathode field emissions electrons. (Figure 1 shows a sectional view, and Figure 2 shows a perspective view).
Figures 3A-3E show sample steps in a Spindt process modified according to the present invention. The innovative modification, in the presently preferred embodiment, occurs at the very beginning of the process, when tips are being formed.

The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment (by way of example, and not of limitation), in which:

Figures 3A-3E show sample steps in a Spindt process modified according to the present invention. The innovative modification, in the presently preferred embodiment, occurs at the very beginning of the process, when tips are being formed.
Figure 3A shows a first stage of the innovative process, wherein a silicon layer 810 (e.g. polysilicon) is deposited on a substrate 800 of e.g. glass or quartz, to a thickness of e.g. 1.2 µm. (One of the advantages of field emission display fabrication is that the technology is highly amenable to fabrication on an insulating substrate; thus this technology has many of the fabrication advantages of thin-film transistor technology for large-area fabrication, while avoiding many of the disadvantages of that technology.)
Figure 3B shows a further stage of the innovative process, wherein the deposited silicon 810 has been oxidized to produce an oxide layer 820. (Alternatively the dielectric layer 820 may be deposited.)
Figure 3C1 shows a further stage of the innovative process, wherein microspheres 830 have been deposited in a random spaced pattern on the dielectric 820. In the presently preferred embodiment, these spheres may be e.g. 0.6 µm in diameter.
Figure 3C2 shows an alternative to the step of Figure 3C1. In this alternative embodiment a photoresist layer 822 is used to receive the spheres 830, and ultraviolet illumination then transfers the pattern defined by the spheres 830 down into the dielectric 810.
Figure 3D shows a further stage of the innovative process, wherein an anisotropic etch has been used to transfer the pattern of the spheres 830 into the dielectric 820, to produce islands 824.
Figure 3E shows a further stage of the innovative process, wherein conventional etching and deposition steps have been used to produce pointed emitters 812 at positions where the islands 824 were formerly located.

Processing then continues with conventional steps, to form a display structure as shown in Figure 1. (However, the structure formed by the disclosed innovations differs from conventional structures in having a random spacing of the emitters, rather than a strictly geometrical array.)
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.
For example, as will be obvious to those of ordinary skill in the art, a wide variety of matrix addressing circuitry and device implementations can be used to address individual emitters. Preferably the matrix addressing structure uses a striped gate, in combination with an orthogonal array of striped emitter contacts.
For another example, various spacer and phosphor structures can be used in combination with the specific emitter topologies of the presently preferred embodiment.
For another example, the specific dimensions given are merely exemplary, and can be widely varied as is well-understood by those of ordinary skill in the art.
For another example, although the presently preferred embodiment uses silicon emitters, metal or diamond or other materials can be used instead to make emitter structures according to the disclosed innovative teachings.
For another example, in one class of embodiments an unpatterned fabrication of the emitter lips, as described above, can be combined with a lithographically patterned fabrication of spacers.
For another example, emitter resistors can optionally be introduced to equalize current across individual emitter tips, and to provide protection against emitter-gate shorts.
For another example, although the presently preferred embodiment uses a single grid, the disclosed innovative teachings.can also be applied to fabrication of tetrode or pentode structures, in which an additional (focussing) grid is added to reduce divergence of the current from each emitter.
This idea can also be applied to other types of vacuum microelectronic devices, particularly to power devices. Here too there is no inherent need for small devices, but simply for a high current density.

Claims

A method for fabricating an array of vacuum-microelectronic grid+emitter devices, comprising the steps of:
(a.) providing a first conductive thin film layer;

(b.) providing a second dielectric layer over said first conductive layer;

(c.) depositing electrostatically charged particles, above said second layer, in a random pattern;

(d.) transferring said random pattern into said second layer; and

(e.) patterning said first and second layers, and forming and patterning a third conductive layer over said second layer, to form an array of emitters in locations defined by said random pattern, and a gate structure in said second conductive layer which is self-aligned to said array of emitters and has apertures over each one of said array of emitters.
The method of Claim 1, wherein said first conductive layer comprises silicon.
The method of Claim 1, wherein said particles carry a net charge, with respect to said first conductive layer, during said step (c.).
The method of Claim 1, wherein said step (c.) deposits said charged particles directly onto said second layer.
The method of Claim 1, wherein said step (c.) deposits said charged particles onto a photoresist layer which overlies said second layer.