EP0803859A3 - System and method for optimizing storage requirements for an N-way distribution channel - Google Patents

System and method for optimizing storage requirements for an N-way distribution channel Download PDF

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Publication number
EP0803859A3
EP0803859A3 EP96118476A EP96118476A EP0803859A3 EP 0803859 A3 EP0803859 A3 EP 0803859A3 EP 96118476 A EP96118476 A EP 96118476A EP 96118476 A EP96118476 A EP 96118476A EP 0803859 A3 EP0803859 A3 EP 0803859A3
Authority
EP
European Patent Office
Prior art keywords
texels
frame buffer
storage unit
buffer controller
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96118476A
Other languages
German (de)
French (fr)
Other versions
EP0803859A2 (en
Inventor
John A. Dykstal
Darel N. Emmot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of EP0803859A2 publication Critical patent/EP0803859A2/en
Publication of EP0803859A3 publication Critical patent/EP0803859A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving

Abstract

In a texture mapping computer graphics system including a texture mapping chip (46) that stores a plurality of texels (S, T) and multiple frame buffer controller chips (50A-50E) that process the texels, an interface is provided between the texture mapping chip (46) and the frame buffer controller chip. The interface includes a texel array storage unit, coupled between the texture mapping chip (46) and the frame buffer controller chips (50A-50E), that temporarily stores a limited number of texels, each texel being destined for a particular frame buffer controller chip. A control unit (110), coupled to the texel array storage unit (90), controls shifting texels from the texture mapping chip (46) into locations within the texel array storage unit (90) and transferring texels from the texel array storage unit (90) into appropriate frame buffer controller chips (50A-50E). A plurality of address storage units (114A-114E), coupled to the control unit (90), store addresses of locations within the texel array storage unit (90) in which texels are stored. Each address storage unit (114A-114E) corresponds to a different frame buffer controller chip (50A-50E).
EP96118476A 1996-04-23 1996-11-18 System and method for optimizing storage requirements for an N-way distribution channel Withdrawn EP0803859A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63625096A 1996-04-23 1996-04-23
US636250 1996-04-23

Publications (2)

Publication Number Publication Date
EP0803859A2 EP0803859A2 (en) 1997-10-29
EP0803859A3 true EP0803859A3 (en) 1998-03-04

Family

ID=24551094

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96118476A Withdrawn EP0803859A3 (en) 1996-04-23 1996-11-18 System and method for optimizing storage requirements for an N-way distribution channel

Country Status (2)

Country Link
EP (1) EP0803859A3 (en)
JP (1) JPH1083457A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4617210B2 (en) * 2005-07-13 2011-01-19 日立ビアメカニクス株式会社 Drawing apparatus and exposure apparatus equipped with the same
US8207980B2 (en) * 2007-05-01 2012-06-26 Vivante Corporation Coordinate computations for non-power of 2 texture maps
JP5669199B2 (en) * 2011-02-25 2015-02-12 Ｎｅｃソリューションイノベータ株式会社 Image drawing apparatus, image drawing method, and program

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197412A2 (en) * 1985-04-05 1986-10-15 Tektronix, Inc. Variable access frame buffer memory
EP0447227A2 (en) * 1990-03-16 1991-09-18 Hewlett-Packard Company Method and apparatus for generating textured graphics primitives in frame buffer computer graphics systems
US5230039A (en) * 1991-02-19 1993-07-20 Silicon Graphics, Inc. Texture range controls for improved texture mapping
WO1994011807A1 (en) * 1992-11-13 1994-05-26 The University Of North Carolina At Chapel Hill Architecture and apparatus for image generation
WO1995024682A1 (en) * 1994-03-07 1995-09-14 Silicon Graphics, Inc. Integrating texture memory and interpolation logic
EP0747858A2 (en) * 1995-06-06 1996-12-11 Hewlett-Packard Company Texture cache

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197412A2 (en) * 1985-04-05 1986-10-15 Tektronix, Inc. Variable access frame buffer memory
EP0447227A2 (en) * 1990-03-16 1991-09-18 Hewlett-Packard Company Method and apparatus for generating textured graphics primitives in frame buffer computer graphics systems
US5230039A (en) * 1991-02-19 1993-07-20 Silicon Graphics, Inc. Texture range controls for improved texture mapping
WO1994011807A1 (en) * 1992-11-13 1994-05-26 The University Of North Carolina At Chapel Hill Architecture and apparatus for image generation
WO1995024682A1 (en) * 1994-03-07 1995-09-14 Silicon Graphics, Inc. Integrating texture memory and interpolation logic
EP0747858A2 (en) * 1995-06-06 1996-12-11 Hewlett-Packard Company Texture cache

Also Published As

Publication number Publication date
EP0803859A2 (en) 1997-10-29
JPH1083457A (en) 1998-03-31

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