EP1051803A1 - Slew rate control circuit - Google Patents
Slew rate control circuitInfo
- Publication number
- EP1051803A1 EP1051803A1 EP99902988A EP99902988A EP1051803A1 EP 1051803 A1 EP1051803 A1 EP 1051803A1 EP 99902988 A EP99902988 A EP 99902988A EP 99902988 A EP99902988 A EP 99902988A EP 1051803 A1 EP1051803 A1 EP 1051803A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- driver
- slew rate
- transistors
- rate control
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
Definitions
- the present invention relates to the slew rate of a binary digital signal, and, more particularly, to a method or technique for adjusting or controlling this slew rate.
- processors such as microprocessors
- the effective length of the transistor channel may vary due to slight variations in the process, such as temperature and the like.
- processor speeds increase, the effect that these variations in the channel length have upon processor performance becomes of greater significance.
- the slew rate of binary digital signals produced by the processor may be affected by these variations.
- a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor.
- an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver.
- the at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.
- FIG. 1 is a block diagram illustrating an embodiment of a slew rate control circuit in accordance with the invention
- FIG. 2 is a circuit diagram illustrating a portion of the embodiment of FIG.
- FIG. 3 is a plot illustrating the slew rate of a digital output signal
- FIG. 4 is a schematic diagram illustrating an embodiment of an analog-to- digital converter circuit that may be used in or in conjunction with an embodiment of a slew rate control circuit in accordance with the invention.
- FIG. 5 is a circuit diagram illustrating an alternative embodiment of a slew rate control circuit in accordance with the invention.
- processors such as microprocessors
- the effective length of a transistor channel which may vary depending upon the process employed, temperature, and other variables, may affect the slew rate of digital output signals produced by an integrated circuit, for example. Therefore, although the invention is not restricted in scope to being employed only in connection with processors or microprocessors, the slew rate may become a performance factor due, at least in part, to high execution speeds.
- a GTL Guard Transceiver Logic
- binary digital signals may employ slew rate control to affect performance.
- binary digital signal or bit refers to a voltage signal having two voltage levels with the particular voltage levels corresponding to one of either a logical one or a logical zero signal, such as a five volt level signal and ground level signal, for example.
- slew rate When such a binary digital signal transitions from one voltage signal level to another, the slope of the voltage signal during the transition is referred to as slew rate and is typically proportional with the speed of the device. Slew rate is illustrated in the diagram of FIG. 3 and is typically specified in volts per nanosecond.
- the effective length of the channel of a transistor may vary due to a variety of factors. Likewise, because the length of the channel affects the speed of the transistor, the variation in effective channel length is directly related to to the performance/ speed of the processor under fixed environmental conditions. In this context, the effective transistor channel length is referred to as "LE.” Thus, although the transistors to be fabricated for a given integrated circuit are targeted to have a particular LE, typically the fabricated transistors are faster or slower than intended due to variations in the effective channel length of the transistor from the targeted LE.
- a relatively "tight" specification window is employed for the minimum valid time (T com ⁇ n ) and maximum valid time (T comax ) for a signal port.
- T com ⁇ n minimum valid time
- T comax maximum valid time
- this refers to, respectively, the smallest amount of time that must elapse or pass before the data signal available from a signal port is "valid,” measured with respect to an edge of a pulse of a system clock signal, and the longest amount of time to elapse after which the data signal available from the signal port, measured with respect to the same system clock signal pulse edge, is valid.
- the 3 processor may vary with LE for the associated transistors. This may occur because, as previously indicated, the speed of the transistors may vary considerably, depending, at least in part, on the deviation from a target LE. Therefore, it may be desirable in some environments to be able to adjust the slew rate of a buffer, such as an output buffer, for example, based, at least in part, on the speed of the transistors, at least to limit or reduce the noise in the overall system.
- a buffer such as an output buffer
- One way to adjust or control the slew rate is to adjust current based at least in part on the speed of the fabricated transistors.
- this control may be accomplished by a pre-driver stage or pre-driver circuitry, such as may be used in conjunction with a buffer, so that the pre-driver stage does not provide as much drive current if the transistors are too fast and provides excess current if the transistors are too slow, although the invention is not limited in scope in this respect.
- Such pre-driver circuitry may also be used in conjunction with a buffer on a processor, such as a microprocessor.
- the invention is not limited in scope to this embodiment.
- the resistance of the driving transistor may be adjusted to affect the slew rate. Likewise, the resistance and current may both be adjusted.
- FIG. 1 is a block diagram illustrating an embodiment 100 of a slew rate control circuit in accordance with the present invention.
- This particular embodiment is illustrated in conjunction with a pre-driver 1 60 coupling to the gate, such as gate 0, of a output driver for an output buffer although, as previously indicated, the invention is not restricted in scope to an output buffer.
- Coupled to pre-driver 1 60 in this embodiment is a plurality of pre-driver cells, 1 10, 1 20, 1 30, 140, and 1 50.
- a single pre-driver cell, at least one pre-driver cell, or more pre-driver cells may be coupled to a pre-driver, such as 1 60.
- pre-driver refers to a circuit prior to the final or output driver, including a circuit not immediately prior, in the data path, that has the capability to affect T comin and/or T comax .
- the pre-driver and pre-driver cells in this particular embodiment form a pre-driver stage.
- the plurality of ceils are each in this embodiment coupled by bit lines to a register capable of storing a plurality of binary digital signals.
- the term register refers to one or more sequential elements coupled in a chain or series.
- sequential element refers to a component of a circuit controlled by a clock signal, such as a latch or
- each cell is coupled to a separate sequential element of the register (see FIG. 4, for example). This is illustrated in FIG. 1 by bit lines 1 51 , 1 52, 1 53, 1 54, and 1 55.
- the output port of each ceil in this particular embodiment is coupled to a gate of the driver, such as gate 0, along with an output port of pre-driver 1 60.
- FIG. 1 illustrates the output ports of pre-driver 1 60 coupling to four gates.
- pre-driver 1 60 employs GTL phase control. Therefore, many transistors are employed as the output driver and the transistors are activated at different phases using pass gates to provide delay between activation.
- each pre-driver cell is coupled to pre-driver 1 60 and to a sequential cell of the register to adjust or modify the current supplied by the pre-driver based, at least in part, on a plurality of binary digital signals capable of being stored in the register.
- the binary digital signal or signals may simply be loaded into the register from an external source.
- the binary digital signal or signals may be based, at least in part, on measuring the "turn on" resistance of one or more fabricated transistors.
- the "turn on” resistance of a transistor is directly related to the effective length of the transistor channel and, therefore, this measurement should provide information regarding whether the transistor is relatively fast or relatively slow compared to one having the target LE.
- This analog signal information regarding the "turn on” resistance may then be transformed to a binary digital signal or signals using an analog-to-digital converter coupled in a feedback configuration, as illustrated in FIG. 4.
- FIG. 4 illustrates one embodiment of an analog-to-digital converter coupled in a feedback configuration to accomplish this result. This particular embodiment is illustrated as providing
- FIG. 4 is a schematic diagram illustrating an embodiment 500 of a circuit for converting the "turn on" resistance measured for one or more transistors to a plurality of binary digital signals.
- this particular embodiment includes: a comparator 520, a five-bit counter 510, and five transistors, 530, 540, 550, 560, and 570.
- counter 510 also operates as a register.
- the relative size of transistors 530 to 570 are binary- weighted.
- Comparator 520 in operation shall provide up and down digital signals to counter 510.
- the comparator in this feedback configuration in equilibrium, approximately equalizes the voltage provided to the plus terminal of 520 with the voltage provided to the minus terminal of 520.
- Resistances 585, 590, and 595 are all equal in this embodiment and counter 510 is coupled to the respective five transistors so that when a bit for a logical one signal is stored in a respective cell of the counter, the corresponding transistor is "turned on” , and so that when a bit for a logical zero signal is stored in a cell of the counter, the corresponding transistor is turned off.
- the circuit operates so that the "turn on" resistance of selected transistors indicated by counter 510 as being “on” in equilibrium approximately equals the resistance R.
- the resistances need not be equal.
- 585 comprises external precision resistor that does not vary with environmental conditions.
- Resistors 590 and 595 are implemented internally using two transistors that are coupled to provide Vcc/2 to 520. Thus, process variations from one transistor are offset by the other in the case . Of course, a variety of other approaches will suffice also. In this embodiment, N-channel transistors are employed; however, P- channel transistors or both N and P-channel transistors may be employed in an alternative embodiment.
- the specific binary digital signals determined by this circuit and contained in counter 510 are then provided as illustrated in FIG. 1 , along bit lines 1 51 , 1 52, 1 53, 1 54, and 1 55.
- the transistors of pre-driver cells 1 10, 1 20, 1 30, 140, and 1 50 are binary-weighted, as shall be described in more detail hereinafter, so that a substantially linear relationship exists between the contents of counter 510 and the effect on pre-driver 1 60. If the value of the bit, referred to here as the control bit, from counter 510 corresponding to a
- the binary-weighted pre-driver turns on and provides more drive to switch the gate of the driver for the buffer, gate 0 in this example.
- the binary-weighted pre-driver cell corresponding to that control bit does not provide additional drive to switch the gate of the driver.
- the resistance R is chosen so that a mid-range binary value, such as 01000 by the counter, approximately corresponds a channel length of the target LE.
- the counter should exceed 1 6 and if the transistors are fast, it should be below 1 6.
- the invention is not limited in scope in this respect.
- a desirable aspect of this particular embodiment of a slew rate control circuit with the invention is its ease of testability.
- the five binary weighted pre-driver cells are logically redundant.
- this fault would be difficult, if not impossible, to detect.
- a fault may result in a buffer, for example, that is too fast or too slow.
- pre-driver 1 60 may be turned off or tri-stated, as illustrated, based on a signal provided by NAND gate 1 70. More specifically, "test #" is high when it is desired to test the pre-driver cells.
- test # when test # is low, the output signal of 170 enables the pre-driver cells.
- pre-driver 1 60 is tri- stated because port “test #” of 1 60 is low and port “test” of 1 60 is high.
- a data signal may be driven one bit at a time through the binary weighted control cells, 1 50 to 1 10. This may be accomplished by loading selected binary digital signals into counter/register 510 to test the particular or selected cell. Therefore, referring to FIG. 1 , the only additional circuitry to provide this testability feature is NAND gate 1 70 and the control line to the cells.
- FIG. 2 shows the internal circuitry of pre-driver cell 1 50 in this particular embodiment, thereby illustrating the operation of this particular embodiment of a slew rate control circuit in accordance with the present invention.
- a signal to be provided at the output port of the buffer designated "in #" is applied to transistors 240 and 250.
- transistors 240 and 250 are coupled to form an inverter and the output signal of that device is provided to the gate of the buffer driver.
- This inverter is provided so that in this embodiment the logic of the output signal of a pre-driver cell, such as 150,
- pre-driver 160 may be employed. However, in this particular embodiment, the remaining cells are similar except that the transistors are binary-weighted in size in order to provide the appropriate amount of additional current to correspond to the binary digital signal provided to that particular pre-driver cell from counter 510.
- the slew rate control circuit may be employed to adjust the siew rate for a digital output signal produced by a buffer, such as an output buffer, so that an integrated circuit employing such a buffer or output buffer may be employed in a variety of different circuits or circuit environments without redesigning the integrated circuit.
- a buffer such as an output buffer
- an integrated circuit employing such a buffer or output buffer may be employed in a variety of different circuits or circuit environments without redesigning the integrated circuit.
- a processor or microprocessor including an embodiment of a slew rate control circuit in accordance with the present invention may be employed in a variety of computer systems without redesigning the processor or microprocessor.
- Such a processor or microprocessor might be employed in a desk top system, a lap top system, a mobile system and a variety of other systems in which T com ⁇ n , and T comax may all be different over a particular range and likewise the slew rate may be different over a particular range.
- An embodiment of a slew rate control circuit in accordance with the invention may be employed to adjust or control the slew rate to meet the specifications of the particular computer system in which the processor or microprocessor is to be employed. In this embodiment, this may be
- FIG. 5 is a circuit diagram illustrating another alternative embodiment of a slew rate control circuit in accordance with the present invention.
- pre-driver 660 corresponds to pre-driver 1 60 of FIG. 1 .
- pre-driver cells 610, 620, 630, 640, and 650 correspond to driver cells 1 10 to 1 50.
- Bit lines 651 , 652, 653, 654 and 655 correspond to bit lines 1 51 to 155 of FIG. 1 .
- gates 670 and 680 correspond to gates 170 and 180 of FIG. 1 .
- One difference between this particular embodiment and the embodiment illustrated in FIG. 1 is the inclusion of pass gates 661 , 662, 663, 664 and 665.
- pass gates 661 , 662, 663, 664 and 665 For the embodiment illustrated in FIG.
- gate 0 was employed because in this particular embodiment gate 0 is coupled to a majority of the transistors of the output driver, as previously described. However, in this particular embodiment, in addition to coupling the output ports of cells 610 to 650 to gate 0, these output ports are further coupled to gate 1 , as illustrated in FIG. 5. However, as previously described, although the invention is not limited in scope in this respect, this particular embodiment employs GTL ( or GTL + ) phase control. Therefore, current will be applied to gate 1 on a different phase than the phase on which current is applied to gate 0.
- GTL or GTL +
- pass gates 661 to 665 are introduced to provide a delay corresponding to the delay between the current being applied to gate 0 and the current being applied to gate 1 .
- this particular embodiment provides the capability to affect the drive current for more transistors of the output driver than the embodiment illustrated in FIG. 1 .
- another or separate set of pre-driver cells may be employed and coupled to the bit lines from, for example, counter 510 and, likewise, coupled to "enable #" and "in #" signals and the output ports of these cells may be coupled to gate 1 to provide current modification or adjustment.
- An embodiment of a method of adjusting the slew rate of a digital output signal produced by a buffer in accordance with the present invention may operate in the following manner.
- Current supplied to drive an output driver of the buffer may be
- the contents of counter 510 may be employed to adjust the current supplied to gate 0 and, therefore, drive an output driver.
- a binary digital signal may be loaded into counter 510, which is also a register in this context.
- a measured "turn on" resistance of at least one transistor may be converted to one or more binary digital signals and contained in a register.
- the "turn on" resistance of at least one, and possibly, more transistors may be measured, and using an operational amplifier coupled in the feedback configuration, such as illustrated in FIG.
- this measured turn on resistance may then be converted to one or more binary digital signals and stored in counter 510, for example.
- this "turn on" resistance measurement also indicates whether the channel length of the transistors deviates from a target LE and also provides an indication of the amount of deviation. This deviation from the target LE may result in a faster or slower transistor and, therefore, it is desirable to adjust the current supplied to drive the output driver in accordance with this "turn on" resistance measurement.
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12120 | 1998-01-22 | ||
US09/012,120 US6075379A (en) | 1998-01-22 | 1998-01-22 | Slew rate control circuit |
PCT/US1999/000200 WO1999038258A1 (en) | 1998-01-22 | 1999-01-05 | Slew rate control circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1051803A1 true EP1051803A1 (en) | 2000-11-15 |
EP1051803A4 EP1051803A4 (en) | 2001-10-04 |
EP1051803B1 EP1051803B1 (en) | 2005-10-12 |
Family
ID=21753487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99902988A Expired - Lifetime EP1051803B1 (en) | 1998-01-22 | 1999-01-05 | Slew rate control circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US6075379A (en) |
EP (1) | EP1051803B1 (en) |
AU (1) | AU2311299A (en) |
DE (1) | DE69927671T2 (en) |
WO (1) | WO1999038258A1 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6157204A (en) * | 1998-08-05 | 2000-12-05 | Micron Technology, Inc. | Buffer with adjustable slew rate and a method of providing an adjustable slew rate |
US6218863B1 (en) * | 1999-04-12 | 2001-04-17 | Intel Corporation | Dual mode input/output interface circuit |
JP4832635B2 (en) * | 2000-12-05 | 2011-12-07 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Data transmission system, data transmission method, data recording apparatus, and computer system |
US6617895B2 (en) * | 2001-03-30 | 2003-09-09 | Intel Corporation | Method and device for symmetrical slew rate calibration |
US6633178B2 (en) * | 2001-09-28 | 2003-10-14 | Intel Corporation | Apparatus and method for power efficient line driver |
CN1898869A (en) * | 2003-12-23 | 2007-01-17 | 皇家飞利浦电子股份有限公司 | Load-aware circuit arrangement |
US7009894B2 (en) * | 2004-02-19 | 2006-03-07 | Intel Corporation | Dynamically activated memory controller data termination |
KR100693922B1 (en) | 2004-12-24 | 2007-03-12 | 삼성전자주식회사 | Push-pull output driver with capability of controlling slew rate and driving strength |
US20060253663A1 (en) * | 2005-05-06 | 2006-11-09 | Micron Technology, Inc. | Memory device and method having a data bypass path to allow rapid testing and calibration |
US7372291B2 (en) * | 2005-09-30 | 2008-05-13 | Stmicroelectronics Asia Pacific Pte. Ltd. | Circuits having precision voltage clamping levels and method |
KR100771544B1 (en) | 2006-06-29 | 2007-10-31 | 주식회사 하이닉스반도체 | Output circuit |
US7902885B2 (en) * | 2006-12-28 | 2011-03-08 | Stmicroelectronics Pvt. Ltd. | Compensated output buffer for improving slew control rate |
JP2011004038A (en) * | 2009-06-17 | 2011-01-06 | Hitachi Ltd | Semiconductor lsi and semiconductor device |
US9614506B1 (en) * | 2015-12-03 | 2017-04-04 | Texas Instruments Incorporated | Digital pre-compensation for voltage slewing in a power converter |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5220208A (en) * | 1991-04-29 | 1993-06-15 | Texas Instruments Incorporated | Circuitry and method for controlling current in an electronic circuit |
US5498977A (en) * | 1995-03-03 | 1996-03-12 | Hewlett-Packard Company | Output driver having process, voltage and temperature compensation for delay and risetime |
US5519338A (en) * | 1994-09-14 | 1996-05-21 | Microunity Systems Engineering, Inc. | Controlled slew rate output buffer |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5118971A (en) * | 1988-06-29 | 1992-06-02 | Texas Instruments Incorporated | Adjustable low noise output circuit responsive to environmental conditions |
US5134311A (en) * | 1990-06-07 | 1992-07-28 | International Business Machines Corporation | Self-adjusting impedance matching driver |
US5162672A (en) * | 1990-12-24 | 1992-11-10 | Motorola, Inc. | Data processor having an output terminal with selectable output impedances |
US5254883A (en) * | 1992-04-22 | 1993-10-19 | Rambus, Inc. | Electrical current source circuitry for a bus |
US5537070A (en) * | 1994-10-14 | 1996-07-16 | Texas Instruments Incorporated | Output driver with slew rate control |
US5568081A (en) * | 1995-06-07 | 1996-10-22 | Cypress Semiconductor, Corporation | Variable slew control for output buffers |
US5926032A (en) * | 1995-08-14 | 1999-07-20 | Compaq Computer Corporation | Accommodating components |
US5781050A (en) * | 1996-11-15 | 1998-07-14 | Lsi Logic Corporation | Open drain output driver having digital slew rate control |
-
1998
- 1998-01-22 US US09/012,120 patent/US6075379A/en not_active Expired - Lifetime
-
1999
- 1999-01-05 DE DE69927671T patent/DE69927671T2/en not_active Expired - Lifetime
- 1999-01-05 WO PCT/US1999/000200 patent/WO1999038258A1/en active IP Right Grant
- 1999-01-05 AU AU23112/99A patent/AU2311299A/en not_active Abandoned
- 1999-01-05 EP EP99902988A patent/EP1051803B1/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5220208A (en) * | 1991-04-29 | 1993-06-15 | Texas Instruments Incorporated | Circuitry and method for controlling current in an electronic circuit |
US5519338A (en) * | 1994-09-14 | 1996-05-21 | Microunity Systems Engineering, Inc. | Controlled slew rate output buffer |
US5498977A (en) * | 1995-03-03 | 1996-03-12 | Hewlett-Packard Company | Output driver having process, voltage and temperature compensation for delay and risetime |
Non-Patent Citations (1)
Title |
---|
See also references of WO9938258A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP1051803B1 (en) | 2005-10-12 |
AU2311299A (en) | 1999-08-09 |
EP1051803A4 (en) | 2001-10-04 |
DE69927671D1 (en) | 2006-02-23 |
WO1999038258A1 (en) | 1999-07-29 |
US6075379A (en) | 2000-06-13 |
DE69927671T2 (en) | 2006-08-10 |
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