EP1061580A3 - Method and circuit for minimizing the charging effect during manufacture of semiconductor devices - Google Patents

Method and circuit for minimizing the charging effect during manufacture of semiconductor devices Download PDF

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Publication number
EP1061580A3
EP1061580A3 EP00305161A EP00305161A EP1061580A3 EP 1061580 A3 EP1061580 A3 EP 1061580A3 EP 00305161 A EP00305161 A EP 00305161A EP 00305161 A EP00305161 A EP 00305161A EP 1061580 A3 EP1061580 A3 EP 1061580A3
Authority
EP
European Patent Office
Prior art keywords
protection transistor
antenna
protection
minimizing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00305161A
Other languages
German (de)
French (fr)
Other versions
EP1061580A2 (en
Inventor
Boaz Eitan
Ilan Bloom
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion Israel Ltd
Original Assignee
Spansion Israel Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Israel Ltd filed Critical Spansion Israel Ltd
Publication of EP1061580A2 publication Critical patent/EP1061580A2/en
Publication of EP1061580A3 publication Critical patent/EP1061580A3/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor (52) and an antenna (55). The protection transistor is connected between a metal line (40) having devices to be protected electrically connected thereto and a ground supply (41), where the metal line is connected to devices (50) to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna (55) is connected to a gate (G) of the protection transistor. Optionally, there is a metal ring (112, Fig. 7) around the antenna which is connected to a drain (D) of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off. Turning off is provided either by a line formed of a second metal layer that is connected between the antenna and ground, or by a reversed biased diode (118) and a parallel capacitor (120) that are connected between the gate of the protection transistor and ground. The present invention includes the method of manufacturing the protection device.
Figure 00000001
EP00305161A 1999-06-18 2000-06-19 Method and circuit for minimizing the charging effect during manufacture of semiconductor devices Withdrawn EP1061580A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/336,666 US6337502B1 (en) 1999-06-18 1999-06-18 Method and circuit for minimizing the charging effect during manufacture of semiconductor devices
US336666 1999-06-18

Publications (2)

Publication Number Publication Date
EP1061580A2 EP1061580A2 (en) 2000-12-20
EP1061580A3 true EP1061580A3 (en) 2001-05-30

Family

ID=23317125

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00305161A Withdrawn EP1061580A3 (en) 1999-06-18 2000-06-19 Method and circuit for minimizing the charging effect during manufacture of semiconductor devices

Country Status (3)

Country Link
US (2) US6337502B1 (en)
EP (1) EP1061580A3 (en)
JP (1) JP2001057389A (en)

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US7098107B2 (en) * 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
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DE10211359A1 (en) * 2002-03-14 2003-10-02 Infineon Technologies Ag Determination arrangement, method for determining electrical charge carriers and use of an ONO field-effect transistor for determining an electrical charge
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US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
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US6885244B2 (en) 2003-03-24 2005-04-26 Saifun Semiconductors Ltd. Operational amplifier with fast rise time
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US8339102B2 (en) * 2004-02-10 2012-12-25 Spansion Israel Ltd System and method for regulating loading on an integrated circuit power supply
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US7187595B2 (en) * 2004-06-08 2007-03-06 Saifun Semiconductors Ltd. Replenishment for internal voltage
US7256438B2 (en) * 2004-06-08 2007-08-14 Saifun Semiconductors Ltd MOS capacitor with reduced parasitic capacitance
US7190212B2 (en) * 2004-06-08 2007-03-13 Saifun Semiconductors Ltd Power-up and BGREF circuitry
US7317633B2 (en) * 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060068551A1 (en) * 2004-09-27 2006-03-30 Saifun Semiconductors, Ltd. Method for embedding NROM
US7638850B2 (en) * 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7402868B2 (en) 2004-11-01 2008-07-22 Spansion L.L.C. System and method for protecting semiconductor devices
US20060146624A1 (en) * 2004-12-02 2006-07-06 Saifun Semiconductors, Ltd. Current folding sense amplifier
US20060145263A1 (en) * 2005-01-06 2006-07-06 Macronix International Co., Ltd. Plasma damage protection circuit for protecting multiple word lines or strapped word lines of a memory device
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US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
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US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
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JP2009054909A (en) * 2007-08-29 2009-03-12 Panasonic Corp Semiconductor device, its manufacturing method and driving method
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Also Published As

Publication number Publication date
EP1061580A2 (en) 2000-12-20
US6337502B1 (en) 2002-01-08
US6627555B2 (en) 2003-09-30
US20010026970A1 (en) 2001-10-04
JP2001057389A (en) 2001-02-27

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