EP1206325A2

EP1206325A2 - Vapor phase connection techniques

Info

Publication number: EP1206325A2
Application number: EP00954052A
Authority: EP
Inventors: Belgacem Haba; John W. Smith
Original assignee: Tessera LLC
Current assignee: Adeia Semiconductor Solutions LLC
Priority date: 1999-08-11
Filing date: 2000-08-11
Publication date: 2002-05-22
Also published as: JP2003506891A; AU6640000A; KR100764582B1; KR20020021405A; WO2001011662A3; WO2001011662A2; EP1206325A4

Abstract

Electrical connections are made between a pair of elements (32, 38) disposed on opposite side of a hole (28) extending through a dielectric layer (20) by evaporating a conductive material (40) such as a metal having high vapor pressure within the hole while maintaining the hole in a substantially sealed condition. The process may be performed simultaneously to form numerous connections within a microelectronic unit as, for example, within a multilayer circuit panel.

Description

VAPOR PHASE CONNECTION TECHNIQUES

FIELD OF THE INVENTION

The piesent invention relates to microelectronic components and fabiication of microelectionic components

BACKGROUND ART

Numerous microelectronic components incorporate insulating or "dielectπc" layers and conductois extending through such layeis The directions along the surfaces of the layers aie commonly leferred to as "horizontal" directions, whereas the direction thiough the layers is commonly refeired to as the "\ ertical" or "z" direction The conductors extending through the layers are commonly refened to as z-direction conductors or "vias" For example, a multilayei microelectronic circuit panel may include several dielectπc layers Each dielectπc layer has conductors extending along one or both surfaces of the layer in horizontal directions and has vias extending through the layer to connect certain conductors on opposite sides of the panel with one another Typically, such a multi-layer circuit is fabricated by a sequential process Each dielectric layer is deposited on previously-formed dielectric layers and the processes needed to form the vias and the horizontal conductors are performed Such a sequential buildup process suffers from numerous drawbacks, including significant loss of productivity caused by quality problems If any defect occurs in formation of a later layer, the entire multi-layer structure must be discarded

As taught in certain preferred embodiments of commonly assigned United States patents 5,367,764 and 5,282,312, multi-layer circuit panels can be fabricated using a parallel- processing approach In this approach, the vaπous panels constituting the multi-layer structure are fabricated separately and then stacked together with mterposers incorporating a curable dielectπc matenal such as an epoxy and also incorporating masses of electrically conductive joining material such as solder extending through the mterposer at predetermined locations The stacked assembly is then cured as, for example, under heat and pressure The dielectric material joins the circuit panels to one another and the electrically conductive material forms conductive pathways between conductors on the vaπous panels Because the individual panels can be tested prior to assembly, defects in the panel manufactuπng process do not result m loss of the entire assembly Also, as further explained in the aforementioned '764 and '312 patents, the individual panels can be selectively treated so that vertical connections between panels are made only at certain locations Other processes involving parallel production of multiple circuit panels and assembly a stack are taught in certain preferred embodiments of co-pendmg, commonly assigned PCT Application PCT/US97/23948, published as International Publication No 98/26476 and US Patent 5,590,460 As taught m certain preferred embodiments of the '460 patent and '948 PCT application, multiple circuit panels can be stacked and electrically interconnected with one another and mechanically engaging features on the circuit panels with features of conductive elements carried on mterposer layers

These appioaches offer useful solutions to the encountered m fabrication of multi-layer problems However, even with these improvements, the circuit panels typically still include v ias extending through dielectric layers Such vias commonly are formed by providing holes m the dielectnc layers and depositing a conductive metal in the dielectπc layers by processes such as electroless plating and electroplating These processes work well with relatively large vias However, it would be desirable to provide smaller vias so as to make the entire assembly more compact It is difficult to form relatively small vias, such as circular vias having diameters less than about 60 microns and, more particularly, less than about 25 microns by plating

Various proposals have been advanced for depositing conductive materials into holes to form vias by techniques other than plating Cranston, et al , U S Patent 3,562,009 shows a process for forming "metahzed through-holes" by positioning a metallic element at a lower surface of a substrate having a hole formed therein and directing a laser beam or electron beam from above the substrate through the open top end of the hole onto the metal, thereby evaporating the metal onto the walls of the hole In other embodiments, this reference discloses directing a similar beam onto a mass of powdered material disposed within the hole This method suffers obvious drawbacks as a production technique, including the need to direct a powerful beam sequentially onto various locations on the substrate and hold the beam at each location for a time sufficient to vaporize the matenal Moreover, this method is useful only to process a single substrate at a time Beilin, et al , U S Patent 5,454,161 discloses metal organic chemical vapor deposition ("MOCVD") of metal into openings of a dielectric layer In the MOCVD process, the substrate is held in the reaction chamber so that openings of the holes are exposed to the interior of the reaction chamber A metal-contammg gaseous composition is introduced into the chamber The composition decomposes to deposit metal m the open vias Yamaguchi, et al , U S Patent, 5,589,668 discloses a similar process using vapor deposition methods such as evaporation, ion plating, or sputtering In all of these processes, the substrate is held w ithin a chambei so that openings of the vias aie open to the inteiioi of the substrate Each substiate must be held withm a relatively complex and expensive treatment apparatus foi a time sufficient to build up the required metallic layer withm its vias Moreovei, stacked substrates cannot be tieated U S Patent, 4,933,045 refers to metahzation of vias by "evaporation, sputtering oi plating" as assertedly "well-known m the art" but does not offei furthei details of such processes Despite these attempts to use vapor deposition for forming \ ιas. there is still need foi bettei useful and economical vias-formmg process

Anothei common problem encountered in fabrication of microelectronic assemblies is mounting and connecting one component to anothei For example, a semiconductor chip or othei microelectronic de\ ice typically must be connected to a circuit panel As described m certain preferred embodiments of commonly assigned United States Patent 5,148,265 and 5,148.266 and 5,347,159. the contacts of a semiconductor chip may be electrically connected to terminals on a small circuit panel or connection component overlying a face of the chip itself The terminals on the connection component in turn are connected to contact pads on a substrate such as a cncuit panel Desirably, the connection component is movable with respect to the chip to accommodate dimensional changes caused by thermal effects during manufacture and/or use The connections between the chip contacts and the mterposer can be made by various methods For example, these connections can be made by wire-bonding or by techniques such as thermosonic or ultrasonic bonding of pre-fabπcated leads on the mterposer to the chip contacts Further improvements in lead bonding are taught, for example, m United States Patent 5,536,909, 5,787,581 and PCT International Publication 94/03036 These processes provide marked improvements m chip connection processes and m the resulting assemblies

In a process known as flip-chip bonding, contacts on the chip are bonded directly to contact pads on a substrate such as a circuit board using solder balls All of the contacts of the chip may be connected simultaneously However, flip-chip bonding requires considerable spacing between contacts on the chip to accommodate the solder balls and suffers from other drawbacks including susceptibility to thermal stresses

As described m United States Patent 5,518,964, numerous connections on a semiconductor chip or wafer can be made simultaneously by superposing an element such as a dielectric substrate having leads thereon with the chip or wafer bonding tip ends of the leads to the contacts on the chip and moving the element away from the chip or wafer so as to deform the leads The resulting structure provides compensation for thermal effects and provides a high-iehability interconnection with the chip Nonetheless, it would be desirable to piovide even furthei ιmpιo\ ements m methods for connecting components to one anothei

Kim, U S Patent 5,407.864 proposes mounting a chip on one surface of a circuit panel so that the contacts of the chip face down onto a top surface of a circuit boaid The contacts on the chip are aligned with through-holes extending through the circuit boaid, to the bottom suiface thereof A metal is deposited through the openings of the through-holes at the bottom surface, as by sputtering, screening, electroplating oi evaporation, so that the deposited metal forms conductive extensions of the chip contacts extending through the holes to conductors on the circuit boaid This method suffers from the obvious drawback that holes must extend through the cncuit board at each chip contact location This, m turn, makes it impractical to mount a chip onto a multi-layer circuit panel Moieovei, where the process is performed using an evapoiative technique, the structure, including the chip and the cncuit panel must be retained m the evaporation apparatus for the full time required to deposit the metal Additionally, the resulting struct e has no ability to take up differential expansion and contraction between the chip and the circuit panel Thus, despite all of the effort m the art presented by the aforementioned patents and publications, further improvements m via formation and connection techniques would be desirable

DISCLOSURE OF THE INVENTION One aspect of the present invention provides a method of making connections m a microelectronic unit A method according to this aspect of the invention includes the step of providing fust and second conductive elements and a dielectric so that the dielectric and the conductive elements cooperatively define a substantially closed chambei A dispersible conductive material, such as a metal having appreciable vapor pressure is also provided withm the chambei For example, low -melting metals such as tm, gallium, silver, mdium and alloys thereof may be used Other low-melting alloys include alloys containing one or more of tin, bismuth and antimony The method further includes the step of dispersing the conductive material withm the substantially closed chamber so that the conductive material deposits on the dielectric and forms a connector extending between the conductive elements Most preferably, the step of dispersing the conductive material is performed by evaporating the conductive material withm the chambei The chamber desirably is maintained under subatmospheπc pressure Alternatively or additionally, the atmosphere withm the chamber may consist essentially of one or more inert gases, most preferably argon The dielectπc, the conductive elements oi both maintain the chamber substantially isolated from the sunoundmgs during the dispeising step, so that the dispersing step occurs without appreciable transfer of the conductn e material into the chambers during the dispersing step Stated another way, the conductπ e matenal already present withm the substantially closed chambei s is dispersed m situ Most pieferably, the substantially closed chamber is sealed gas-tight by the conductive elements, the dielectric or both

The step of providing first and second conductive elements and a dielectric may include pioviding a dielectπc layer ha\mg oppositely directed first and second surfaces and having one oi moie holes extending through the layer between the surfaces, and providing the first and second conductive elements so that they overlie the hole on the first and second surfaces of the dielectric layer For example, the first conductive elements, the second conductive elements or both may be provided on separate bodies bearing these elements These bodies may be laminated onto the dielectric layer, thereby forming one or more chambers as discussed above The conductive material may be provided on the conductive elements as, for example, by depositing the conductive material through one or more techniques such as electroplating, electroless plating, sputtering, evaporation and chemical vapor deposition

Once the chamber or chambers is or are closed, the process of evaporation simply requires maintaining the assembly at a suitable temperature for a sufficient time to allow the conductive material to redistribute itself withm the chambers by evaporation The assembly may be maintained under an external, surrounding subatmospheπc pressure as, for example, by holding the assembly withm a temporary housing or storage bin held at subatmospheπc pressure so as to minimize mechanical stress on the assembly and minimize diffusion into the chamber or chambers However, there is no need to maintain the assembly withm specialized processing apparatus during the evaporation process The evaporation process may occur, for example, withm a simple oven or holding fixture

Numerous connections can be formed simultaneously using these methods For example, hundreds or thousands of connections can be formed between individual conductive elements of an assembly during a single evaporation step The process is inherently reliable, provided that the conductive matenal is present and the conductive elements are exposed to the interior of the chamber, the conductive material will form a conductor connecting the conductive elements Moreover, the evaporation process can be repeated after the assembly is tested to repair any defects detected dunng testing operation If an assembly has defects, the assembly is simply recycled into the heating step, without further processing Unlike conventional ia-formmg piocesses such as electroplating, the process according to this aspect of this invention works best with small holes For example, holes having cross-sectional dimensions on the ordei of 60 micrometers or less, and more prefeiably 25 micrometers (about 0 001 inches) oi less may be used successfully The process thus lends itself well to fabncation of extremely compact, high density circuits

A furthei process according to this aspect of the invention includes the step of providing a first dielectric layer having first and second surfaces and having a plurality of holes extending thiough such layei between the first and second surfaces and providing first conductive elements adjacent the first surface and second conductive elements adjacent to second suiface so that these conductive elements aie aligned with at least some of the holes For example, the step of providing the first conductive element may include providing a first body having the conductive elements thereon juxtaposed with first surface of the dielectric layer The second conductive elements may be provided on a similar, second body juxtaposed with the second surface of the dielectric layer A method according to this aspect of the invention desirably further includes the step of providing a conductive material in at least some of the holes which have the first and second conductive elements aligned therewith and dispersing the conductive materials, preferably by e\ aporatmg the conductive mateπals, so as to form conductors interconnecting the first and second conductive elements which are aligned with at least some of the holes The process can be used to provide connections to a semiconductor chip or other microelectronic element having contacts on a front surface Thus, the first body used in the aforementioned process may be a chip, an assemblage of plural discrete chips or an integral wafer incorporating numerous semiconductor chips The dielectric layer may be provided on the contact-bearing front surface of the chip, assembly or wafer as by applying a curable adhesive to the front surface and bonding a preformed dielectric layer onto the adhesive or by applying the dielectric layer as a coating and cuπng and curing the coating The holes may be formed in the dielectric layer in alignment with the contacts either before or after applying the dielectric later to the front surface In this arrangement, the contacts on the microelectronic element sen e as the first conductive elements The second conductive elements may be provided on a circuit panel or other mounting substrate In certain embodiments, the second conductive elements may include elongated conductors having fixed ends and free ends The fixed ends are aligned with at least some of the hole sm the dielectric element The free ends of the leads may be displaceable relative to the dielectric layer so that a second microelectronic element may be attached to the fiee ends of the elongated conductors and moved away from the dielectric layer so as to deform the conductors Alternatively, the dielectric layer may include elongated lead regions having fixed ends and having free ends displaceable with lespect to the remainder of the dielectric layer At least some of the conductors desirably extend along these elongated lead regions so that the free end of each such elongated conductor is disposed adjacently free end of an associated lead region Heie again, a further micioelectromc element may be assembled to the free ends of the leads and moved away from the first micioelectromc element and dielectnc layer to deform the leads As further discussed belo , such processes can provide semiconductoi chip packages and mountings with the ability to take up relative movement caused by thermal effects

At least one of the steps of providing first conductive elements, providing second conductive elements, and providing conductive material may be performed selectively so that the first conductive element, the second conductive element, or the conductive material is omitted at least some of the holes and hence no connection is made between first and second conductive elements at those holes The process therefore can be used to form connections selectively As discussed below, selective formation of conductive elements and/or selective application of conductive material can be achieved readily using known techniques such as selective plating or etching, screen printing and selective vapor deposition, as for example, using a mask to block vapor deposition in areas where deposition is not wanted According to a further variant, the process may incorporate the step of providing a stacked structure including one or more dielectric layers and plural layers of conductive elements separated from one another by these one or more dielectπc layers At least some of the conductive elements m different layers are aligned with one another at one or more sites and the dielectric layers have holes extending through them between the aligned conductive elements at at least some of the sites Here again, a dispersible conductive material such as the aforementioned high- vapor pressure metals is supplied at at least some of the sites After the stacked structure has been made, the conductive material is evaporated onto the walls of the holes in the dielectric layers to thereby form vertical connections between conductive elements The conductive metal may be evaporated withm holes m all of the stacked layers simultaneously

The vertical connections are formed at only those sites where the conductive elements are aligned with one another, where the dielectric layer which is disposed between these aligned conductive elements has a hole m alignment with the conductive element and where the conductiv e material is provided This method is particularly well-suited to manufacture of multi-layer circuitry Thus, the one or more dielectric layers typically includes numerous dielectπc layers The vertical conductors extending through the stacked structure can be provided selectively by conducting any one of several steps selectively For example, the step of providing holes m the dielectric layers may be performed selectively so that holes are provided at less than all of the sites The holes may be disposed at locations of a regulai grid pattern, but less than all of such locations may be provided with holes Also, the step of applying the evaporable conductive material may be performed selectively For example, where the conductive material is applied onto the conductive elements before stacking as, for example, where the conductiv e material is applied by plating, the conductive material may be applied selectively by masking areas where conductive material is not wanted before plating or by selectively etching away the conductive material using an etchant which does not attack the conductive elements substantially Stated another way, the operations required to piovide conductive material m a selective manner to less than all of the sites may involve only conventional procedures commonly used for applying metals m a controlled fashion m microelectronic circuit processing

The layers of conductive elements may include first direction and second direction layers arranged m alternating order The conductive elements m each first direction layer include elongated traces extending predominantly in a first horizontal direction whereas the conductive elements in each second direction layer have elongated traces extending predominantly m a second hoπzontal direction transverse to the first horizontal direction The holes are desirably arranged at at lest some locations of a regular grid pattern corresponding to crossing points of the first direction and second direction traces Such an arrangement provides complete flexibility m layout of the circuit Moreover, because very small vias can be employed, there is no need to provide enlarged features at the crossing points

In further variants, the conductive matenal may be dispersed withm the chambers by processes which do not entail evaporation as, for example, by applying sonic energy to atomize the conductive matenal m a liquid state or to mechanically spread the liquid conductive material Here again, the process desirably does not rely upon filling of the chamber or via with liquid In still other variants, a conductive material precursor is provided within the closed chambers and reacts to form a conductive matenal within the closed chambers BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a diagrammatic perspective view depicting certain components used n one embodiment of the invention

Figure 2 is a diagrammatic sectional view depicting the components of Fig 1 during an assembly piocedure in accordance with one embodiment of the invention

Figure 3 is a diagrammatic sectional view depicting components m accordance with a further embodiment of the invention

Figure 4 is a diagrammatic sectional view depicting the components of Fig 3 m conjunction with another element during a later step of the process Figure 5 is a diagrammatic top plan view depicting a component m accordance with yet another embodiment of the invention

Figuie 6 is a diagrammatic sectional view taken along line 6-6 m Fig 5

Figure 7 is a view similar to Fig 6 but depicting the component m conjunction with another element during a later stage of a manufactuπng process Figure 8 is a fragmentary, diagrammatic sectional view depicting components in accordance with another embodiment of the invention

Figure 9 is a diagrammatic elevational view of the components shown m Fig 8

Figure 10 is a diagrammatic elevational view depicting components in accordance with a further embodiment of the invention Figure 11 is a fragmentary, partially-sectional perspective view depicting components m accordance with yet another embodiment of the invention

Figure 12 is a diagrammatic, partially-exploded view depicting certain components during a process according to a further embodiment of the invention

Figure 13 is a diagrammatic sectional view depicting components used m a further embodiment of the invention

Figure 14 is a fragmentary, diagrammatic sectional view depicting components and process equipment dunng a method according to yet another embodiment of the invention

Figure 15 is a diagrammatic elevational view depicting components and process equipment during a method according to a still further embodiment of the invention Figure 16 is a fragmentary, partially sectional elevational view depicting an assembly according to another embodiment of the invention MODES FOR CARRYING OUT THE INVENTION

A process in accordance with one embodiment of the invention utilizes a set of bodies 20 of a fust type and bodies 22 of a second type Each body 20 includes a sheet-like dielectric layer having a top surface 24 and an oppositely directed bottom surface 26 In the parti culai embodiment illustrated, each layer 20 is formed from a sheet of polyannde approximately 25-100 microns thick Each of the bodies or layers 20 has a coating or sublayer 21 of a heat- curable bonding material on its bottom surface Bonding material layei 21 may be integral w ith body or layer 20 or else may include a distinct adhesive differing in composition from the remainder of the body or layer 20 Suitable adhesives include those commonly used in manufacture of laminated flexible circuits for high-temperature service, such as polyamides, epoxies and cyanate-PTFE materials

Each layer 20 also has holes 28 extending through it, from its top surface 24 to its bottom surface 26 These holes are arranged at locations of a regular, rectilinear grid pattern having columns of holes extending in a first or x horizontal direction and having rows of holes extending in a second or y horizontal direction orthogonal to the first or x-direction The holes need not be provided at every location of the regular grid pattern For example, one hole is omitted at a location 30 withm the grid pattern Although only a few holes are depicted Fig 1 for clarity of illustration, in practice a typical layer may have tens, hundreds or thousands of holes and may have omitted holes at many locations of the regular grid patterns Desirably, each hole is less than about 60 microns in diameter, more preferably less than about 25 microns in diameter and most preferably about 12 5 microns in diameter or less The dielectric layers 20 may be solid dielectπc Alternatively, some or all of the dielectric layers in bodies 20 may incorporate conductive elements disposed m the interior of the dielectric layers For example, body 20b includes an internal electrically conducive potential plane 36 disposed between the top and bottom surfaces of the dielectric layer As shown m Fig 2, potential plane 36 is isolated from most of the holes 28 in this layer However, the potential plane 36 extends to one or a few holes 28b m layer 20b As explained below, conductive layer will form connections to a vertical via at hole 28b

Each layer 20 also includes traces 32 extending along the top surface of the layer The traces 32 on bodies 20 extend predominantly in the first or x direction, although some portions of the traces extend m other directions as well Here again, the trace pattern is greatly simplified for clarity of illustration A typical pattern of traces will include hundreds of traces

Also, traces may be broken or continuous For example, trace 32a has a break 34 at one location. At least some of the traces 32 extend over the top ends of holes 28. Stated another way, the traces extend over locations of the regular grid pattern of the holes.

The holes and traces can be formed by essentially any conventional technique used in fabrication of microelectronic circuit panels. For example, the traces can be formed by subtractive etching from a sheet of copper or other conductive metal overlying the top surface of the body by using a photoresist or other patternable masking material to control the etchant process and leave the undesired traces. Alternatively, the traces can be formed by conventional additive plating. The holes may be formed by laser ablation or chemical etching of the dielectric layer again using a photoresist or other mask. Alternatively, the dielectric layer itself may be formed from a photosensitive dielectric and the holes may be formed by selective exposure and curing of the dielectric.

Dielectric bodies 22 of the second type are essentially the same as bodies 20. Each body 22 has a top surface 23, a bottom surface 25, and a curable bonding material 27 on its bottom surface 25. Each body 22 has holes 39 extending through it. The traces or conductors 38 on layers 22 extend predominantly in the second or y horizontal direction. Spots of a high vapor pressure conductive metal 40 are disposed on the top surfaces of traces 38. Similar spots of conductive metal 42 are disposed on the top surfaces of the traces 32 of first-direction layers 20. The spots 40 and 42 are disposed in regular grid patterns with spacing in the first and second horizontal directions equal to the spacing used in the regular grid pattern of the holes. The spots of high vapor pressure conductive material are omitted from body 20a, which will form the top layer in the stack.

In an assembly process according to one embodiment of the invention, bodies 20 having leads extending in the first or x direction are stacked in alternating order with bodies 22 having traces extending in the second or y direction. The grid of conductive material spots 40 on each second-direction body 22 is aligned with the grid of holes 28 in the next higher first- direction layer 20 in the stack. For example, the grid of conductive material spots 40 on second-direction layer 22a is aligned with the grid of holes 28 in the next higher layer 20a. Similarly, the grid of conductive material spots 32 on first-direction layer 20b is aligned with the grid of holes 39 in the overlying second-direction layer 22a. The layers are disposed in a vacuum lamination apparatus having an enclosed chamber and having a pair of opposed platens inside the chamber. The chamber is flushed with an inert gas and brought to a substantial vacuum. This process is repeated to assure that the holes in all of the layers have been substantially flushed with the inert gas, and then the chamber is brought to a lower, subatmospheric pressure desirably about 200 Torr or less and more desirably about 10 Torr or less. Still lower pressures, of about 1 Torr or less can be used. During the flushing and the evacuation process, the layers may be held apart from one another by temporary spacers (not shown) to assure good communication between each of the holes and the surrounding atmosphere within the chamber. Alternatively, the flushing and the evacuation process can be perfonned before the layers are stacked on one another.

After the flushing and evacuation procedure, the layers are laminated to one another under heat and pressure applied by squeezing the layers between the platens. The bonding materials 21 and 27 on the bottom surfaces of layers 20 and 22 are activated so as to bond the layers to one another and close the holes 28 and 39 in the various layers. Thus, after the lamination step, hole 39a has a first conductive element (trace 32a on layer 20b); a second conductive element (trace 38a at the top surface of layer 22a) and a dielectric (the dielectric of layer 22a) cooperatively defining a substantially closed, sealed chamber, and has a conductive material 42 disposed within such chamber. The same arrangement is present at at least some of the other holes 39 and 28. Desirably, the joints between the layers are gas-tight, so that each hole is sealed. At this point, the atmosphere within each hole consists essentially of inert gas at a low subatmospheric type of pressure corresponding to the pressure used in the vacuum chamber during the lamination step.

After lamination, the assembly is maintained at an elevated temperature for a time sufficient to evaporate some or all of the metal in spots 40 and 42. The upper limit of the temperature used in this stage of the process should not exceed the degradation temperature of the materials constituting bodies 20. For example, typical polyamides degrade at temperatures of about 350-400 °C. Also, the pressure within the sealed chambers defined within the bodies increases with temperature. The temperature used in this stage should not be so high as to raise the pressure above the pressure prevailing on the exterior of the laminate. Thus, the internal pressure within the sealed chambers should not exceed atmospheric pressure when the assembly is maintained under normal atmospheric pressure during this stage of the process. Where the bodies include organic polymers, the degradation temperature of the polymer normally controls. The evaporated metal deposits as a coating on the interior walls of holes 28 and 39, and forms electrically conductive vias or vertical, z-direction conductors 50 extending through the various layers at the holes. The vertical conductors join the conductive elements or traces bounding the various holes and thus forms vertical conductive paths through the stacked structure. For example, one such vertical conductive path extends almost entirely through the stack, from trace 32a at the top of layer 20a downwardly through hole 28a, hole 39a and so on through other holes to trace 32c at the top of the lowermost layer 20d Where the bodies 20 and 22 incorporate internal conductive featuies extending to the holes, the conductive via lmers 50 also form connections with such internal conductive features Foi example, potential plane element 36 is electrically connected to the vertical conductor at hole 28b

The vertical conductive paths are provided selectively Thus, a vertical via oi conductiv e path through an individual layer is provided only where three conditions are met First, there must be a hole at such location, no path is formed at location 30 where a hole is omitted Second, there must be traces or conductive elements adjacent both ends of the hole For example, no trace oveihes the top end of hole 39c in layer 22c near the bottom of the stack Therefore, no vertical connection will be formed at this hole Third, the evaporable conductive material must be present withm the hole For example, at hole 39d, no conductive material is provided and hence no vertical connection will be formed Thus, the formation of vertical connections can be controlled by providing holes selectively, by providing conductive elements selectively and by providing the evaporable conductive matenal selectively, as well as by any combination of these measures Additionally, the locations and extent of vertical and honzontal conductive pads through the stacked assembly can be controlled by selective formation or interruption of the traces or conductive pads along the surfaces of the bodies For example, a break 52 a trace 38 on the top surface of layer 22a electrically isolates trace 32c on the top surface of layer 20a from trace 32d on the top surface of layer 20b Stated another way, customization of the traces on the individual layers can provide customization of vertical path formation even without selective formation of the vertical conductive themselves The use of horizontal-conductor customization to provide selectivity in vertical path formation is descπbed in greater detail in United States Patents 5,282,312 and 5,367,764 the disclosures of which are hereby incorporated by reference herein

To assure reliable connections between the conductive elements, the conductive elements should be substantially free of contaminants, particularly oxides, which may interfere with formation of a good, low resistance joint between the deposited conductive material and the conductive element or trace Where the traces are formed from a reactive metal such as copper, they will typically have an oxide layer The oxide layer can be removed by baking m a atmosphere having very low partial pressure of oxygen as, for example, by holding the bodies bearing the conductive elements m a vacuum chamber at an elevated temperature These procedures are similar to the deoxidizing procedures employed for flux-free soldeπng Alternatively or additionally, the reactive metal may be coveied with a non-ieacti e metallic surface coating such as a gold layei Typically, a gold layer is applied over a coating of nickel During the evaporation step, the assembly need not be maintained between the platens of the lamination process Thus, each assembly can be laminated in a brief heating and pressing opeiation and then transferred to an oven for the evaporation operation The assemblies can be handled in bulk m the evaporation operation, without need for any particular fixturmg other than that required to avoid mechanical damage to the exterior surfaces of the assemblies Therefore, large numbers of assemblies can be held m the evaporation operation The process therefore can achieve substantial throughput even if the dwell time m the evaporation operation is substantial Typically, dwell times from a few minutes to a few hours are sufficient to form the vertical conductors Preferably, the evaporation operation is conducted m air at atmospheric pressure or even at sup eratmo spheric pressure, so that the pressure outside of the laminate balances or exceeds the pressure developed inside the sealed chambers Alternatively, the evaporation operation can be conducted under subatmospheric pressure and m an atmosphere consisting essentially of an inert gas This assures that even if an assembly has a leakage path to a particular hole, that hole will retain its low pressure, inert gas atmosphere When this alternative is employed, the assembly may be held between platens to assure that excess internal pressure does not cause delamination In a further alternative, the bodies and conductive elements may be provided with small openings so that the interiors of the chambei s communicate with the exterior of the assembly dunng the evaporation operation In this case, the evaporation operation should be conducted with an atmosphere surrounding the exterior of the assembly under a subatmosphereic total pressure Even m this case, however, the chambers remain substantially closed, and the process is conducted without appreciable transfer of conductive matenal into the chambers from outside of the assembly, and typically without any transfer of conductive material into the chambers during the process of distributing the conductive material withm the chambers

In the process discussed above, the vertical conductors are formed m numerous layers simultaneously However, the process can be vaπed so as to form vertical conductors m different layers seriatim Thus, a first set of closed chambers can be formed by stacking a first set of parts, and the conductors can be formed m those chambers Then, one or more additional layers are added to form further chambers, and the conductor-forming steps are repeated This cycle of operations can be repeated add still more layers and form more conductors, until the desired number of layers have been added

A process accoiding to a furthei embodiment of the invention begins with a semiconductor wafer 100 having contacts 102 on a first oi front surface The wafer desirably also has passivation layer 104 overlying the front surface except at contacts 102 The wafer incorporates internal electronic devices (not shown) electrically connected to contacts 102

Contacts 102 are treated to provide a good electrical connection with the material to be evaporated in latei stages of the process and also to prevent undesired reactions between the conductive metal to be evaporated and the material of the contacts For example, the zmcated aluminum contacts may be covered with a layer of nickel followed by an over-coatmg of gold Following this procedure, a high vapor pressure conductive metal 103 is applied onto contacts 102 using a conventional deposition process such as sputteπng or evaporation Desirably, a mask is used during the sputtering or evaporation process so that the conductive material is deposited only on contacts 102 Other methods of applying the high vapor pressure metal can be employed For example, the high vapor pressure metal can be applied by depositing balls of the metal onto the contacts and melting the metal, using the same techniques as employed in application of conventional solder balls Also, the high vapor pressure metal may be applied by contacting the front face of the wafer with the metal in liquid form, using a technique similar to wave soldering The techniques taught m copendmg, commonly assigned United States Provisional Patent Application 60/123,602 the disclosure of which is hereby incorporated by reference herein for application of bonding materials such as solders can be used for application of the high vapor pressure materials In yet another alternative, a separate substrate layer beanng the high vapor pressure material may be applied over the front face of the wafer In the next stage of the process, a dielectric layer 106 is laminated over the passivation layer 104 Layer 106 has an adhesive layer 108 similar to the adhesive layers discussed above on a bottom surface and has holes 110 extending through and between its top and bottom surfaces Layer 106 also has elongated leads 112 on its top surface Each lead has a first or fixed end 114 overlying one of the holes 110 and a free or tip end 116 remote from such hole Each lead carries a bonding material 118 such as a solder, eutectic bonding alloy or the like

The tip end 116 of each lead desirably is releasably attached to the top surface of layer 106, whereas the fixed end 114 of each lead desirably is securely attached to layer 106 Lead structures suitable for this purpose are disclosed m commonly assigned United States Patent 5,518,964, 5,904,498 and m co-pending, commonly assigned international application PCT US/99/02748 and United States Patent applications 09/020,750 and 09/195,371 the disclosures of which are hereby incorporated by reference herein For example, as disclosed in the aforementioned '498 patent, the lead sections may have differing bond strengths on different portions of the top layer As set forth m certain preferred embodiments of the '518 patent and in certain preferred embodiments of the aforesaid PCT and US applications, the tip end of the lead may be connected to the supporting dielectric by a small metallic or dielectric element which can be broken or dislodged readily

Layer 106 is laminated to wafer 100 using gas flush and vacuum lamination techniques similar to those discussed above m connection with formation of the stacked assembly Thus, after lamination, the dielectric layer 106, with its cured adhesive layer 108 forms a gas-tight seal to the wafer Each hole 110 is sealed by the dielectric layer, by the fixed end 114 of the overlying conductoi 112 and by the wafer and contact 102 itself Each holes contains an inert gas atmosphere at a low subatmospheric pressure as discussed above Again, the assembly is held at an elevated temperature so as to evaporate the conductive material 103 from each contact 102 and to the mtenor of the hole 110 and thereby form a vertical connector extending between the contact and the fixed end 114 of the associated lead

After the vertical conductors have been formed so as to connect leads 112 to the contacts 102 of the wafer, the wafer is engaged with a further element 122 having pads 124 exposed on a bottom surface 126 Merely by way of example, the further element may be a single-layer or multi layer stπcture having terminals 128 exposed at the top surface 130 Pads 124 are bonded to the tip ends 116 of the leads by activating the bonding matenal 118 earned on the tip ends of the leads Typically, the bonding material is activated by engaging the components under heat and pressure After the tip ends of the leads have been bonded to the pads 124, element 122 is moved away from wafer 100 and away from dielectric layer 106 through a predetermined vertical displacement These components may also move relative to one another in a horizontal direction Movement of these components relative to one another bends the leads towards a vertically extensive disposition Dunng or after movement of the components, a flowable, curable composition is introduced between the components and cured to form a dielectric, desirably compliant layer 132 surrounding leads 122 For example, the curable matenal may be introduced under pressure between the components and may help to impel the components away from one another Techniques for performing the lead bonding and movement operations are descnbed in the aforementioned patents and publications The resulting assembly is then severed by cutting both component 122 and wafer 100 along cutting planes 134 so as to thereby form a plmahty of individual units Each unit includes one semiconductor chip or a few chips m the wafer and a portion of element 122 As described m greater detail m the aforementioned patents and publications, such a unit can be mounted on a substrate such as a printed circuit board with teπmnals 128 bonded to the substrate Leads 112 can flex and compliant layer 132 can deform so as to permit differential thermal expansion of the chip and circuit board without imposing significant stresses on the solder joints between the terminals 128 and the circuit board In other cases, the additional unit 122 itself may be a circuit board or other microelectronic device The flexible leads and compliant layer provide similar benefits in these cases The evaporation technique provides an effective, economical and reliable way of making connections between leads 112 and contacts 102 In a variant of this approach, conductive material 103 may be provided on the bottom surfaces of lead fixed ends 114, withm holes 1 10, and evaporated so as to form connections to the contacts 102 of the chip Also, bonding material 118 may be carried on pads 124 rather than on the tip ends of the leads

In a further vanant, (Figs 5-7) dielectric layer 206 has numerous generally U-shaped slots 250 extending through it and subdividing the dielectric layer into a mam region 251 and a plurality of elongated lead regions 252 Holes 210 are formed in the mam region 251 of the sheet adjacent to each lead region Elongated conductors 212 extend from the main region of the sheet onto each lead region 252 Each such conductor overlies one hole 210 and has a bonding material 218 at the tip end of the lead region, remote from the mam region The conductive, evaporable material 203 is provided on the undersides of conductors 212, withm holes 201 The adhesive layer 208 used to secure dielectπc layer 206 to the front surface of wafer 200 is a UN-degradable or other radiation degradable adhesive matenal The lamination and evaporation steps are performed in substantially m the same way as discussed above so as to form vertical conductors 220 connecting contacts 202 with conductors 212 Before, or more desirably, after the evaporation step, adhesive layer 206 is selectively degraded m regions 256 (Fig 5) encompassing the tip ends of lead regions 252 Such selective degradation may be provided, for example, by selectively applying ultraviolet light or other radiation effective to degrade layer 206 The tip ends of the leads are bonded to a further element 222 by the conductive material carried on the tip ends Here again, further element 222 and wafer 200 are moved away from one another so as to bend the leads towards a vertically extensive configuration A curable material desirably is injected around the leads dunng or after the movement step Components with lead regions, and assembly techniques for use with such components, aie disclosed m copending, commonly assigned United States Patent applications 09/140,589, filed August 26, 1998, and 09/317,675, filed May 24, 1999, the disclosures of which are hereby incorporated by reference herein Other components which include leads with polymeric layers are disclosed m United States Patents 5,915,752 and 5,536,909 the disclosures of which are hereby incorporated by reference herein, and the aforementioned PCT/US96/14965 application

As illustrated in Fig 8 and 9, the vapor phase connection method discussed above can be used to make more complex assemblies Thus, a component 300 in accordance with another embodiment of the invention incorporates numerous dielectric layers 302 and tiaces 304 extending between these dielectric layers Vertical conductors 308, desirably formed by the vapor-phase process as discussed below, extend through some or all of these layers At least some of the traces 304 and vertical conductois 308 are arranged m pairs oi sets The bottom suiface of body 300 has numerous leads 310 As best seen m Fig 8, each lead 310 includes a plurality of conductors 312 and 314, as well as a dielectric layer 316 separating the conductors from one another The conductors 312 and 314 are connected to contacts 318 and 320 of a semiconductor device 322 such as a chip or wafer The contacts 318 and 320 connected to each lead desirably are adjacent one another and may be connected to the same internal electronic device 324 disposed withm chip or wafer 322 As explained in greater detail m co-pendmg commonly assigned United States Patent Applications 09/140,589, 08/715,571 filed September 19, 1996 and 09/020,754 filed February 9, 1998 and in PCT International Publication WO 97/11588, the disclosures of which are incorporated by reference herein, the use of traces and conductors arranged in pairs or sets of plural traces or conductors provides a controlled impedance signal path For example, such a path may incorporate a signal conductor and a ground conductor extending generally parallel to one another, or may include a set of two or more signal conductors extending generally parallel to one another As discussed in detail m these applications, a circuit 324 withm the chip may be arranged to transmit or receive oppositely directed pulses on a set of adjacent contacts such as contacts 318 and 320, so that these pulses will be transmitted along the set of conductors 312 and 314 on the same lead and transmitted along juxtaposed, parallel traces such as traces 304a and 304b (Fig

8) As further described in these apphcations and publications, such an arrangement provides rapid, reliable signal transmission Also, the controlled impedance signal paths provided m this arrangement may be used to conduct signals between different elements of chip or wafer 322 l e , to conduct signals with a single chip or wafei For example, traces 304c and 304d and the associated leads 310a and 310b provide a low impedance signal path between two widely separated electronic devices withm chip 322, as well as a path for conduction to external terminals 326 Provision of a low impedance signal path in turn allows rapid propagation of signals between widely separated elements of the chip and simplifies the task of loutmg signals withm the chip The ability of the present invention to fomi connections withm small holes provides for a particularly compact assembly As best seen in Fig 8, the vertical conductors may be formed withm holes of different sizes and types For example, a vertical conductor 332 is formed withm hole 330 extending through several polymenc layers, whereas another vertical conductor is formed at the hole overlying contact 320 and extends through only the thickness of passivation layer 334 In a further variant, multiple chips are connected to a single component, such as component 300, and interconnected by the conductors and leads to fonn a multi-chip module

As seen m Fig 10, the vapor phase connection process may be used within an assembly composed entirely of bodies formed from silicon or other semiconductor mateπals Thus, a composite chip or wafer can be made by stacking chips 400, 402, and 404 Chips 400 and 404 may contain active semiconductor electronic devices 405, whereas the middle chip 402 may incorporate only insulating layers and conductors 406 Holes 408 m chip 402 may be aligned with contacts on the other chips and an evaporable conductive material may be evaporated withm the holes m substantially the same way as described above The process of evaporation may occur simultaneously with a process of fusion which binds the chips together and fuses the same into a solid unit For example, such a process may occur at a relatively high temperature and may involve the fusion of silicon or other elements at the mating surfaces Alternatively or additionally, such a fusion process may involve activation of a high- temperature adhesive or a eutectic bonding matenal

Such a process can be used to fabncate assemblies of chips where each of the chips includes active device or, alternatively, where one or more of the chips includes only conductors and passive device This is particularly useful where the production processes used to make the vaπous chips are incompatible with one another For example, traces 406 may formed from a metal such as copper, gold, platinum or other metals which are difficult to deposit m conventional semiconductor fabncation processes or which have deleterious effects on active devices when present m close proximity to the active devices The vapor phase connection process serves to unite these conductors with electronic devices 405 m chips 400 and 404 Although the conductois 406 are electrically connected to the devices 405, the conductois remain isolated from the devices so that little or no diffusion of the conductoi material into the devices occurs during fabrication or use Stated another way, the connections formed by the vapor phase connection process maintain chemical isolation Alternatively oi additionally, chips 400 and 404 may be formed by mutually incompatible processes or formed from mutually incompatible materials as, for example, where chip 400 is formed from a compound semiconductor such as a III - V compound, a II - VI compound, or other compound semiconductor and where chip 404 is formed principally fiom silicon As used m this disclosure, the term "ffl-V" compound refers to a compound of any one or more of Al, Ga, In or Tl with any of N, P, As, Sb or Bi, whereas the term "II-VI compound" refers to a compound of any one or more of Be, Mg, Ca, Sr, Ba, Zn, Cd, and Hg with one or more of O, S, Se and Te Typically, these compound semiconductors also include dopants In a further variant, the middle chip 402 is eliminated and the entire stack consists of only two chips One or both of these chips has holes and contacts aligned with the holes and the contacts on the two chips are joined to one another using an evaporable conductive matenal as described above The ability of the vapor phase conductoi forming process to provide small vias is particularly useful where these vias are to be formed withm a chip itself A further advantage of using the present connection process to assemble plural layers of semiconductor material is that it allows parallel processing of the vaπous layers For example, one or more layers (typically layers incorporating active devices) may be formed using a very fine line width, whereas another layer or layers (typically incorporating only conductors and passive devices) may be fabricated with a coarser line width This allows fabrication of the conductor layers using less expensive, more reliable and higher-yielding processes Further, the ability to fabπcate the layers separately allows for testing of the individual layers before assembly

As depicted in Fig 11, an assembly according to a further embodiment of the invention includes a dielectric layer 500 having one or more conductors 502 disposed adjacent a top surface These conductors extend predominantly m first or x direction Dielectnc element 500 has holes 504 in the form of elongated slots extending generally in the x direction beneath some portions of conductors 502 Another element such as a dielectπc layer or body 506 has conductors 508 extending predominately m a second or y direction transverse to and desirably orthogonal to the first or x direction Conductors 508 have elongated masses of conductive matenal 510 thereon In the position illustrated m Fig 11, bodies 500 and 506 are remote from one another. In a joining process, the bodies are engaged with one another in the same manner as described above and the conductive material 510 is evaporated so as to form a vertically extending conductor within each slot 504.

Use of elongated conductive elements and slots in this embodiment helps to assure that a reliable connection will be made even if one or both of the elements is slightly out of nominal positron. Thus, provided that any point on slot 504 is aligned with any region of lead 508 having the evaporable conductive material, the connection will be made. Misalignment in the first or x direction will simply move the connection slightly along the length of slot 504 and trace 502, whereas misalignment in the y direction will simply move the interconnection along the lead 508. Tolerance sensitivity can be further reduced by providing the evaporable conductive material within slot 504. In this case, so long as slot 504 intercepts some portion of lead 508, the connection will be made. As discussed above, the vapor phase connection process typically works best with relatively small holes. Thus, the minimum dimension or width w of the hole or slot 504 desirably is less than about 60 microns and more desirably 25 microns or less.

In a further variant, the chambers are formed by providing openings in adhesive layers, so that the adhesive layer itself serves as the dielectric element which cooperatively defines the chamber. Thus, the assembly shown in Fig. 12 includes several dielectric bodies 620. Each dielectric body includes traces 602 extending on its top surface and traces 604 extending on its bottom surface. Traces 602 on all bodies other than the topmost body 620a are provided with an evaporable conductive material over their entire surfaces. Adhesive layers 625 are provided on the top surfaces of the dielectric bodies other than the topmost body. These adhesive layers cover traces 602. Prior to laminating the layers, the adhesive is removed selectively to form holes 622 over traces 602 only at those locations where connections are to be formed. For example, the adhesive may be removed by laser ablation or by selective treatment with a solvent using a mask to protect areas which are not to be removed. The layers are then laminated. Adhesive layers 625 hold bodies 620 together, and insulate the traces 602 on the top of each dielectric layer from the traces 604 on the bottom surface of the next adjacent layer except at locations where holes are provided in the adhesive layers. Holes 622 in the adhesive layers form chambers between the bodies 620. The evaporable conductive material on traces 602 at holes 622 can be evaporated and deposited within these chambers to form conductive connections to the traces 604 in the same manner as discussed above. The holes formed in the adhesive layers may have any of the configurations discussed above, such as round holes or elongated slots.

In a further variant, the adhesive layers may be provided in separate, self-supporting elements, referred to herein as "interposers". Each such interposer may consist entirely of the adhesive. More typically, each interposer may include one or more sublayers such as structural reinforcements, electrically conductive elements or both, with the adhesive being disposed on opposite sides of the reinforcements. Merely by way of example, the interposers may include internal structures as shown in commonly assigned United States Patents 5,367,764 and 5,282,312, the disclosure of which is hereby incorporated by reference herein. For example, an interposer 725 depicted in Fig. 13 includes a dielectric reinforcing layer 726 and layers of adhesive 727 and 728 on oppositely-facing top and bottom surfaces of the reinforcing layer, so that the adhesive layers define the first surface 731 and second surface 733 of the interposer. Holes 730 extend through all of these layers. Bodies 740 and 742 are laminated to the first and second surfaces, respectively, of the interposer. Conductive elements 744 on body 740 and conductive elements 746 on body 740 are aligned with holes 730 and thus exposed to the holes adjacent opposite ends of each hole. The conductive elements, bodies and interposer cooperatively define chambers in substantially the same manner as discussed above. A conductive material is provided within each such chamber, also in the same manner as discussed above. For example, one or both of the conductive elements may bear the conductive material. The conductive material is evaporated within the chambers as described above, so as to form electrical conductors extending between the conductive elements associated with each hole. In a further variant, the interposers may include metallic sheets having holes therein and dielectric material coated on the metallic sheets and lining the holes as disclosed, for example, in certain embodiments of United States Patents 5,590,460 the disclosure of which is hereby incorporated by reference herein. The coating may be performed selectively so as to leave the conductive sheet uncoated in the interiors of at least some of the holes. Electrical connections to the conductive sheet will be formed when the conductive material is dispersed in such holes as discussed above with reference to hole 28b, Fig. 1.

In the processes discussed above, the conductive material is dispersed by conversion to a gaseous phase through application of heat, and deposited from the gaseous phase onto the walls of the holes so as to form the conductors. However, other methods of dispersing the conductive material within the chambers may be employed. For example, energy may be supplied to promote dispersion of the conductive material by application of an electromagnetic, acoustical or ladiant eneigy as, for example, by inductive or microwave heating 01 a irradiation of the assembly with isible or infrared light or other ladiant energy

Mechanical energy in the form of ultrasonic 01 some vibration may be applied to the assembly, with or without sepaiate heat input Such some energy may cause evaporation of the conductive material, 01 may physically disperse the conductive material withm the holes without evaporation Foi example, the applied energy may be effective to convert the conductive material to a liquid phase, and to atomize the lesultmg liquid mass, thereby forming a mist of conductive material withm each chambei Even where a mist is not formed, the applied energy may move the liquid about withm the chambers, thereby spreading the liquid withm the chambers and onto the walls of the chambers Mechanical energy also may be applied by vigorously shaking and/or tumbling the assembly In the liquid-phase spiead g processes, as well as m the evaporation processes discussed above, energy applied to the conductive material withm the chambers is effective to spread the conductive material by mechanisms which do not rely on wetting of the interior surfaces of the chambers In those embodiments where the conductive material can be spread as a liquid, evaporation of the conductive material is not essential Therefore, the conductive matenal need not be evaporable The term "dispersible conductive matenal" as used herein includes both evaporable conductive materials and materials which can be dispersed in the liquid phase by application of energy

It is not essential to apply either mechanical energy or heat to the entire assembly at the same time For example, as shown m Fig 14, an ultrasonic energy applicator 800 dnven by a conv entional ultrasonic vibration source (not shown) is swept m a direction of movement M across one surface of the assembly while the opposite surface is supported on a support 802 The applicator thus applies ultrasonic energy to various sections of the assembly seπatim, so that conductors are formed in different holes at different times In the position shown, conductors have already been formed in holes 804, conductors are being formed m holes 806, and conductors have yet to be formed in holes 808 A localized heating device or a beam of radiant energy can be swept over the assembly in the same way Also, more complex sweep patterns such as raster scanning with or without momentary dwell at locations where the energy is directed onto holes may be employed The relative motion between the energy applicator and the assembly may be imparted by motion of the assembly, by motion of the applicator, or both For example, as seen m Fig 15, heat, ultrasound or other energy may be applied through a pair of rollers 822 which cooperatively define a nip therebetw een The assembly is advanced through the nip by rotation of the rollers as indicated by arrow s R The rollers apply pressure on the surfaces of the assembly, and also apply energy to the region of the assembly which is momentarily disposed between the rollers

In the embodiments discussed above, the dispersible conductive material is piovided in the fonn of a metal and does not change composition during the process However, a conductive material may be provided withm the closed chambers by providing one oi more materials which decompose or otherwise react to yield a metal or other conductive matenal which disperses withm the chamber and deposits on the walls of the chamber The term "conductive material precursor" is used in this disclosure to refer to such materials A conductive material precursor may be provided as a single component or as multiple components which are mixed with one another withm the chambers Some conductive material precursors include , for example, metal hydπdes, metal azides and metal acetates The reaction may occur in the vapor phase or m a liquid phase

In the embodiment discussed above with reference to Figs 8 and 9, a semiconductor device such as a chip or wafer is connected to another element through leads In a further vaπant, the invention can be employed to make connections between a semiconductor device and another element without the use of leads As shown in Fig 16, a semiconductor device 900 such as a chip or wafer having a front surface 902 and contacts 904 on such front surface is mounted to a substrate 906 having contact pads 908 on a top surface 909 Device 900 is mounted to the substrate by a dielectric layer 910 having holes 912 therein The front face 902 of the semiconductor device faces toward the top surface 909 of the substrate The holes 912 are aligned with contacts 904 and pads 908 Dielectric layer 910 may include adhesives, and may be provided in any of the ways discussed above For example, the layer may be applied as a coating on the device or on the substrate, and holes 912 may be formed in registration with the contacts or pads Here again, when the parts are assembled, the holes form chambers with conductive elements exposed therein A dispersible conductive matenal or a conductive matenal precursor is provided withm each chamber, and energy is applied so as to disperse the conductive matenal or react the precursor and thereby deposit conductive matenal on the interiors of holes 912 and form conductors 914 extending between contacts 904 and pads 908

As these and other vaπations and combinations of the features discussed above can be utilized without departing from the invention, the foregoing descnption of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention as defined by the claims

Claims

1. A method of making connections in a microelectronic unit comprising:

(a) providing first and second conductive elements and a dielectric, said dielectric and said conductive elements cooperatively defining a substantially closed chamber; (b) providing a conductive material within said chamber; and

(c) dispersing said conductive material within said chamber so that said conductive material deposits on said dielectric within said chamber and said deposited conductive material connects said conductive elements to one another.

2. A method as claimed in claim 1 wherein said dispersing step includes evaporating said conductive material.

3. A method as claimed in claim 1 wherein said chamber is maintained under subatmospheric pressure during said evaporating step.

4. A method as claimed in claim 2 or claim 3 wherein said chamber contains an inert gas during said evaporating step. 5. A method as claimed in claim 3 wherein said dielectric and said conductive elements maintain said chamber under said subatmospheric pressure during said evaporating step.

6. A method as claimed in claim 3 wherein said dielectric and said conductive elements are maintained in a process fixture at subatmospheric pressure during said evaporating step.

7. A method as claimed in claim 1 wherein said dispersing step includes applying mechanical energy to spread the conductive material in a liquid phase within said chamber.

8. A method as claimed in claim 7 wherein said mechanical energy is effective to atomize the conductive material. 9. A method as claimed in claim 1 wherein said step of providing a conductive material within said chamber includes the step of providing a conductive material precursor and reacting said conductive material precursor within said chamber.

10. A method as claimed in claim 1 wherein said step of providing said first and second conductive elements and a dielectric includes providing a dielectric layer having oppositely-directed first and second surfaces and having a hole extending through the layer between said surfaces, and providing said first and second conductive elements exposed to said hole adjacent said first and second surfaces, respectively. 1 1 A method as claimed m claim 10 wherein said step of prov iding said first and second conductive elements includes providing first and second bodies bearing said first and second conductive elements and laminating said first and second bodies to said dielectric layer

12 A method as claimed m claim 10 wherein said hole has a minimum cross- sectional dimension of about 60 μm

13 A method as claimed in claim 12 wherein said minimum cross-sectional dimension is about 25 μm or less

14 A method as claimed m claim 12 wherein said hole is of circular cross-sectional shape 15 A method as claimed in claim 1 wherein said conductive matenal is provided on at least one of said conductive elements

16 A method as claimed m claim 1 wherein said conducti e elements are piovided with substantially oxide-free metallic surfaces

17 A method as claimed in claim 1 wherein said dispersing step includes applying heat to said conductive elements and dielectπc element

18 A method of forming a plurality of electrical connections compnsmg the steps of

(a) providing a first dielectnc layer having first and second surfaces and having a plurality of holes extending through the layer between said first and second surfaces, (b) providing a plurality of first conductive elements adjacent the first surface of the layer and providing a plurality of second conductive elements adjacent the second surface of the layer, said conductive elements being aligned with at least some of said holes so that at least some of said holes have first and second conductive elements aligned therewith, (c) providing a conductive matenal in at least some of the holes having first and second conductive elements aligned therewith, and

(d) dispersing said conductive material so as to form conductors interconnecting the first and second conductive elements aligned with at least some of said holes 19 A method as claimed in claim 18 wherein said step of providing first conductive elements includes providing a first body having conductive elements, said first body being juxtaposed with said dielectric layer 20 A method as claimed in claim 19 wherein said step of providing said conductive material includes the step of depositing said conductive material on said first conductive elements

21 A method as claimed m claim 20 wherein said step of depositing said conductive material includes one or more techniques selected from the group consisting of electroplating, electroless plating, sputtering, evaporation and chemical vapor deposition

22 A method as claimed in claim 19 wherein said step of providing said dielectric layer includes forming said dielectric layer in place on a surface of said first body

23 A method as claimed m claim 19 wherein said first body is a microelectronic element having contacts on a front surface, said first surface of said dielectric layer confronting said front surface

24 A method as claimed in claim 23 wherein said step of providing said dielectric layei includes applying a curable adhesive to said front surface and applying a preformed dielectric layer over said adhesive 25 A method as claimed in claim 23 wherein said second conductive elements include elongated conductors having fixed ends and free ends, said fixed ends being aligned with at least some of said holes

26 A method as claimed m claim 25 wherein said free ends of said elongated conductors are displaceable relative to dielectnc layer 27 A method as claimed m claim 26 further comprising connecting a second microelectronic element to said free ends of said elongated conductors and moving said second microelectronic element away from said dielectric layer to thereby deform the conductors

28 A method as claimed m claim 25 wherein said dielectric layer includes elongated lead regions having fixed ends and having free ends displaceable with respect to the remainder of the dielectric layer, at least some of said elongated conductors extending along said elongated lead regions, so that the free end of each such elongated conductor is disposed adjacent the free end of an associated lead region of the dielectnc layer

29 A method as claimed in claim 28 further compnsmg the step of connecting a second microelectronic element to said free ends of said elongated conductors and moving the second microelectronic element away from the first microelectronic element to thereby deform the elongated conductors and the lead regions of the dielectnc layer

30 A method as claimed in claim 18 wherein at least one of said steps of providing first conductive elements, providing second conductive elements and providing conductive material is performed selectively, so that at least one of said first and second conductive elements and said conductive material is omitted at at least some of said holes, whereby no connection is made between first and second conductive elements at such holes.

31. A method as claimed in claim 18 wherein said step of providing said conductive material is performed selectively, so that said conductive material is omitted at at least some of said holes, whereby no connection is made between first and second conductive elements at such holes.

32. A method as claimed in claim 18 wherein said step of providing said first and second conductive elements is performed by providing a first body bearing said first conductive elements and a second body bearing said second conductive elements and sealing said first and second bodies to said first dielectric layer.

33. A method as claimed in claim 32 wherein said sealing step is performed while maintaining said dielectric layer under a subatmospheric pressure.

34. A method as claimed in claim 33 wherein said step of maintaining said dielectric layer under a subatmospheric pressure includes maintaining said dielectric layer in a gas consisting essentially of one or more inert gasses at said subatmospheric pressure.

35. A method as claimed in claim 18 wherein said dispersing step includes applying heat to said conductive elements and dielectric layer so as to evaporate the conductive material.

36. A method as claimed in claim 35 further comprising the step of testing said connections and repeating said heating step if any of said connections are defective.

37. A method of making a multilayer circuit comprising the steps of:

(a) providing a stacked structure including one or more dielectric layers and plural layers of conductive elements separated from one another by said one or more dielectric layers, at least some of said conductive elements in different layers being aligned with one another at one or more sites, said one or more dielectric layers having holes extending through them between the aligned conductive elements at at least some of said sites;

(b) providing a conductive material at at least some of said sites; and

(c) dispersing said conductive material so as to spread the conductive material onto the walls of the holes in said dielectric layers to thereby form vertical connections between conductive elements at only those sites where (i) conductive elements are aligned with one another, and (ii) the dielectric layer between such conductive elements has a hole aligned with the conductive elements; and (iii) said conductive material is provided. 38 A method as claimed in claim 37 wherein said stacked structure includes a plmality of said dielectric layers and vertical conductors are formed m each of said dielectric layers

39 A method as claimed m claim 37 wherein said step of providing said holes in said dielectnc layers is performed selectively so that holes are provided at less than all of the sites having conductive elements on opposite sides of a dielectric layer

40 A method as claimed m claim 37 wherein said step of providing holes is performed so as to place said holes at at least some locations of a regular grid pattern

41 A method as claimed m claim 40 wherein said conductive elements m each said layer extend to less than all of said locations of said regular grid pattern

42 A method as claimed in claim 40 wherein said layers of conductive elements include first direction and second direction layers arranged m alternating order, the conductive elements in each said first direction layer including elongated traces extending predominantly in an first horizontal direction, the conductive elements m each said second direction layer including elongated traces extending predominantly m a second horizontal direction transverse to said first horizontal direction

43 A method as claimed in claim 43 wherein said holes in said regular grid pattern are provided at crossing points of said first direction and second direction traces

44 A method as claimed in claim 38 wherein said step of providing said stacked structure is performed in a senes of stacking operations with one or more dielectnc layers, one or more conductive layers or both being added to the stacked structure in each such operation

45 A method as claimed in claim 44 wherein said dispersing step is performed m a series of evaporating operations, at least some of said evaporatmg operations being performed before all of said stacking operations have been completed 46 A method as claimed in claim 44 wherein said dispersing step is commenced after all of said stacking operations have been completed

47 A method as claimed m claim 37 wherein said dispersing step includes evaporating said conductive matenal withm said holes

48 A method as claimed in claim 47 wherein said stacking operations include sealing said dielectnc layers to one another while maintaining the stacked structure under subatmospheric pressure to thereby seal said holes under subatmospheπc pressure

49 A method as claimed m claim 37 wherein at least some of said dielectric layers include adhesive layers

50. A component for making connections in a microelectronic assembly comprising:

(a) a dielectric layer having first and second surfaces;

(b) a plurality of elongated conductors on said first surface; and

(c) slots in said dielectric layer extending through the layer beneath said conductors, said slots extending in the direction of elongation of said conductors.

51. A component as claimed in claim 48 further comprising a dispersible conductive material disposed in said slots.