EP1476818A4 - Low-processor-load aggregation - Google Patents

Low-processor-load aggregation

Info

Publication number: EP1476818A4
Authority: EP; European Patent Office
Prior art keywords: processor; low; load aggregation; aggregation; load
Prior art date: 2002-01-22
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Withdrawn

Application number

EP03705893A

Other languages

German (de)

French (fr)

Other versions

EP1476818A1 (en

Inventor

Joel D Peshkin

Alexey E Pynko

Michael C Whitfield

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Mindspeed Technologies LLC

Original Assignee

Mindspeed Technologies LLC

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2002-01-22

Filing date

2003-01-21

Publication date

2008-05-14

2002-01-22 Priority claimed from US10/055,529 external-priority patent/US20030140168A1/en

2002-01-22 Priority claimed from US10/055,597 external-priority patent/US20030140163A1/en

2003-01-21 Application filed by Mindspeed Technologies LLC filed Critical Mindspeed Technologies LLC

2004-11-17 Publication of EP1476818A1 publication Critical patent/EP1476818A1/en

2008-05-14 Publication of EP1476818A4 publication Critical patent/EP1476818A4/en

Status Withdrawn legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/66—Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/64—Hybrid switching systems
- H04L12/6402—Hybrid switching fabrics
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/35—Network arrangements, protocols or services for addressing or naming involving non-standard use of addresses for implementing network functionalities, e.g. coding subscription information within the address or functional addressing, i.e. assigning an address to a function
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/14—Multichannel or multilink protocols

EP03705893A 2002-01-22 2003-01-21 Low-processor-load aggregation Withdrawn EP1476818A4 (en)

Applications Claiming Priority (5)

Application Number	Priority Date	Filing Date	Title
US10/055,529 US20030140168A1 (en)	2002-01-22	2002-01-22	Assigning addresses to packet-network devices and booting multi-channel devices
US10/055,597 US20030140163A1 (en)	2002-01-22	2002-01-22	Low-processor-load aggregation
US55597		2002-01-22
US55529		2002-01-22
PCT/US2003/002067 WO2003063011A1 (en)	2002-01-22	2003-01-21	Low-processor-load aggregation

Publications (2)

Publication Number	Publication Date
EP1476818A1 EP1476818A1 (en)	2004-11-17
EP1476818A4 true EP1476818A4 (en)	2008-05-14

Family

ID=27615957

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP03705893A Withdrawn EP1476818A4 (en)	2002-01-22	2003-01-21	Low-processor-load aggregation

Country Status (4)

Country	Link
EP (1)	EP1476818A4 (en)
JP (1)	JP2005516440A (en)
KR (1)	KR20040103917A (en)
WO (1)	WO2003063011A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5790546A (en) *	1994-01-28	1998-08-04	Cabletron Systems, Inc.	Method of transmitting data packets in a packet switched communications network
WO2000056024A2 (en) *	1999-03-17	2000-09-21	Broadcom Corporation	Network switch
US6278708B1 (en) *	1998-04-10	2001-08-21	Cisco Technology, Inc.	Frame relay access device with user-configurable virtual circuit bundling
US6339595B1 (en) *	1997-12-23	2002-01-15	Cisco Technology, Inc.	Peer-model support for virtual private networks with potentially overlapping addresses

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6035105A (en) *	1996-01-02	2000-03-07	Cisco Technology, Inc.	Multiple VLAN architecture system

2003
- 2003-01-21 KR KR10-2004-7011322A patent/KR20040103917A/en not_active Application Discontinuation
- 2003-01-21 JP JP2003562806A patent/JP2005516440A/en active Pending
- 2003-01-21 EP EP03705893A patent/EP1476818A4/en not_active Withdrawn
- 2003-01-21 WO PCT/US2003/002067 patent/WO2003063011A1/en active Application Filing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5790546A (en) *	1994-01-28	1998-08-04	Cabletron Systems, Inc.	Method of transmitting data packets in a packet switched communications network
US6339595B1 (en) *	1997-12-23	2002-01-15	Cisco Technology, Inc.	Peer-model support for virtual private networks with potentially overlapping addresses
US6278708B1 (en) *	1998-04-10	2001-08-21	Cisco Technology, Inc.	Frame relay access device with user-configurable virtual circuit bundling
WO2000056024A2 (en) *	1999-03-17	2000-09-21	Broadcom Corporation	Network switch

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO03063011A1 *

Also Published As

Publication number	Publication date
JP2005516440A (en)	2005-06-02
EP1476818A1 (en)	2004-11-17
WO2003063011A1 (en)	2003-07-31
KR20040103917A (en)	2004-12-09

Legal Events

Date	Code	Title	Description
2004-10-01	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text: ORIGINAL CODE: 0009012
2004-11-17	17P	Request for examination filed	Effective date: 20040817
2004-11-17	AK	Designated contracting states	Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR
2004-11-17	AX	Request for extension of the european patent	Extension state: AL LT LV MK RO
2004-12-29	RAP1	Party data changed (applicant data changed or rights of an application transferred)	Owner name: MINDSPEED TECHNOLOGIES, INC.
2005-02-16	RIN1	Information on inventor provided before grant (corrected)	Inventor name: WHITFIELD, MICHAEL, C. Inventor name: PYNKO, ALEXEY, E. Inventor name: PESHKIN, JOEL, D.
2008-05-14	A4	Supplementary search report drawn up and despatched	Effective date: 20080416
2008-05-14	RIC1	Information provided on ipc code assigned before grant	Ipc: H04L 12/56 20060101ALI20080410BHEP Ipc: H04L 12/28 20060101ALI20080410BHEP Ipc: H04L 12/12 20060101ALI20080410BHEP Ipc: G06F 15/16 20060101AFI20030807BHEP
2009-01-30	STAA	Information on the status of an ep patent application or granted ep patent	Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN
2009-03-04	18D	Application deemed to be withdrawn	Effective date: 20080717

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