EP1568041A1 - Smart verify for multi-state memories - Google Patents
Smart verify for multi-state memoriesInfo
- Publication number
- EP1568041A1 EP1568041A1 EP03787219A EP03787219A EP1568041A1 EP 1568041 A1 EP1568041 A1 EP 1568041A1 EP 03787219 A EP03787219 A EP 03787219A EP 03787219 A EP03787219 A EP 03787219A EP 1568041 A1 EP1568041 A1 EP 1568041A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- verify
- state
- programming
- subset
- storage elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
Definitions
- This invention pertains to the field of semiconductor non- volatile data storage system architectures and their methods of operation, and, in particular, relates to program verify methods.
- a number of architectures are used for non-volatile memories.
- a NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines.
- the individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: Patent Nos.
- a NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end.
- Word lines are connected to corresponding control gates of cells across multiple such different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patent application Serial No. 09/893,277, filed June 27, 2001, that is also hereby incorporated by reference, and references contained therein.
- a non-volatile memory such as flash electrically erasable and programmable read-only memories (EEPROMs)
- the write, or programming operation is typically designed to move a targeted population of storage elements progressively through a series of data states until each element reaches its desired state. This is done by incrementally changing the state of the storage elements, sensing a parameter indicative of this state in a verify process, and further changing the state of those cells that have not yet verified as being in their desired final or target state.
- V th threshold voltage
- steering voltage step e.g. staircase
- a verify operation is a sensing or read operation where the state of the storage unit is compared to its data-associated target value.
- a binary storage unit there is only one data state aside from the ground state, while the multi-state case will have additional states.
- each storage element or cell stores a total of 3 -bits or eight states.
- all cells in a write or sense group being simultaneously respectively written or read are tied to a common control, or steering, gate.
- this verify set might also proceed sequentially through the full set of steering voltage target V th levels (e.g. set of seven for eight state storage elements), associated with the corresponding set of programmable data states.
- Figure 1 illustrates the basic multi-state program/verify operation for the 8- state case in a flash type memory.
- Programming pulses which include incrementally increasing steering or control gate program voltage levels, are interlaced with a 7-step verify sequence of increasing steering gate sensing voltage levels.
- Figure 2 expands this verify series in waveform 103 (also labeled B), labeling the 7 sequentially increasing verify pulses 1, 2, 3, 4, 5, 6, and 7.
- This example shows the results of such verification for a storage element in the (charged) state (i.e. sensed threshold or V t h level) between verify levels 3 and 4, as represented by dotted line 101 (also labeled A) representing either threshold voltage directly or another parameter (e.g. a current level) indicative of this state.
- sensing strobe As represented by waveform 105 (also labeled C).
- waveform 107 The results of this strobed sensing verification is shown in waveform 107 (also labeled D). Whenever the verify level is lower than the stored charge level, this results in a "1" logic level pulse, as shown for the first three verify strobes, whereas when higher this results in a "0" logic level, as shown for the final four verify strobes.
- FIG. 3 An example of this process is illustrated in Figure 3. This is a schematic representation of which states would be checked at which stage in an exemplary programming process. This can be implemented through a look-up table maintained in the controller or other mechanism.
- the multi-states verified after a given programming pulse are indicated by a checkmark at a corresponding point on the grid. For example, after the first two programming pulses, only the lowest state above ground (e.g. the 1 state) is checked, since it is likely none of the storage elements will have advanced to the 2 state this soon. After the third pulse, a verification of the 2 state is added, since at this point there may be cells arriving at the 2 state. The 3 state is similarly added to the verification list after the fifth pulse and so on. As any cell going to the 1 state is likely to have been programmed by the seventh pulse, the 1 state verify is dropped at this point. Similarly, the 2 state is dropped at the 11th pulse and so on.
- the operation goes as follows: Cells targeted to both states 2, 3 are first programmed and locked out to the lower V th of those two higher states (i.e. state 2). This is accomplished using only a single verify-2 operation following each programming pulses, locking out further programming of both 2s and 3s as they pass that verify-2 level. Once all 2s and 3s have so locked out, the 3 s are then automatically unlocked, and the programming sequence restarted on those 3 s, but now with the single verify operation set at the verify-3 level.
- a variation begins with a 2s only verification during the concurrent programming of the 2 and 3 states.
- the 3 state's verification is added after a predetermined number of programming pulses, with the 2s verify eventually dropped out to leave only the 3 s verify from then until completion.
- Various aspects of this process are discussed more in U.S. patent number 5,920,507, which is hereby incorporated by reference.
- This approach could be extended to greater levels of multi-state storage (e.g. storing 8 states per storage element), by locking all cells targeted for a V th equal to or greater than a target V t h level (i.e. state), using a single verify at that targeted V th level. Once all cells are so locked out, the operation is repeated for the cells targeted at the next higher Vt state or beyond, repeating this loop until those cells targeted for the highest data state pass their corresponding verify target.
- V t h level i.e. state
- the starting voltage should be reduced somewhat below that optimal level, increasing the number of programming pulses further still, degrading write performance.
- This approach also re-introduces the issue of coming up with a fixed (i.e. non-intelligent/ adaptive) value (in this case for re-starting programming) which balances performance with reliable write. If pushed too aggressively in favor of increased write speed, this risks programming state overshoot, whereas if too conservative, write speed suffers.
- multi-state memories are programmed using a "smart verify” technique with a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations.
- the "smart verify” technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing "intelligent" means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence.
- the scan's low and high ends of the threshold voltage scan window can be reliably established, with minimum time wastage from extra, unneeded verify operations.
- the storage elements may be the memory cells of a flash EEPROM memory that are pulsed with a programming voltage and subsequently sensed to monitor their progress.
- the next state in the sequence of multi-states is added to the verify process. This next state can either be added immediately upon the fastest cells reaching this preceding state in the sequence or, since memories are generally designed to have several programming steps to move from state to state, after a delay of several cycles.
- the amount of delay can either be fixed or, preferably, use a parameter based implementation, allowing the amount of delay to be set according to device characteristics.
- Figure 1 is a program/verify waveform sequence showing a full 7-verify sequence alternating with a progressively higher steering program voltage.
- Figure 2 shows a full sequential 7-step verify sequence.
- Figure 3 is an illustrative example of a look-up table for which states are to be verified after a given programming pulse.
- Figure 4 is a flow chart for an exemplary embodiment of the present invention.
- Figures 5a and 5b plot the number of verify pulses applied following each programming step in a simulation of two embodiments of the present invention.
- Figure shows 6 the distribution of occurrences for the range of number-of- verify pulses used in the embodiment of Figure 5b.
- Figure 7 shows the resulting simulated threshold distributions for the programming states following lockout.
- Figure 8 shows the resulting simulated threshold distributions for the cell population not yet locked out at programming steps just prior to locking out each of the programming states.
- Figure 9 plots the number of cells still to be programmed to their corresponding verified/locked-out conditions as a function of the number of cumulative programming pulses.
- Figure 10 is a schematic of a program related verify / lockout implementation.
- Figure 11 shows a reduced sequential 7 step verify sequence illustrative of smart verify operation.
- Figure 12 is a schematic of peak verify level detection and application for establishing high voltage end of smart verify operation.
- Figure 13 is a schematic of minimum verify level detection and application for establishing low voltage end of smart verify operation.
- the various aspects of the present invention are applicable to non-volatile memory systems in general.
- the description below, as well as that in the Background, is given mainly in terms of an EEPROM Flash memory embodiment
- the particular type of storage unit used in the memory array is not a limitation to the present invention.
- the particulars of how the storage elements are read, are written, and store data do not enter in to the main aspects of the present invention and can be those of any of the various non-volatile and volatile systems which likewise us sequential verification through state conditions to perform the cell by cell verify/program terminate operation.
- the present invention uses verify-results- based dynamic adjustment of the multi-states verify range to establish a reliable, minimal time wasting multi-state write operation in sequential verification implementation.
- This provides a higher speed verify algorithm while maintaining proper write reliability for sequential sensing/verification of multi-state storage. For example, when programming multi-state storage elements from state 0 sequentially through states 1, 2, and so on, at an early stage only the 1 state will be verified. When the faster programming cells begin to verify at the 1 state, state 2 will be added to the verify state range, perhaps with a lag of a number of program/verify cycles that can be parameter based. The other states can similarly be added to the verify set as programming progresses to higher state levels.
- verify-results-based approach is to provide and use information relating to the progress of programming of the population of cells to thereby dynamically establish the appropriate and reliable span for the V th (or other parameter) scan window.
- the first piece of useful information is knowing when the fastest programming storage element or cell of the set of cells being programmed crosses the next lowest data state's (e.g. state 1) V th target of that set (i.e. following the concept of a peak V th detector). Therefore, until such crossing is detected, only a single verify pass, for this lowest level, needs to accompany each programming pulse.
- V tll detection is preferably defeated, which is to say that the full population of cells participates in the peak threshold voltage detection, independent of their corresponding targeted data states. In other words, this information must be known independent of the target state of that fastest cell.
- the data conditional verify and lockout is performed for a limited range of data states above this value (e.g. up to one verify V th step above this lowest level).
- another piece of useful information is the determination that all cells targeted for this lowest data state have in fact completed verification/lockout. Once this is known, the verify operation for that lowest state is no longer needed and can be safely eliminated.
- This strategy could then be continued as each population of cells targeted at the existing lowest state verify complete their associated verification/lockout. This provides a way of reliably eliminating time wastage for verifying the lower end of the verify range, as well as a gauge for dynamically positioning the V th window scan.
- the way to circumvent this problem completely is to provide information relating to the highest cell V th at any given time.
- This is the concept introduced above; namely means to determine when the fasted programming cell of the full cell population crosses a given V th verify level, independent of its target data (the peak V t h detector). With this means applied at any time to the highest V, h range being checked (which should span one state higher than that expected to exist in the population V t h distribution), then once such crossing is signaled, the verify V th high end is incremented to the next higher level. This means is then repeated at that new level following the next pulse.
- the upper end of that scan range is adaptively adjusted as well, based on information relating to the fastest programming cell at any time (i.e. step) in the programming sequence. More generally, the adding of higher states to the verify scan window is an independent process from removing lower state verifies as these lower states fully lockout.
- an alternative is to not add the next state to the verify set immediately upon the fasted programming state verifying at the preceding state.
- the actual lag amount can either be fixed, or in an exemplary embodiment use a parameter based implementation. The parameter can then be set according to operating conditions, device age, and other factors to improve performance while still allowing a sufficient safety margin. For the simulation example to be described below, this lag can gain an additional 10% or so in write speed without incurring unacceptable risk.
- Figure 4 is a flow chart for an exemplary embodiment of the present invention and begins with step 201, where the portion of the memory to be programmed is selected. This will be one or more of the write units appropriate to the memory structure, where the write unit is referred to here as a page. Once the storage elements to be written are selected, they typically undergo a data unconditional pre- write conditioning phase 210.
- the phase 210 is a representative erase process which may optionally include soft programming, preprogramming, erasing, soft erasing, and/or other conditioning steps (as is appropriate for the type of storage unit), to get selected storage elements ready for a data write.
- the exemplary embodiment shown here is taken to contain steps 211, 213, 215, and 217.
- Step 211 is a pre-programming process that is sometimes used wherein, prior to erase, the addressed storage elements are given non-data dependent programming by raising all their corresponding word-lines, for example, to level out storage element wear and provide a more uniform starting point for the erase.
- Step 213 is the erase process, such as those described in the cited references incorporated above, appropriate for the type of storage unit being used. A particular example is the smart erase process suitable for a flash EEPROM memory is described in U.S. patent number 5,095,344.
- Step 215 is any soft-programming or similar operations designed to put the erased storage units into a more uniform starting range for the actual write phase.
- any of the storage units fail to verify during erase (or during soft programming if it features a verify), they can be mapped out of the logical address space at step 217 and replaced by a properly operating storage units. Again, the actual steps and their execution for phase 210 will vary according to the particular memory and its requirements.
- the write phase 220 causes a series of incremental changes to the level of the parameter representing the data state of the storage element, the result of which is then checked, and as the storage elements do verify to their target data states, they get removed from the process. This process is largely as found in the prior art, but differs from the prior art in step 221.
- the actual writing begins in step 223 with a programming pulse.
- the pulse can vary in duration, voltage level, or both with each iteration of the loop 220 as is known in the art.
- Step 225 senses the state of each of the elements pulsed in the previous pulse in relation to the verify levels, over the targeted range of levels for the states to be verified, initially encompassing only the lowest programming state. At each verify level it compares the measured parameter of each element against its associated data target value.
- each of these elements is so compared over the range of verify states established for that iteration of the loop 220:
- this may include all of the possible states, or it may consist of a subset based on the number of loop iterations using a look-up table or similar implementation, as described in the Background section.
- the set of verify levels used is determined in step 221 by the verify results of the previous iteration.
- the initial verify set of states can be taken as only the lowest state or possibly even have no verifies, and can be based on a settable parameter. (Although in the present discussion the verify set is taken as a proper subset of the full set of target values, there may arise cases where the subset is coincident with the full set, particularly when the number of multi-states is small.)
- step 227 all elements that pass the verify condition with respect to their target state are locked out.
- Step 229 determines whether all of the elements being programmed have verified to their target data values. If so, the process ends at step 231; if not, the process returns to step 221. More generally, some elements may fail to program, as determined in step 229, resulting in a write error, in which case the bad elements or blocks can be mapped out.
- Step 221 determines which states to include in the next verify operation based upon the results of step 225 as well as a step 227 to the extent that the lockout condition is used for such determination. As has been described above, this is a major aspect of the present invention. Although the look-up table type of embodiment, described in the Background section with respect to Figure 3, could also determine at this stage which states to include in the next verify operation, in that case the determination would be based solely on the current iteration of the loop in the write process 220, whereas here it is based on the verify result of step 225 (and potentially step 227). Depending on the results in step 225, step 221 adds higher states to be verified, as needed.
- step 227 it removes lower state verifications as the elements being programmed to those lower states all verify and are locked out (or were determined to be bad cells and are mapped out). Once the verify set is re-established at step 221, the process again continues to step 223.
- Figures 5-9 show results of simulation of the "smart verify" process for the exemplary memory embodiment, wherein the storage unit is a memory cell storing 8 states.
- the storage unit is a memory cell storing 8 states.
- a specific example of a non-volatile memory in which this method may be implemented is described in U.S. patents 5,712,180, 6,103,573 and 6,426,893 and U.S. patent application Serial No. 09/667,344, all incorporated by reference above. Further details on an exemplary embodiment follow the discussion of the simulation.
- the "smart-verify” algorithm was simulated to move a population of 1500 8-state cells from the ground or erased (0) state to targeted program data states (1,2,3,4,5,6,7).
- all voltage levels are given in arbitrary units, with target threshold voltage "V th " levels for states 1,2,3,4,5,6,7 set at values 2,3,4,5,6,7,8, respectively.
- the starting V th distribution for the entire population was set to be a normal distribution with a one- ⁇ value of 0.22 centered at - 0.25, resulting in an initial V th spanning -1 to + l ⁇ .
- the average programming speed per programming step was set at 0.25, resulting in cells moving from one state to another in about 4 steps (and thereby allowing an entire locked out distribution for each programmed state to be confined to around that one step value).
- a spread in speeds was incorporated, which follow a normal distribution with one- ⁇ equal to 0.015 centered at the average 0.25 speed value, resulting in speeds spanning the range 0.2 to 0.3 ⁇ V th per step.
- the speed value assigned to any given cell remained unchanged. It should be noted that the assumption of a constant speed value for a given cell may not apply t all storage technologies, but in any case it is not required for the present invention to effective.
- the graph of Figure 5 a plots the number of verify (vfy) pulses or steps (303) applied to the cell population following each programming step, per the smart verify algorithm. Also shown are the minimum (Vt_min, 304) and maximum (Vt max, 305) V th S of the cell population not yet locked out, as well as the low (Vfy_lo, 301) and high (Vfy_hi, 302) verify voltage levels applied following each program step.
- the process begins with a number of pulses to bring the cells into a steady state before the threshold values begin to move up. The first few program pulses require only the lowest state verify, during which the V th distribution programs up to that verify point.
- the number of verifies increases, plateauing at around the two to three verify pulse level, and dropping back down towards the one verify condition as the last few states are programmed to their corresponding targets (with all states verified and locked-out at around program pulse number 37).
- the low and high verify limits of the sequential verify scans are adaptively adjusted (based on the all-lowest-state-cells verified/locked out condition and the peak V t detection criteria, respectively) to intelligently and reliably span the appropriate, optimal data state V th range, per the smart verify logic criteria.
- the embodiment of Figure 5a includes a delay of two program steps following the fastest programming cells' verify at the existing maximum state verified, before adding the next state to the verify set.
- the Vt_max line 305 begins to move and crosses the "Voltage' -l line of state 1 at step 6; however, only the 1 state is verified for a further two steps with the 2 state being added to the verify set at step 9, as is shown by the number of verifies (#Vfy pulses, 303) moving up to 2 at this point.
- the entire process is complete after step 37, including the initial five program steps.
- Figure 6 shows the distribution of occurrences for the range of number-of- verify pulses used in the embodiment of Figure 5b. While the 3-verify condition dominates, i.e. half of the time, the ability to drop to 2 verifies does occur about a quarter of the time, as does the need to increase to 4 verifies. On the average, around 2.7 verifies are needed per programming pulse, a figure that drops to under 2.5 for the embodiment of Figure 5 a. Assuming that the time required to perform one program operation (or step) is comparable to that for one verify operation, then, in the example of Figure 5b, the smart verify algorithm is capable of safely reducing the overall program time to 46% of the time that a full 7-step verify would require. Thus, raw programming speed roughly doubles.
- FIG. 7 gives a snapshot of the resulting simulated V th distributions ("Vt") for each of the seven programming states following their lockout, as well as the starting erased or 0-state distribution, for the embodiment of Figure 5b.
- Vt V th distributions
- Figure 8 gives a snapshot of the resulting simulated V th distributions for the cell population not yet locked out at programming steps just prior to locking out all of the cells targeted for each of the seven programming states (as well as the starting distribution following the first programming pulse). This indicates how well- behaved the programming progress is for the population of cells through the programming sequence.
- 601 represents the initial distribution.
- 603 corresponds to the distribution of cells after program pulse eight, just before all targeted state 1 cells are locked out. This includes both cells with states whose ultimate destination is the 1 -state, but not yet locked out, as well as those just passing through on their way to higher states. This explains the number of cells with levels well above that for the 1 state.
- 605 corresponds to program pulse 13, just before all state 2 cells lock out, and so on for the subsequent states.
- Figure 9 plots the number of cells still to be programmed to their corresponding verified/locked-out conditions as a function of the number of cumulative programming pulses. Superimposed are horizontal lines indicative of the number of cells which exist in the noted range of data states.
- Line 701 corresponds to the number of cells with data 1
- line 702 corresponds to the number of cells with data 2, 3, 4, 5, 6 or 7, and so on until line 707 shows the number of cells with data 7.
- the curve is flat until the cells with data 1 begin to lock out, after which it decreases fairly linearly until it flattens out as the straggling cells in the highest state finally lock out.
- the smart verify approach is effective at improving device performance while also insuring a reliable program/verify/lockout operation. It does so by providing "intelligent" means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence.
- the V t h scan low and high ends of the Vu, scan window can be reliably established, with minimum time wastage from extra, unneeded verify operations.
- the raw write performance is doubled as compared to the full seven step verify approach, with even further improvement for embodiment of Figure 5a that includes the delay before introducing the next verify state in the programming sequence to the verify set.
- These improvements can be realized in memory systems whose programming rely upon an iterative process of progressively shifting the states of a set of storage elements operating in parallel followed by verifying the results of these shifts (or attempted shifts if an element is defective) by sensing, in parallel, a parameter indicative of each element's state.
- An exemplary embodiment of an implementation for the smart verify technique is described with respect to Figures 10-13.
- This illustrative embodiment describes a schematic implementation of the smart verify operation on a 3-bit/storage element technology (i.e. 8-states with 7-verify sequence).
- the storage element or memory cell is of the type for which controlled, incrementally increasing storage levels, required for controlled multi-state writing, are achieved by incrementally increasing the steering gate voltage with each successive programming pulse.
- multi-state memory cell reading is accomplished by sequentially scanning this steering gate through a increasing progression of 7 steering gate voltage levels (corresponding to the 7 verify voltage levels used for multi-state data programming).
- Figure 10 schematically illustrates one embodiment of the program- verify and lockout circuit for an individual memory element 1001 (lockout terminating programming of that element for the remainder of that programming session).
- the structure of Figure 10 is similar to that found in the prior art for use with an embodiment such as found described in the Background section with respect to Figures 1 and 2 and is discussed here for reference when the smart verify case is discussed.
- the memory element 1001 in this example is a floating gate transistor, other forms of storage element can be used as is discussed below.
- n such memory elements being programmed in parallel (where n can typically range from hundreds to thousands), there are a corresponding n of such program- verify circuits, all working concurrently. Information emanating from these n circuits form the base for the smart verify operation.
- the circuit includes both components that are common to all n circuits, highlighted by the double lined borders (e.g. COUNTER 1009, RESET 1021 and the reference voltage Ref), as well as components that are replicated in each circuit (e.g. COMPARATOR 1011, DATA STATE TO BE WRITTEN register 1019, and various logic elements).
- each memory element, 1001 is connected to a corresponding sense amp COMPARATOR 1011, which compares the conduction level of the cell to a reference source, Ref.
- the action of this COMPARATOR 1011 is to output a "1" logic level whenever the output of SENSING PARAMETER DRIVER 1003 (e.g.
- the steering gate voltage magnitude B, 103, of Figure 2 connected to the storage element's steering gate, is less than that element's stored memory state parameter (e.g. cell V t h as exemplified by 101 in Figure 2).
- element's stored memory state parameter e.g. cell V t h as exemplified by 101 in Figure 2.
- the waveforms at nodes A, B, C, and D respectively correspond to both the outputs of elements 1001, 1003, 1005, and 1007 and the waveforms labeled as 101, 103, 105, and 107, respectively, on Figure 2.
- the COMPARATOR outputs a logic "0" level.
- the progression of the SENSING PARAMETER DRIVER 1003 waveform is controlled by the COUNTER 1009, which counts from 1 to 7, to generate the 7 sequential verify pulses at node B, as exemplified by waveform 103 of Figure 2.
- Each cell can store one of eight possible data states ⁇ 0,1,2,3,4,5,6,7 ⁇ , the specific one of which, for each cell, is loaded into a corresponding DATA STATE TO BE WRITTEN register 1019.
- State 0 is established by a data unconditional preset operation (e.g. sector erase) to all the to-be- written cells, corresponding to phase 210 in Figure 4.
- Data states 1, 2, 3, 4, 5, 6 and 7 constitute the seven programmable states, and correspond to the COUNTER 1009 related verify levels of 1, 2, 3, 4, 5, 6 and 7, respectively, which are used during program verify to establish those states.
- the storage element parameter e.g. storage cell V th
- the storage element parameter is sequentially and controllably moved through states 1, 2, 3, ... until terminated by the verify/lockout operation.
- the function of the three XNOR gates 1015a-c (corresponding to the 3-bit equivalent of the eight data states) feeding into the 4-input NAND gate 1017, all interposed between the COUNTER 1009 and the DATA STATE TO BE WRITTEN register 1019, is to trap the condition when a match occurs between the target DATA STATE TO BE WRITTEN and the instantaneous level being verified (via the SENSING PARAMETER DRIVER 1003), as governed by the COUNTER 1009 value.
- the fourth leg of the NAND comes from the COMPARATOR 1011 output, gated by a positive pulsing VERIFY STROBE circuit, 1005, which provides a time synchronized pulse of the comparator output D from the AND gate 1007, as exemplified by 107 in Figure 2.
- a positive pulsing VERIFY STROBE circuit 1005
- COMPARATOR output high (e.g. cell V th higher than verify level)
- the output of this 4-input NAND gate 1017 pulses down to a logical "0" (gated by the VERIFY STROBE 1005 pulse), remaining at logical "1" otherwise.
- the output of the 4-input NAND gate 1017 is fed into one leg (termed the set leg) of the LOCKOUT SR latch 1013 (implemented here in a cross-coupled NAND gate based latch).
- all LOCKOUT SR latches 1013 are set to a logical "0". This is accomplished by applying a RESET pulse 1021 (pulsing down to logic level "0" in this implementation, remaining at logic level” 1" otherwise) to the other leg (termed the reset leg) of all these SR latches, initializing all corresponding storage elements' LOCKOUTS to a logical "0".
- the following describes the progression of program/verify leading to lockout for a memory cell whose data state targeted is state 3, as is shown in Figure 2.
- the cell is set to data state 0 (e.g. erased), and its corresponding LOCKOUT latch 1013 is set to logic level "0" by the RESET signal 1021.
- an initial programming level e.g. steering or control gate voltage
- it receives a series of progressively increasing level programming pulses, each pulse being followed by the 7-level verify pulse sequence, as illustrated in Figure 1.
- the strobed results of this verify sequence is all 0's (i.e. no positive going pulses).
- the strobed result is a single logical "1" pulse during the level 1 verify strobe. This does not trigger the lockout condition, however, because during this time, the verify condition (i.e. COUNTER 1009 value equaling 1), does not match the targeted data state (i.e. DATA STATE TO BE WRITTEN 1019 equaling 3).
- the verify condition i.e. COUNTER 1009 value equaling 1
- the targeted data state i.e. DATA STATE TO BE WRITTEN 1019 equaling 3.
- the condition of verify state i.e. COUNTER 1009 value
- target data state i.e. COUNTER 1009 value
- Waveforms 1101, 1103, 1105, and 1107 correspond to signals 101, 103, 105, and 107 of Figure 2, and again respectively represent the signals to the cell parameter of storage element 1001 (node A), the output of sensing parameter driver 1003 (node B), the output of the verify strobe 1005 (node C), and the output of AND gate 1007 (node D of Figure 10).
- Figure 12 schematically illustrates one preferred embodiment for implementing the maximum or peak verify level when programming n memory elements in parallel. It includes an n-input OR gate 1211, with inputs 1207 coming from the corresponding D nodes of each of the n verify/lockout circuits, as represented in Figure 10 as the output of AND gate 1007. As described above, each D node will momentarily pulse to logic level "1" (strobed by the VERIFY STROBE, 1005 Figure 10), whenever the storage element state (e.g. cell V ⁇ parameter) exceeds the applied verify level (i.e. SENSING PARAMETER, the value at node B of Figure 10 and represented as 1103 on Figure 11).
- SENSING PARAMETER the value at node B of Figure 10 and represented as 1103 on Figure 11.
- the n-input OR gate 1211 will likewise pulse to logic level "1" whenever one or more of the addressed memory elements satisfies this programming level (e.g. cell V th ) requirement.
- This pulsing condition is established when the instantaneous verify level, as governed by COUNTER 1249, matches the existing value of MAX VERIFY LEVEL “COUNT” REGISTER 1233, as established by an exclusive OR circuit function implemented in the three XNORs 1251a-c, thereby allowing the pulse to pass through AND gate 1253.
- This pulse is then fed into the NEW MAX VERIFY LEVEL "COUNT” functional block 1235 to assert the peak verify level to its next available value.
- the n-input OR gate 1211 will maintain a logical "0", thereby freezing this current maximum verify level.
- the n-input OR gate 1211 will once again output a logical "1" pulse, thereby incrementing the maximum verify level to the next higher level.
- FIG. 12 An alternative implementation to the instantaneous incrementing approach is illustrated in Figure 12 in the alternative branch, emanating directly below the NEW MAX VERIFY LEVEL “COUNT” circuit block 1235, and consisting of elements 1241, 1243, 1245, and 1247.
- a program pulse counter termed PROGRAM COUNT
- PROGRAM COUNT is set to 0 via functional block 1241, and gets incremented by 1 with each successive programming pulse via functional blocks 1243 and 1245. Once this count reaches a prescribed "delay count" (e.g.
- the "delay count” value is preferably implemented through a settable parameter, as discussed previously, rather than having a fixed value.
- the "delay count” value could be monitored by a controller and dynamically changed based upon device behavior, for example in response to programming or read errors, or operating conditions, such as temperature or power supply variations.
- the peak verify level is set to that associated with the first state (i.e. MAX VERIFY LEVEL "COUNT" REGISTER 1233 is set to 1). This is allowed because the state set for all the addressed storage elements prior to this program operation is state 0 (e.g. via an erase operation), and it will take a number of programming pulses before any of these cells reach the verify level associated with this first state.
- Figure 13 schematically illustrates one preferred embodiment for implementing the minimum verify level when programming n storage elements in parallel. It depicts n circuit blocks (1301-1 to 1301-n) that operate in parallel; one block for each of the n concurrently addressed storage elements. Each said circuit block includes existing circuit portions of the corresponding n verify/lockout circuits described in Figure 10. As with Figure 10, those circuit blocks which are common to all n circuits are highlighted by the double lined borders (.e.g. the MIN VERIFY LEVEL "COUNT" REGISTER 1305).
- Each said circuit block 1301-/ (1 ⁇ i ⁇ n) contains a matching circuit (matching DATA STATE TO BE WRITTEN 1019 with ML VERIFY LEVEL), which consists of an exclusive-or circuit function, built from three XNOR 1331a-c gates feeding into a 3-input NAND gate 1333 for the exemplary 3-bit implementation.
- a matching circuit matching DATA STATE TO BE WRITTEN 1019 with ML VERIFY LEVEL
- this matching circuit to ignore the status of all storage elements whose target data do not match that associated with the current minimum verify level. In does this by outputting a logical level "1" to the lower input leg of the 2-input OR gate 1339. This is then transmitted to the n +1 input AND gate 1313, and thereby does not interfere with the decision process.
- the output of this the n+1 input AND gate 1313 is fed into a series of two functional circuit blocks.
- the first circuit block 1315 termed NEW MIN VERIFY LEVEL "COUNT"
- NEW MIN VERIFY LEVEL "COUNT” will, upon receiving a logical "1" pulse, increment the existing minimum verify level by one.
- the following block 1317 then loads this new minimum value into the MIN VERIFY LEVEL "COUNT" REGISTER 1305, for use in subsequent program/verify series. Note that if at any time there are no storage elements targeted to the data state associated with the current minimum verify level, the embodiment of Figure 13 will likewise increment this minimum verify level to that of the next higher data state for the following program/verify operations.
- the minimum verify level attempts to exceed the top of the verify range (i.e. MAXIMUM ALLOWED), then no further such increase is allowed.
- the minimum verify level then remains pinned to the top of the verify range (i.e. verify level 7 in this embodiment).
- the minimum verify level is set to that associated with the first state (i.e. MIN VERIFY LEVEL "COUNT" REGISTER 1305 is set to 1), in preparation for cells to be programmed up to this verify level.
- the number of verify pulses following each programming pulse is dynamically kept to the minimum required at any point in the programming sequence.
- MAX and MIN verify levels will be both at state 1.
- MAX will increase to stay above the fastest programming cells, independently, at some later point MIN will also increase, as all cells targeted for the prior minimum state have so programmed (and locked out).
- this continual dynamic readjustment of max and min allows the average number of verifies required to be less than half that value (e.g. ⁇ 3 verifies per program step on the average).
- the maximum verify level gets pinned to the high end limit, 7, and at some later point the minimum verify level also gets pinned to this limit. Examples of such operating behavior are shown in Figures 5a and 5b of the disclosure.
- multi-state embodiments using a charge storing device, such as floating gate EEPROM or FLASH cells, for the memory device
- a charge storing device such as floating gate EEPROM or FLASH cells
- other multi-state embodiments including magnetic and optical media, as well as volatile storage media such as multi-state DRAM.
- the various aspects of the present invention may be applied to other memory types, including, but not limited to, sub O.lum transistors, single electron transistors, organic/carbon based nano-transistors, and molecular transistors.
- NROM and MNOS cells such as those respectively described in U.S.
Abstract
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