EP1696390A2 - Method and arrangement of controlling the printing of a thermal transfer printer - Google Patents

Abstract

The method involves converting each pixel energy value into a number of binary pixel data with the same binary value by printing data control. Each binary pixel data value is output as a component of single printing impulses during a phase of a printing impulse duration of an assigned driver of a thermotransfer printing head. The component produces a printed dot lying in a column of a print image. An independent claim is also included for an arrangement for controlling printing of thermotransfer printing device.

Description

The invention relates to a method and an arrangement for controlling the printing of a thermal transfer printing apparatus, according to the preambles of claims 1 and 8. The invention is used in devices with relative movement between a thermal transfer print head and the print material, especially in franking machines, addressing machines and other mail processing equipment.
In US 4,746,234 a postage meter with a thermal transfer printing device has already been proposed, which allows a slight change of the print image information. In this case, semipermanent and variable print image information are electronically stored as print data in a memory and read out into the thermal transfer printing apparatus for printing. The print image (postage stamp image) includes a message and postal information including postage data for conveying the mail piece, for example, a postage stamp image, a postmark image with the post office delivery date and date, and an advertising stamp image.

The entire print image is microprocessor-controlled print image column wise imprinted by a single thermal transfer print head. In this case, a printing of printing columns in an orthogonal arrangement to the transport direction takes place on a moving mailpiece. The machine can thereby achieve a maximum throughput of mail of 2200 letters / hour at a print resolution of 203 dpi.

The franking machine T1000 has only a microprocessor for controlling a 30 mm wide thermal transfer print head with 240 heating elements for column-wise printing. All heating elements lie in a row, which is arranged orthogonal to the transport direction. Thermal transfer printers use for printing a uniformly wide thermal transfer ribbon, which is arranged between a surface to be printed - for example, a mail piece - and the series of heating elements. The energy of an electrical pulse is converted at the resistance of the driven heating element into heat energy, which transfers to the thermal transfer ribbon. Printing requires melting of a colored layer piece from the thermal transfer ribbon and application of the colored layer piece to the print material surface. The printing takes place only when the impinged with the pulse heating element was brought to the pressure temperature, ie a higher than the preheating temperature. When moving the thermal transfer ribbon at the same time with the mailpiece relative to the heating element and running heat energy supply a line is printed parallel to the movement or transport direction. A bar is printed orthogonal to the direction of transport in a printing nip when electrical impulses are applied simultaneously to all heating elements in the row of heating elements for a predetermined limited period of time (pulse duration). The pulse duration is subdividable into phases. Within the predetermined limited time duration (pulse duration), there exists a final phase (printing phase) in which the dots of a printing nip are printed. The last phase is preceded by further phases of control of the heating elements in order to heat the latter to the pressure temperature. The binary pixel data for Control of the heating elements of all printing columns are stored volatile in a pixel memory. At a low print resolution, the spacing of adjacent print columns is large and the binary pixel data of the print phase reflects the print image.
A long single pulse can be divided into several pulses whose pulse duration is the same and correspond to a specific heating phase. Usually several pulses are required to generate enough heat energy for melting a color layer piece under the heating element, which is printed on the surface of the mail piece as a dot (DE 38 33 746 A1).
In principle could be printed to achieve a high printing resolution in each phase, if only in good time in previous phases, the control of the heating elements to heat them up. It must also be noted that also the resistance of the adjacent heating element in the row, the energy of an electrical pulse is converted into heat energy (heat conduction problem). The heat energy is reduced by cooling when the pulse is eliminated. Due to the adjacent energy input, an increase in heat energy by heat conduction is possibly given so far that the control of certain heating elements can be exposed to their heating in one phase and yet sufficient heat energy is present, which causes melting of a paint layer piece under the heating element. Therefore, in addition to providing and outputting binary pixel data for generating or not generating an electrical pulse, a microprocessor is also concerned with controlling the power distribution depending on the pattern to be printed. The original reflection of the print image by binary pixel data is changed accordingly in the pixel memory, so that a clean print image is created. This requires extensive computation, as is known, inter alia, from DE 41 33 207 entitled "Method for controlling the supply of a thermal printing heating element".
To achieve a higher print resolution, a microprocessor with higher computing speed could be used. The issue of binary pixel data to the thermal print head would then take place more often per unit of time, in which a print good a similar piece of the transport path is moved on. At the same time, however, the storage space requirement in the pixel memory increases due to the pixel data for each additional virtual column or heating phase. A virtual column is to be understood here as a possibility of a further column in the printed image, which, however, is not visible since no dot is printed in the heating phase.
The binary pixel data for driving the heating elements when printing each printing column can be known to be encoded into image information and stored in the pixel memory in order to save storage space. From EP 578 042 B1 (US 5,608,636) a method for controlling the column-wise printing of a postage indicia is known in which encoded image information is converted into binary signals for driving printing elements prior to the respective printing process, wherein the converted variable and unchangeable image data only during of printing. In this case, the decoding of the variable print data and providing the print data for a complete column in a register by a microprocessor. Since the data for the next print column must be made available in the time between two print columns, the microprocessor's processing time is required in accordance with the proportion of the variable print data, the amount of postage throughput and the print resolution. This increases the bus load and limits the ability to print a franking stamp image faster on a franking.

The microprocessor can be relieved of pressure control hardware. From US 5,651,103 there is known in real time an apparatus and method for column-wise printing an image in which variable and fixed image data elements are interconnected and stored in a buffer for use in printing a column. The variable and fixed image data elements reside in non-volatile memory, with a portion of the fixed image data elements being compressed. The print image data are separated by a Hardware for the printing of each printing column composed of variable and invariable image data only before their printing, ie the image data for an impression are not in binary form in a memory area, but in a with EP 578 042 B1 for the T1000 disclosed methods comparable coded form. By a controller, the variable image data items in the nonvolatile memory are identified and data corresponding to the variable image data items is transferred to the hardware to download, connect and then print the variable and fixed image data items. The hardware proposed for this purpose requires a variable address register for each variable image data element. The number of variable pixels is thus limited by the number of address registers.

Since the introduction of the franking machine T1000 of the applicant Francotyp-Postalia AG & Co.KG in 1991, which in addition to the date and post fees now for the first time also allowed to change the aforementioned advertising stamp image electronically by pressing a button, the demands on their microprocessor control were constantly increasing. On the one hand, more data is processed, the more variable data is required in the print image. On the other hand, it is also necessary to produce other print images, which differ significantly in structure and content of a franking stamp image, for example, to print business cards, fees and court costs stamp images. The requirements for the print resolution dot's per inch (dpi) are constantly increasing. In this case occurs when printing a dot, the aforementioned heat conduction problem between the adjacent heating elements by the adjacent in the printed image to be printed pixel, the closer the pixels are adjacent. The aforementioned problem associated with the thermal transfer printing method increases with high printing resolution.

Modern franking machines should enable a so-called security impression, ie an impression of a special one Marking in addition to the above message. For example, a message authentication code or a signature is generated from the aforementioned message, and then a character string or a barcode is formed as a marker. If a security print is printed with such a mark, this allows a verification of the authenticity of the security print, for example in the post office or at the private carrier (US 5,953,426, US 6,041,704).

The development of the postal requirements for a security print in some countries results in a very high amount of variable print image data that has to be changed between two prints of different postage stamp images. For example, for Canada, a data matrix code of 48 x 48 pixels is to be generated and printed for each individual franking imprint.

In order to streamline postal distribution and increase counterfeit security, Deutsche Post AG introduced a new standard called FRANKIT in Germany in 2004. In some franking machines, a postal ½ inch inkjet print head with bubble jet technology is used today to increase the printing resolution, which is arranged in a cartridge and secured by special means (EP 1 132 868 A1).
An FRANKIT-capable franking machine ultimail® 60 from the applicant Francotyp-Postalia AG & Co. KG uses two modified 600 dpi inkjet printheads to produce a security imprint with 300 dpi print resolution (FIG.
From EP 1 378 820 A2 (US 6,733,194 B2) an arrangement for controlling the printing in a mail processing device is known, which has a print data control for pixel data processing during printing with a printhead and is connected via a BUS with a pixel memory. The circuit arrangement has a DMA controller, a printer controller and at least one pixel data processing unit with two latches for data string data transfer from the pixel memory, wherein two latches are alternately described with data and be read out. However, the aforementioned circuit arrangement is not suitable for controlling the printing of a thermal transfer printing apparatus. In order to create a FRANKIT-compatible franking machine with thermal transfer printing, the pressure data control would have to be changed accordingly, by which the microprocessor should be relieved. For faster printing at high print resolution, however, further coded pixel data would have to be stored column by column in the pixel memory and transferred sequentially to a printer controller for all the phases preceding the printing phase, wherein virtual columns are located in time between the print columns and contain coded pixel data which serve to preheat the heating elements. If, for example, pixel data were stored and transmitted as voltage values valid per pulse duration, this would result in a considerable memory requirement in the machine and a correspondingly high time requirement for the transmission of these data.

The object of the invention is to provide a method and an inexpensive arrangement for controlling the printing of a thermal transfer printing device on a moving printing material with a high throughput and with a high-resolution thermal transfer print head, wherein the responsible for the control of the thermal transfer printing device microprocessor should be relieved.

Despite a higher print resolution and higher transposting speed of the moving mail, access to the stored data should not create any additional load on the microprocessor. The number of variable picture elements should be almost unlimited, so that the variable printed image portion can be extensive and flexible for different postal requirements. Nevertheless, the arrangement for controlling the printing of a thermal transfer printing device should require as little memory as possible.

The object is achieved with the features of the method according to claim 1 and the features of the arrangement according to claim 8.

The method of controlling the printing of a thermal transfer printing device assumes that for printing a single dot, the maximum printing pulse duration at constant printing pulse voltage is a specific parameter for a particular thermal transfer ribbon and thermal transfer printing head system. The maximum pressure pulse duration can be specified by the manufacturer of the system or thermal transfer print head or determined empirically by the manufacturer of the thermal transfer printing device. The method is based on the idea that the preheat temperature and pressure temperature are closer to each other at higher print speeds than at low print speeds. Thus, in addition to higher speed of data processing, special accuracy and fineness of controllability of the thermal transfer printing apparatus become necessary.
According to the invention, it is therefore provided that in each case pixel energy values are converted by means of a print data controller into a number of binary pixel data of the same value corresponding to the pixel energy value, wherein each binary pixel data value, for example equal to one, proceeds in successive phases (heating phase and / or one printing phase) of a pressure pulse duration is outputted from each heating element of a thermal transfer printing head as a constituent of a single printing pulse giving a printed dot located in the printing column of the printed image. The pressure pulse duration may begin at different times for those heating elements to which a different pixel energy value is assigned, but ends for all driven heating elements of the row of heating elements at the same time. Thus, there are no printed dots that are in virtual columns. The pulse duration of the single pressure pulse is proportional to the aforementioned number of binary pixel data with the value equal to one.
At pixel energy level zero, no pulse is generated and thus no dot is printed in the printing phase. The maximum necessary pulse duration of the control of a heating element for printing a pixel (Pixel's) as a pressure point (dot) is thereby decomposed into a defined maximum number M equal phases. In this way, a subsequent phase length of said parameter is defined, which describes the duration of each phase and thus a delivered during the phase part of the amount of energy required for printing at a constant pulse height.
The amount of energy required by each individual heating element of a high-resolution thermal transfer printhead when printing a dot located in the printing nip is supplied by the printing data controller. The amount of energy required is determined in a manner known per se prior to printing in dependence on whether this heating element or adjacent heating elements are actuated by it during the printing of these printing gaps or have been activated when printing a preceding printing gap. The required amount of energy determines the necessary pulse duration of the control of a heating element for printing a pixel (pixel) as a pressure point (dot). The respectively required pulse duration is likewise divided by the defined phase length (duration) in order to determine a corresponding number of phases. This transformation allows the encoding of pixel energy values without significant loss of information. It is envisaged that the code is a binary code, for example a 4-bit per pixel quad.
Furthermore, the amount of energy of all the heating elements can be changed to the same extent before printing, the change being dependent on parameters such as the print head resistance, the printing speed and the print head temperature. The process of energy value calculation is time consuming and therefore can not be done during printing. A microprocessor is programmed by software for energy value calculation and encoding as well as providing pixel energy data. The results of the energy value calculation and encoding are cached in a pixel energy store without the need to generate pixel data for virtual columns. This memory content (pixel energy data) is then decoded by the print data control during of printing to drive the printhead to produce binary pixel data for the virtual columns and the actual printing column. It is provided that at constant pressure pulse voltage height, the pressure pulse duration corresponds to a pixel energy value A, which can be predetermined for each pixel by an associated code (quadruple) that the maximum pressure pulse duration in a predetermined maximum number M of phases of each same phase length (duration) can be divided in that a phase count B is preset to a value M-1 which corresponds to the predetermined maximum number M of phases reduced by a value 'one', that the phase count B is decremented stepwise by a value 'one' and during each phase the number of phases selectable by the phase count B, for printing dot's of a print column, successively select all pixel energy values A and compare them with the current phase count B, generating binary pixel data of value 'one' if the phase count B is smaller as the respectively selected pixel energy value is A.

After the energy value calculation and before printing, the energy values are coded, for example in 4-bits per pixel (quadruple), and stored in the pixel energy store. The codes of the pixel energy values (quadruples) are stored in the pixel energy store word by word for a predetermined number of print columns. Starting with the code (quadruple) belonging to the first pixel of a printing column, the following code (quadruple) belonging to the respectively adjacent pixel of the printing column are stored one after the other. Advantageously, the microprocessor is not additionally burdened by the provision of coded pixel data for virtual columns in the heat-up phases and the storage space requirement in the pixel energy storage is much less dependent on the number of heat-up phases before the actual printing phase.

A print data controller with pixel energy data processing for a high-resolution thermal transfer printhead is proposed, wherein at least one pixel energy data processing unit is controlled by a special controller to word-code the pixel energy values from the pixel energy store to a buffer for each print column and to generate binary pixel data for virtual columns and / or or for print columns which are serially transmitted to the shift register of the thermal transfer printhead, the pixel energy data processing unit outputting pixel data for each heater in each phase and thus providing the thermal transfer printhead for printing dots in a print image column.

In a first variant of the print data control for a thermal transfer printhead having only one serial input and a number of 360 heating elements in the row, two latches are provided in the print data control, alternately one of each of the direct memory access (DMA) latches having a number of 90 x 16 bit data words are loaded while the other is read out to transfer, in each phase, the codes (quadruples) of pixel energy data to each successive heater element in the row of 360 heaters, to a phase data processing unit for pixel energy data.
The loading and reading of the latches, which are preferably designed as dual-port RAMs, preferably takes place via separate ports of the latches. After the microprocessor initializes direct memory access (DMA) and starts printing a print image, an encoder signal e triggers the alternately load and read the print data control latches to generate the pixel data per column in the print data control. The encoder delivers a signal e with a pulse rate corresponding to the transport speed of the franking material.
The codes (quadruples) of pixel energy data for a complete print column become the print data controller for DMA printing loaded and cached there. The at least one printhead drive pixel energy data conditioning unit has an output connected to the serial data input of the thermal transfer printhead shift register.
The pixel energy data is stored in the pixel energy storage so that, in synchronism with the encoder clock, the direct memory access can perform a certain number of cycles to load the pixel energy data for the next print column into the corresponding buffer. For printing a print column, in each phase, the codes (quadruples) of pixel energy data of the same print column are sequentially read from the other of the two buffers. For the successive phases, therefore, the same codes (quadruples) are read out on pixel energy data. With each encoder clock, a column counter is incremented in the print data controller. When a preset value is reached, printing stops.
The code (quadruples) of pixel energy data read from one of the two latches reaches a first parallel data input (4-bit) of the at least one phase data processing unit for pixel energy data. The pixel energy data read out from the respective other of the two latches reaches as a code (quadruple) a second parallel data input (4-bit) of the at least one phase data processing unit for pixel energy data. The phase data conditioning unit has a multiplexer connected to both parallel data inputs, whose parallel data output (4-bit) is connected to a first parallel data input (4-bit) of an evaluator logic.
The multiplexer is controlled by a switching signal which is output from the printer controller.
A value B of a phase counter goes to a second parallel data input (4-bit) of the evaluator logic of the at least one phase data conditioning unit for pixel energy data. The parallel data output (4-bit) of the multiplexer supplies the value A. The output of the evaluator logic supplies in the value range 'zero' up to the value A equal to the maximum number M of equal phases only one level with the logical value '1' if the value A is greater than the value B. When a shift clock occurs, the respective value at the output of the evaluator logic is transferred to the shift register of the thermal transfer print head. If the output of the evaluator logic supplies a logic value '0', no associated heating element is activated.

In a second variant, the thermal transfer print head has two serial data inputs for separate shift registers. In the associated print data control two pixel energy data processing units are provided for the printhead drive, each having two latches. In contrast to the first variant, in each case the 180 codes (quadruples) of pixel energy data of one half of the printing column are alternately loaded into the respective first buffer of the two pixel energy data processing units and read from the respective second buffer memories of the two pixel energy data processing units for the printhead drive.
The output signals (SERIAL_DATA_OUT1, SERIAL_DATA_OUT2) of both phase data processing units for pixel energy data are shifted for each phase in the two shift registers of the thermal transfer print head and taken over for driving the heating elements in the driver register. Thereafter, the phase counter is decremented. If one of the outputs is logic '1', the associated heating element is activated in the subsequent phase. If it is logically '0', it will not be driven. When printing a column can thus be generated a number of different lengths of pressure pulses for each heating element.

After all the print data (360 pixels) for a first phase of a print column has been shifted with the LH edge of the shift clock to the thermal transfer print head and stored in the shift register, this data is transferred in parallel to a latch unit by a LATCH signal pulse and in the print head driver register. Thereafter, the STROBEx signals are activated and the print head drivers can drive the heating elements. The control of the heating elements then remains enabled by the STROBEx signals until the end of the last phase. During printing in each phase, the print data for the next phase is already pushed into the print head and taken over by a LATCH signal pulse at the beginning of the next phase. From this division of labor for the microprocessor and the pressure data control there are the following advantages:

The codes (quadruples) can be calculated relatively easily by the microprocessor. They also require less storage space than storing the complete print data for each phase in the pixel memory.
By this solution, pixel energy data can be stored as code (quadruples) in the pixel energy storage in an optimal order, which relieves the microprocessor in the printed image change. Data transfer via DMA also relieves the load on the microprocessor. The 4-bit coded energy values can be easily copied into common image formats and additionally allow a simple check.
The bus load of the microprocessor is reduced because only once print data per DMA print data are loaded into the buffers of the pressure data control. There is no correspondingly high time requirement for the transmission of such data for heating phases. Thus, less data is loaded into the print data controller than pushed by the latter to the thermal transfer print head.
Due to the adjustable phase length, the microprocessor is relieved, since with parameter changes (eg the temperature) only one register value of the pressure data control has to be changed and not all code (quadruples) in the pixel energy storage.
The amount of energy supplied to a heating element is determined by the pressure pulse duration. At a constant voltage level of the pressure pulse, it is proportional to the product of the number of phases and the phase duration for which the heating element is driven. The power supply of the printhead can thus be done by a low-cost standard power supply with a fixed output voltage of 24 V and must not be adjustable.

By keeping the STROBE signal active during all the pressure pulse duration determining phases and not momentarily turning it off after each phase, the heaters for printing dot's of a print column can be driven without interruption. As a result, a high printing speed can be achieved.

Figur 1,

vereinfachtes Blockschaltbild der Frankiermaschine ultimail®,

Figur 2,

Blockschaltbild zum Steuern des Druckens einer Frankiermaschine mit einer Druckdatensteuerung für einen Thermotransferdruckkopf,

Figur 3,

Detail des Blockschaltbildes nach Fig.2, mit einer Schaltungsanordnung zum Steuern einer Pixelenergiedatenaufbereitungseinheit,

Figur 4,

Detail der Schaltungsanordnung nach Fig.3, mit einer Schaltungsanordnung der Pixelenergiedatenaufbereitungseinheit,

Figur 5a,

Logiktabelle einer Bewerterlogik,

Figur 5b,

Schaltungsanordnung der Bewerterlogik,

Figur 6,

Flußplan zur Ablaufsteuerung der Druckersteuerung,

Figur 7,

Flußplan der Druckroutine für eine Druckspalte,

Figur 8,

Flußplan zur DMA-Steuerung,

Figur 9,

Flußplan zur Adressengenerierung,

Figur 10,

Flußplan zur Phasenlängengenerierung.

Advantageous developments of the invention are characterized in the subclaims or are presented in more detail below together with the description of the preferred embodiment of the invention with reference to FIGS. Show it:

FIG. 1,

simplified block diagram of the franking machine ultimail®,

FIG. 2,

Block diagram for controlling the printing of a franking machine with a print data controller for a thermal transfer print head,

FIG. 3,

Detail of the block diagram according to FIG. 2, with a circuit arrangement for controlling a pixel energy data processing unit,

FIG. 4,

Detail of the circuit arrangement according to FIG. 3, with a circuit arrangement of the pixel energy data processing unit,

FIG. 5a,

Logic table of evaluator logic,

FIG. 5b,

Circuitry of evaluator logic,

FIG. 6,

Flow chart for the flow control of the printer control,

FIG. 7,

Flow chart of the print routine for a pressure column,

FIG. 8,

Flow chart for DMA control,

FIG. 9,

Flowchart for address generation,

FIG. 10,

Flow plan for phase length generation.

FIG. 1 shows a simplified block diagram of the franking machine ultimail® as state of the art for the printing data control of a franking machine suitable for FRANKIT. At least one microprocessor 6 ', one pixel memory RAM 7', one non-volatile memory NVM 8 'and one read-only memory FLASH 9' are connected to a print data controller 4 'via an address, data and control unit via a BUS 5'. In a manner not shown, a postal security module (PSD) is also used to support the microprocessor of the mainboard.
The print data control consists of a pixel data processing unit 41 ', 42' and a special controller. The latter comprises a DMA controller 43 ', an address generator 44' and a printer controller 45 ', to which an encoder 3' is connected, which detects the Druckguttransportbewegung. The DMA controller 43 'allows access to the binary pixel data stored in the pixel memory 7' in order to provide the latter data-string-wise to the pixel data processing unit 41 ', 42'. The address generator 44 'generates addresses which are supplied to the pixel data preparation unit 41', 42 'for selecting the binary pixel data from a buffered data string and grouping in the required order. The printer controller 45 'drives the pixel data preparation unit 41', 42 'to supply the binary pixel data in groups to a drive unit 11', 12 'of the ink jet print head 1', 2 '. For this purpose, the printer controller 45 'outputs a shift clock signal to both the pixel data processing units 41', 42 'and the pen driver boards 11', 12 ', which drive the inkjet printheads 1', 2 '.

Figure 2 is a block diagram for controlling the printing of a postage meter with a print data controller for a thermal transfer print head. At least one microprocessor 6, a pixel energy storage RAM 7, a non-volatile memory NVM 8, a read-only memory FLASH 9 and a postal security module (PSD) 10 are connected to the print data controller 4 in terms of address, data and control via a BUS 5. The thermal transfer printhead 1 is connected to the print data controller 4, which assumes 16 bits of parallel data from the bus 5 in the case of a direct memory access and outputs serial binary data pixel by pixel to the thermal transfer printhead 1 on the output side. An encoder 3 is connected to the print data controller 4 to trigger the buffering of the pixel energy data and the printing of the dots of the print columns, each thermal transfer print head being operated at a shift clock frequency of about 2.5 MHz. The approximately 30 mm wide thermal transfer print head 1 is high-resolution and has an internal control electronics and a number of 360 heating elements, which are arranged in a row. A first part of 180 heating elements is driven in parallel by a first shift register 11 via a first latch unit 12 and first driver unit 13. A second part of 180 heating elements is driven in parallel by a second shift register 21 via a second latch unit 22 and second drive unit 23.
The print data controller 4 therefore has separate outputs for a first and second pixel energy data processing unit 41 and 42 and the associated controllers 43, 44, and 45. The associated controllers 43, 44, and 45 are connected to the pixel energy data conditioning units 41 and 42 via address and control lines A & S. It is provided that a printer controller 45 with a DMA controller 43, with the thermal transfer printhead 1 and with an address generator 44 and that the latter with the pixel energy data processing unit 41, 42 is connected in terms of control. The printer controller 45 is connected directly to the microprocessor 6 via the BUS 5. The DMA controller 43 is connected to the microprocessor 6 via a control line for DMA control signals DMA _ACK , DMA _REQ . The printer controller 45 is also in control communication with a sensor / motor controller 46 and an interrupt controller 47. With the sensor / motor controller 46 are on the one hand a start sensor S1, a scooter sensor S2, a flap sensor S3, an end sensor S4 and a thermistor 19 and on the other hand, a motor 2a for driving a roller, not shown for winding the consumed thermal transfer ribbon, a motor 2b for driving a counter-pressure roller for Druckgutbeförderung during printing and a motor 2c for actuating the pressure mechanism of the counter-pressure roller to press the latter by means of the printed matter to the thermal transfer printing head 1 connected. The interrupt controller 47 is connected via a control line 49 for an interrupt signal I directly to the microprocessor 6.

sowie $$\begin{array}{l}\mathrm{B}=\mathrm{B}4\cdot 2^3+\mathrm{B}3\cdot 2^2+\mathrm{B}2\cdot 2^1+\mathrm{B}1\cdot 2^0.\end{array}$$

FIG. 3 shows a detail of the block diagram according to FIG. 2, with a circuit arrangement for controlling a pixel energy data processing unit. At least the microprocessor 6, the pixel energy storage 7, the non-volatile memory 8 and the read-only memory (FLASH) 9 are connected to the address, data and control via the bus 5. The printer controller 45 is also connected to the microprocessor 6 via the BUS 5. The sensor / motor controller 46 and interrupt controller 47, which are also connected to the printer controller 45, have not been shown in detail in FIG. 3 for the sake of simplicity, but only as dashed lines. The encoder 3 is connected to the printer controller 45 for outputting an encoder signal e. The pixel energy data processing unit 42 shown, as well as the pixel energy data processing unit 41, with the thermal transfer printhead 1, DMA controller 43 for direct memory access (DMA), and circuitry in an address generator 44, printer controller 45, and a phase counter 48 in the manner described below. The pixel energy data processing units 41 and 42 have the same structure and each consist of two latches 411, 412 and 421, 422 and a phase data processing unit 413 and 423. The switching signal SO and the control signal SX are generated by the printer controller 45 and are via control lines to the - not shown - phase data processing unit 413 and connected to the phase data processing unit 423 shown. The switching signal SO is also supplied via the control line to the DMA controller 43. The latter is also connected to the printer controller 45 via control lines for DMA control signals (DMA start and DMA busy), the DMA controller 43 being supplied with the DMA start signal from the printer controller 45 and the DMA controller 43 being the DMA outputs a value of zero to the printer controller 45 to signal that the direct memory access is taking place and the DMA cycles have ended. The DMA controller 43 generates address write signals AW as well as select signals Select-2.1 and Select-2.2 for the shown latches 421 and 422 of the second pixel energy data processing unit 42 and Select-1.1 and Select-1.2 for the latches 411 and 412 of the first pixel energy data processing unit 41, not shown Storing or reading out all quadruples of a pressure column. The quadruples are binary coded pixel energy data of 4 bits each and are provided in the pixel energy storage 7 by print columns. For each print column, 360 x 4 bits = 1440 bits are stored in 90 x 16-bit data words. Although the microprocessor 6 has a 32-bit data bus, a 16-bit memory is used to reduce manufacturing costs. An internal DMA controller of the microprocessor 6 also allows the addressing of 16-bit data words. The latches 411, 412 and 421, 422 are connected to the data bus. The buffering of a print column in the direct memory access (DMA) thus requires that a buffering of each 45 _* 16-bit data words is performed in succession in two latches, the latches are selected by the selection signals. The terms "data word" and "wordwise" are to be understood in the following exemplary embodiments always a 16-bit wide data word, unless explicitly the data word width is additionally specified.
The DMA controller 43 has means for generating and outputting selection signals Sel_1.1, Sel_1.2 or Set_2.1, Sel_2.2 depending on from the switching state of the switching signal SO in order to temporarily store the quadruples in the respectively first or respectively second of the two latches 411, 421 or 412, 422. In a transmission of 180 quadruples from the respective one of the two latches to the phase data processing unit 413 or 423, the respective other latches for buffering the quadruples of a subsequent pressure column are successively also selected by the selection signals.
From the DMA controller 43, a 6-bit address write signal AW is supplied for wordwise addressing. The latter is in each case at a separate address input of the first and second latches 421 and 422. From the DMA controller 43, a first select signal Sel_2.1 for pixel energy data for the second print column half is provided and applied to a separate control input of the first pixel data latch 421 for the second printhead. From the DMA controller 43, a second select signal Sel_2.2 for pixel energy data for the second print column half is provided and applied to a separate control input of the second pixel energy data latch 422 for the second print column half.
The printer controller 45 has evaluation means for evaluating the address and control signals transmitted via bus 5, which are evaluated with regard to the occurrence of a print command and communicates with the DMA controller 43 via at least one control line.
Triggered by a print command, the printer controller 45 delivers a first control signal DMA-start to the DMA controller 43. Then, a request signal DMA _{REQ is} generated by the DMA controller 43 and sent to the microprocessor 6. The microprocessor has an internal DMA controller (not shown) which, in the case of a direct memory access, applies a specific address to the pixel energy storage (RAM) 7, thereby enabling a word-by-word transfer of quads of the pixel energy data via bus 5 to the latches. An address write signal AW is supplied to the latches by the DMA controller 43 for this purpose. Of the Microprocessor 6 can read out, for example, a 16-bit-wide data word with pixel data via DMA from pixel energy storage RAM 7 and transmit it to the print data control unit. The microprocessor 6 sends an acknowledgment signal DMA _ACK to the DMA controller 43 to synchronize the generation of the address write signal AW in the DMA controller 43 with the DMA cycle of the microprocessor 6. For each DMA cycle, a 16-bit data word with 4 quadruplets of pixel energy data is put into a buffer. Each of the four latches can provide a total of 180 x 4 bits for further data conditioning after every 45 DMA cycles. To achieve a print resolution of 360 dpi, two of the four buffers each are used for storage during the DMA cycles. In the DMA controller 43, circuit means are provided for outputting the second control signal DMA busy and for realizing at least one cycle counter for a predetermined number of 16-bit data words, the cycle counter being started by a DMA start signal.
When wordwise storing and reading of pixel energy data for the first and second printing column half, the two latches 411 and 412 or 421 and 422 alternate. The sequence in the DMA controller 43 will be explained in more detail later with reference to FIG.
A shift clock signal SCL of the printer controller 45 is connected to the thermal transfer printhead 1 and the address generator 44 via a control line. It is provided that the address generator 44 has means for generating and outputting address read signals AR. The printer controller 45 outputs an address generator start signal AG-start to the address generator 44, which is supplied with the shift clock signal SCL of the printer controller 45 to generate read addresses AR, which allows reading the quadruples from those buffers into which no Quadruples are loaded and cached.
Alternatively, the address generator 44 may be supplied with a control signal other than the shift clock signal SCL of the printer controller 45 to generate read addresses AR. For example is generated in-circuit or by an external oscillator, a clock signal having a frequency of about 20 MHz, wherein the clocking of the address generator 44, an LH edge of the circuit-internal clock signal is used, which immediately follows the LH edge of the shift clock signal SCL.
Further control lines from the printer controller 45 are provided for control signals Latch and Strobe1 and Strobe2 and connected to the corresponding control inputs of the thermal transfer print head 1.
A first phase data conditioning unit 413, not shown, has, like the second phase data conditioning unit 423 shown, two parallel data inputs F, K of 4-bit connected to the outputs of the two latches, a binary coded value A = A4, A3, A2, A1 provide. Both phase data conditioning units 413, 423 also have a second parallel data input of 4-bit for a binary coded value B = B4, B3, B2, B1 and a serial 1-bit data output D. Where: $$\begin{array}{l}\mathrm{A}=\mathrm{A}4\cdot 2^3+\mathrm{A}3\cdot 2^2+\mathrm{A}2\cdot 2^1+\mathrm{A}1\cdot 2^0\end{array}$$

such as $$\begin{array}{l}\mathrm{B}=\mathrm{<figure-callout\; id="4"\; label="B"\; filenames="imgf0001.png,imgf0002.png"\; state="\{\{state\}\}">B</figure-callout>}4\cdot 2^3+\mathrm{<figure-callout\; id="3"\; label="B"\; filenames="imgf0003.png"\; state="\{\{state\}\}">B</figure-callout>}3\cdot 2^2+\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="imgf0001.png,imgf0002.png"\; state="\{\{state\}\}">B</figure-callout>}2\cdot 2^1+\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="imgf0001.png,imgf0002.png"\; state="\{\{state\}\}">B</figure-callout>}1\cdot 2^0,\end{array}$$

The latch control signal of the printer controller 45 is connected to a count input of the phase counter 48. The phase counter 48 applies the binary coded value B = B4, B3, B2, B1 to the second 4-bit parallel data input of the phase data processing units for pixel energy data.
The function of the phase data processing units will be explained in more detail later with reference to FIGS. 4, 5a and 5b.

FIG. 4 shows a detail of the circuit arrangement according to FIG. 3, with a circuit arrangement of the pixel energy data processing unit. The first and second buffer memories 421 and 422 for pixel energy data for the second printing column half are, for example realized as dual port RAM's 4210 and 4220. The latter are selected for reading in the pixel energy data by the first or second selection signal Sel_2.1 or Sel_2.2 supplied by the DMA controller at a separate control input of the respectively first ports 4211 and 4221 of the first and second dual port RAMs 4210 or 4220 is present. During the DMA cycles, a first and a second selection signal Sel_2.1 or Sel_2.2 are alternately supplied by the DMA controller 43 for word-wise storage of pixel energy data for the second half of the printing column. At the respective first ports 4211 and 4221 is an address write signal AW when reading pixel energy data. The number of pixels desired for each print image column requires a total of 90 data words to buffer 16 bits in two out of four latches.
In the same manner-but not shown in detail-the pixel energy data for the first print column half is word-delivered via bus 5 and applied to a corresponding data input of the first and second buffer memories 411 and 412 for pixel data printed in the first print column half. The - not shown in detail in Figure 2 - first pixel energy data processing unit 41 also includes a first and second latches 411 and 412, which are each connected on the input side to the low-order 16 bits of the data bus of the bus 5. The address write signal AW supplied from the DMA controller 43 is also applied to each of a separate address input of the first and second buffer memories 411 and 412 for pixel energy data provided for the first print column half. From the DMA controller 43, a first select signal Sel_1.1 for pixel energy data for the first print column half is provided and applied to a separate control input of the first pixel energy data latch 411 for the first print column half. From the DMA controller 43, a second select signal Sel_1.2 for pixel energy data for the first print column half is provided for a subsequent print column and is applied to a separate control input of the second pixel energy data latch 412 which is the first print column half subsequent printing gaps are provided. The previously read pixel energy data are then read out, for example, from the first and second dual port RAM 4210 and 4220, respectively. For this purpose, an address read signal AR, which is supplied by the address generator 44, is applied to the second port 4212 or 4222. The following describes how the readout pixel energy data is further processed.
The first pixel energy data processing unit 41 of the first printing column half (not shown in detail in FIG. 2) has the same structure as the second pixel energy data processing unit 42 of the second printing column half shown in FIG.
Also, the address read signal AR supplied from the address generator 44 is again applied to a separate address input of the first and second latches 421 and 422 of the second pixel energy data processing unit 42 for pixel energy data of the second print column half. The parallel data outputs of the first and second pixel energy data latches 421 and 422 are applied to first and second inputs of a second phase data processing unit 423 for pixel energy data.
One half of the printed image is printed by half of the heating element row of the print head. The internal printhead electronics for each half of the heating element series is also constructed in a similar way.
Since the printer controller 45 has means for generating and outputting the switching signal SO, which drives the phase data processing unit 423, the pixel energy data can be selected from the output of the respective first or second of the two latches 421 and 422 for further data processing. The phase data processing unit 423 has on the input side four switches 4231, 4232, 4233 and 4234 for the parallel data inputs and an evaluator logic 4235 with an output-side switch 4236. The printer controller 45 controls via the switching signal SO, the four input-side switch 4231, 4232, 4233 and 4234 and the control signal SX the output side switch 4236th Die Switching by the switch 4231 takes place between the terminals H1 and K1 to an output P1. The other switches 4232, 4233 and 4234 and 4236 are preferably constructed in the same way. The switches can be realized for example by logic gates.
Alternatively, a 4-bit multiplexer Mux 2 is used for the input-side switch and controlled by the switching signal SO, which is output from the printer controller 45 and also applied to a control input of the DMA controller (Figure 3).
The phase counter 48 is incremented by the LH edge of the latch signal and is preferably constructed as a down counter and preset to a count. The binary output B supplying parallel output of the phase counter 48 and the binary value A supplying parallel output of the 4-bit multiplexer Mux 2 (or alternatively: the outputs of the input side switch or gate) are connected to two parallel data inputs of the evaluation logic 4235. The serial output X of the evaluator logic 4235 is connected to the first input F6 and a (ground) potential having the value 'zero' is connected to the second input K6 of the output side switch 4236, the binary value D = '1 at its output P6 'outputs when a pulse is to be printed and the control signal SX =' 1 '. After the initialization of the FPGA and the first direct memory access DMA no pulse is yet to be printed and the control signal is therefore SX = '0'.
The sequence control of the printer control will be explained in more detail below with reference to FIG.
The entire print data control can preferably be realized with an application specific circuit (ASIC) or programmable logic, such as Spartan II 2.5V FPGA from XILINX ( www.xilinx.com ).

• Bei A > B sei C = 1 und bei A ≤ M sei Y = 1,
• bei A ≤B sei C = 0 und bei A > M sei Y = 0
• sowie C · Y = X.

Figure 5a shows the logic table of evaluator logic 4235. The quads for values A of the pixel energy data are shown as rows and the values B of the phase counter are shown as columns of the table in which the assignment of a binary value can be seen, which is output at the output X of the evaluator logic. The binary value '1' denotes a pulse during one phase. Thus, the table in FIG. 5a also shows the contribution of successive phases to the pulse duration for the control of the heating elements. The data of the table are preferably stored in a memory formed in the FPGA. For example, such assignment of the quadruples for values A of the pixel energy data and the values B of the phase counter for the value X output by an evaluator logic with a (programmable) read-only memory can be realized from the table. In the table, for example, the maximum number M of phases of equal size is defined as M = 10. From the table, the value for the value A = 0 and for all values A of the pixel energy greater than M the value X = 0 is output. From the table, the value X = 0 is also output for all count values B of the backward counter greater than or equal to the value A of the pixel energy but the value X = 1 for all count values B of the backward counter smaller than the value A of the pixel energy. Consequently:

• For A> B let C = 1 and for A ≤ M let Y = 1,
• for A ≤B let C = 0 and for A> M let Y = 0
• and C x Y = X.

Alternatively, logic built up from logic gates may also be used which satisfies the aforementioned conditions. Figure 5b shows a circuitry of evaluator logic 4235 constructed of NAND logic gates. The gates G1 to G4 logically negate the binary coded values B4, B3, B2, B1, which is subsequently illustrated by the symbol N () or N []. The respective downstream gates G9, G5, G11 and G17 combine the logically negated values N (B4), N (B3), N (B2), N (B1) with the values A4, A3, A2, A1 according to a logical function N. [Ai · N (Bj)] with i = 1, 2, 3, 4 and j = 1, 2, 3, 4. For all values Ai> Bj, a value results at the output of the gates G9, G5, G11 and G17 '0'. For all values Ai <Bj results at the output of the gates G9, G5, G11 and G17 a value '1'. The gates G5, G6, G7 and G8, the gates G11, G12, G13 and G14 and the gates G17, G18, G19 and G20 are connected as exclusive-or and have values Ai and N (Bj) at i = j> 2 thus the function Ai XOR N (Bj). For A4 = B4 or A3 = B3, a value of '1' results at the output of the gates G20 or G14. The circuits for the evaluation of the values A3, B3 and A4, B4 each form an identically constructed stage, and the circuit arrangement of the evaluator logic 4235 is in principle expandable by such stages.
For A1 = B1, a value of '1' also results at the output of the gate G9. The gate G9 has a double function and forms with the downstream gate G10 a gate controlled by the gate G8 which is open for values A2 = B2 and applies the output side value of the gate G9 to an input of the gate G10. The gates G15 and G21 have the same dual function. At A4 <B4, the gate formed by gate G21 is closed due to the value '0' output from the output of gate G20. The output C of the gate G22 outputs the value '0' because the aforementioned condition A> B for the output of a value X = 1 is not given. However, a value X = 1 is needed to form the pulse required for driving the heating elements. For A4 = B4, a value of '1' results at the output of gate G20, and the gate formed by gate 20 and gates G21 and G22 is open for carry from the previous stage provided at the output of gate 16. The value at the output X depends on the value of the carry to the output C. The following applies: $$\mathrm{C}\cdot \mathrm{Y}=\mathrm{X}$$

mit $$\mathrm{Q}26=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{A}3\cdot \mathrm{A}2\cdot \mathrm{A}1\right]$$

am Ausgang des Gatters G26, $$\mathrm{Q}27=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{A}3\cdot \mathrm{A}2\cdot \mathrm{N}\left(\mathrm{A}1\right)\right]$$

am Ausgang des Gatters G27, $$\mathrm{Q}28=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{A}3\cdot \mathrm{N}\left(\mathrm{A}2\right)\cdot \mathrm{A}1\right]$$

am Ausgang des Gatters G28, $$\mathrm{Q}29=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{N}\left(\mathrm{A}3\right)\cdot \mathrm{N}\left(\mathrm{A}2\right)\cdot \mathrm{A}1\right]$$

am Ausgang des Gatters G29, $$\mathrm{Q}30=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{N}\left(\mathrm{A}3\right)\cdot \mathrm{A}2\cdot \mathrm{A}1\right]$$

am Ausgang des Gatters G30.The circuit part with the gates G1 to G21 outputs the value C = 1 at the output C for all count values B of the backward counter, which are smaller than the value A of the pixel energy.
The circuit part with the gates G23 to G32 outputs the value X = 0 at the output Y for all values A of the pixel energy greater than or equal to M. When using a 16 bit backward counter as a phase counter 28 is from the binary values A4, A3, A2, A1 by means of the gate G30 the value A = 11, by means of the gate G29 the value A = 12, by means of the gate G28 the value A = 13, by means of the gate G27 the value A = 14 and by of the gate G26, the value A = 15 determined by the respective NAND gate output assumes the value = 0. The interconnection of the NAND gates 26 to 31 form logically an OR gate which assumes the value = 1 at the output if the conditions apply that the energy values A ≥ M = 10 were transmitted. By negating the output value of the gate G31 by means of the gate G32, a NOR function and thus the value Y = 0 is achieved. Where: $$\mathrm{Y}=\mathrm{Q}26\cdot \mathrm{Q}27\cdot \mathrm{Q}28\cdot \mathrm{Q}29\cdot \mathrm{Q}30$$

With $$\mathrm{Q}26=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{A}3\cdot \mathrm{A}2\cdot \mathrm{A}1\right]$$

at the exit of the gate G26, $$\mathrm{Q}27=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{A}3\cdot \mathrm{A}2\cdot \mathrm{N}\left(\mathrm{A}1\right)\right]$$

at the exit of the gate G27, $$\mathrm{Q}28=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{A}3\cdot \mathrm{N}\left(\mathrm{A}2\right)\cdot \mathrm{A}1\right]$$

at the exit of the gate G28, $$\mathrm{Q}29=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{N}\left(\mathrm{A}3\right)\cdot \mathrm{N}\left(\mathrm{A}2\right)\cdot \mathrm{A}1\right]$$

at the exit of the gate G29, $$\mathrm{Q}30=\mathrm{N}\left[\mathrm{A}4\cdot \mathrm{N}\left(\mathrm{A}3\right)\cdot \mathrm{A}2\cdot \mathrm{A}1\right]$$

at the output of the gate G30.

The function Y can in principle also be extended with further gates for a further digit of the binary coded number for pixel energy data. The construction by means of NAND gates shown serves only as an embodiment and is not intended to preclude a structure with NOR or other logic gates.

FIG. 6 shows a flow chart for the flow control of the printer controller. After switching on and starting in step 101, a step 102 is reached and in routine 100 of the sequence control all selection signals Sel_1.1, Sel_1.2, Sel_2.1, Set_2.2 are set to the value 'zero'. In a first query step 103, a data word transmitted via the bus is evaluated with regard to the occurrence of a command for printing start. If the latter has not yet been issued, then it branches into a waiting loop. On the other hand, after the Start printing in a step 104 setting the column count V to the value 'zero'. The switching signal SO is set to the value 'one' and output. In a second interrogation step 105, the encoder signal e is now evaluated with regard to the occurrence of an LH edge. If the latter has not yet occurred, a branch is made to a waiting loop. On the other hand, in a step 106, a signal DMA start is output and a subroutine 300 is started, which sets certain selection signals Sel_1.1, Sel_1.2, Sel_2.1 or Sel_2.2 to the value 'one' to the binary pixel energy data from the RAM 7 in the latches of the pixel data processing units 41 and 42, which will be explained in more detail later with reference to FIG.
In a step 107, a control signal SX is output by the printer controller and a subroutine for generating and outputting 180 shift clocks SCL is started. In a third interrogation step 108, the DMA-busy signal is now evaluated as to whether it has been set to the value 'zero'. If the latter is not yet the case, then it branches into a waiting loop. However, if the DMA-busy signal has been set to the value 'zero', then a fourth interrogation step 109 is reached, in which the encoder signal is evaluated with regard to the occurrence of an LH edge. If the latter has not yet occurred, a branch is made to a waiting loop. On the other hand, in a step 110, the switching signal SO is logically negated, the control signal SX: = 1 is set and output. Subsequently, in step 111, a DMA start signal is output and DMA control is enabled to restart the aforementioned subroutine 300 (FIG. 8). For subroutine 300, further subroutines in the FPGA can run parallel to one another. Now, in step 112, a column pressure subroutine 500 is started (Fig. 7). When the column pressure subroutine 500 is finished, a column-busy signal = 0 is output. In a fifth query step 113, a query is made as to whether a signal Column busy = 0 has been output and whether the DMA busy signal has been set to the value 'Zero'. If the former or the latter is still not the case, then a branch is made in a waiting loop. Otherwise, a step 114 is reached in which the column count is incremented at the occurrence of the LH edge of the encoder clock V: = V + 1.

In a sixth query step 115, it is evaluated whether the column count value V has reached a limit value U. When a predetermined limit value U is reached, the printing of the printed image, preferably a franking imprint, is ended. If this is not the case, then the fourth query step 109 is branched. Otherwise, the first interrogation step 103 is branched and the routine starts again as soon as a print start command is detected in the first interrogation step 103.

FIG. 7 shows a flow chart of the pressure column for a pressure column. The latter is called as a column pressure subroutine 500 in the course of routine 100 of the scheduler to serially write all pixel data of a column into the shift registers of the thermal transfer printhead and generate latch pulses.
After the start in step 501, a step 502 is reached in which a signal Column-busy: = 1 is set and a latch pulse is generated. This causes a transfer of pixel data initially, for example, with the value 'zero' in the control signal SX: = O has been loaded into the respective shift register 11, 12 of the thermal transfer printhead 1, in its respective latch unit 12, 22 and providing its respective Driver unit 13, 23. Then, in step 503, the pressure signals Strobe1: = 0 and Strobe2: = 0 are generated and output to the driver units 13, 23.
Subsequently, in step 504, the pasal counter 48 is preset to the value M-1, ie, phase_counter: = "" 1001. "In step 505, the printer controller 45 outputs the address generator start signal AG-start to start the subroutine 400. The details of the address generation 9, a phase length counter or a subroutine 200 for phase length generation is then started in the next step 506. The phase length counter is embodied, for example, as a presettable downwards counter The details of the subroutine 200 for phase length generation are explained in more detail below with reference to FIG.

Then, in the next step 507, generation and output of 180 shift clock pulses SCL from the printer controller 45 are performed. The shift clock SCL is generated to advance, via the serial data output D, all the pixel data for the row of heaters to the shift register. Subsequently, in the interrogation step 508, the phase length counter is queried as to whether its value PLC = 0. If this is not the case, then branching back to the beginning of step 508. Otherwise, a latch pulse is generated in step 509. The control of the heating elements remains enabled by both STROBEx signals strobe1: = 0 and strobe2: = 0 until the end of the last phase. During each phase, the print data for the next phase are pushed into the shift register of the printhead and in step 509, ie at the beginning of the next phase by a LATCH pulse in the respective latch unit 12, 22 taken.
Subsequently, in step 510, the phase counter 48 is decremented by the value '1', the following being valid for its count value: $$\mathrm{Phase\_counter}:=\mathrm{Phase\_counter}-1.$$

In the next query step 511, the count of the phase counter 48 is queried and checked whether the value Phase_counter = "1111" has already been reached, which follows the value Phase_counter = "0000" in a countdown. If the value Phase_counter = "1111" has not yet been reached, then the start of subroutine 400 is branched back to the beginning of step 505. Otherwise, a step 512 is reached, in which the signals Strobe1: = 1 and Strobe2: = 1 are generated and output to the driver units 13, 23 in order to terminate the printing of the printing column. The termination is signaled by a signal Column busy: = 0 in step 513 of the printer control. Thereafter, a stop of the subroutine 500 is made in step 514.

FIG. 8 shows a flow chart for DMA control. Such a subroutine 300 is called when a DMA start signal is output from the printer controller 45 to the DMA controller 43 (step 301). In a step 302 of the subroutine 300, a word count W is set to the Value 'zero' set. A DMA-busy signal is set to the value 'one' and transmitted to the printer controller 45. In a further step 303 of the subroutine 300, a DMA request _signal DMA _REQ having a value 'zero' is transmitted to the microprocessor 6. The latter transmits an acknowledgment signal DMA _ACK to the DMA controller 43. In a first interrogation step 304 of the subroutine 300, a non-receipt of the acknowledgment signal DMA _ACK branches to a waiting loop with a value 'zero'. From the first interrogation step 304 of the subroutine 300, on receipt of the acknowledgment signal DMA _ACK , a value 'zero' is jumped to a second interrogation step 305, the state of the switching signal SO being determined. If the switching signal SO has the state equal to one, then a branch is made to a third interrogation step 306. Otherwise, the switching signal SO has the state equal to 'zero' and a branch is made to a fourth interrogation step 309. In the third interrogation step 306, it is checked whether the word counter has a value W less than forty-five. For this case (W <45), a branch is made to a step 307. In step 307, the first selection signal Sel_1.1. for the first pixel energy data processing unit 41 of the first printing column half is switched to the value 'one' and the address writing signal AW receives the current value W of the word counter. In the subsequent step 312, the pixel data are taken over into a buffer of the pixel energy data processing units 41, 42 selected in this way. Subsequently, in step 313, all selection signals are switched to the value 'zero' and a DMA request _signal DMA _REQ with a value 'one' is transmitted to the microprocessor 6.
Then, in step 314, the word count W is incremented with the value 'one'. In a subsequent query step 315, it is checked whether the word counter has a value W smaller than ninety. For this case, in which the word counter has a value W <90, a branch back to a step 303. Otherwise, a branch is made to a step 316 to output a signal DMA busy having the value 'zero' before the end (step 317) of the subroutine 300 is reached.

Otherwise, if it is determined in the third interrogation step 306 that the word count value W is not less than forty-five, then a branch is made to a step 308, in which the first selection signal Sel_2.1. is changed to the value 'one' for the second pixel energy data processing unit 42 for the pixel energy data of the subsequent second printing column half, and the address write signal AW receives the current value W of the word counter which is reduced by the value 'forty five'. In the subsequent step 312, the pixel data are taken over again in the buffer selected in this way.
In the aforementioned fourth interrogation step 309, it is also checked whether the word counter has the value W <45, namely, if it was previously determined in the interrogation step 305, the switching signal SO does not have the state equal to one. If the word counter has the value W <45, then in step 310, the second selection signal Sel_1.2. for the first pixel energy data processing unit 41 for the pixel energy data of the first printing column half of a subsequent printing column is switched to the value of one 'and the address writing signal AW receives the current value W of the word counter. In the subsequent step 312, the pixel data are taken over again in the buffer selected in this way.
Otherwise, if the word counter does not have the value W <45, the fourth query step 309 branches to a step 311 in which the second selection signal Sel_2.2 for the second pixel energy data processing unit 42 of the pixel energy data of the subsequent second print column half of a subsequent print column the value 'one' is switched over and the address write signal AW receives the value W of the word counter which is reduced by the value 'forty-five'. In the subsequent step 312, the pixel data are taken over again in the buffer selected in this way.

Figure 9 shows a flow chart for address generation. The addresses of stored binary pixel data begin with the start address zero, which is the following for the address read signal AR is generated. After the start in step 401 of the address generator 44, an initial value is called in step 402, A: = 0 for a counter of the address read signal AR. In the subsequent step 403, the output of the address read signal AR to the latches takes place for their addressing. In the first query step 404, it is asked whether a HL edge of the shift clock signal SCL has been output to the shift registers 11, 21. If this is not the case, then a queue is branched back to the beginning of the query step 404. If so, then the query step 405 is executed, in which it is checked whether a value of the address read signal AR = 180 has been reached. If this is not the case, it is branched back via a step 406 to the beginning of step 403 for the output of the address read signal AR, which was incremented by the value 'one' in step 406. Otherwise, a branch is made to step 407 to cause the subroutine 400 to stop.

FIG. 10 shows a flow chart for phase length generation. The printer controller 45 has, for example, a down-counter that can be preset to a value PL, which causes an equal time duration for each phase when printing dot's of a column. The backward counter operates on subroutine 200 and is started in step 201. The backward counter is set to a numerical value PLC: = PL in step 202. The value PL of the phase length is provided by a register of the printer controller 45. The register value is written by the microprocessor 6 and changed accordingly when parameter changes.
The printer controller 45 is preferably part of an FPGA which has an internal clock generator or uses an external clock signal which generates a high frequency signal FPGA_CLK, for example 20 MHz. If an LH edge of the signal FPGA_CLK is detected by the backward counter in the subsequent first interrogation step 203, then in step 204 the number value PLC is decremented by the value 'one'. Otherwise, the beginning of the first interrogation step 203 is branched back into a waiting loop in order to switch to a to wait an LH flank. After decrementing in step 204, a further interrogation step 205 is reached in which the count value PLC = 0 is interrogated. The beginning of the first interrogation step 203 is branched back if the count value PLC has not yet reached the value 'zero'. Otherwise, the subroutine 200 is disabled in step 206.

The invention is applicable to both a single thermal transfer printhead having two shift registers which provide pixel data for one-half of a row of heaters, as well as a plurality of such orthogonal-aligned thermal transfer printheads to the transport direction of the print material. This requires several pixel data conditioning units and the special controller 43, 44, 45 and 48.

Of course, in an embodiment with only a single shift register in the thermal transfer printhead for an undivided array of 360 heaters, only a single pixel data processing unit 42 and special controller 43, 44, 45 and 48 are required.

Independently of all embodiments, the arrangement of pixel energy data in the pixel energy storage RAM 7 can advantageously be organized such that a change of picture elements is easily possible. The print data control for pixel data processing during printing with a printhead thus also enables a higher flexibility with regard to the requirements of different national postal authorities to a printing mail processing device.

The invention is not limited to the present embodiment. Thus, obviously other other embodiments of the invention can be developed or used, which are based on the same basic idea of the invention and are covered by the appended claims.

Claims (23)

A method of controlling the printing of a thermal transfer printing device, wherein each pixel energy values are converted by means of a pressure data control into a pixel energy value corresponding to the pixel energy value with the same binary value, wherein each binary pixel data in successive phases of a pressure pulse duration of respective heating element of a thermal transfer printhead as a part of single print pulse is output, which results in a print column of a printed image lying printed dot. Method according to Claim 1, characterized in that the pressure pulse duration is proportional to the aforementioned number of binary pixel data having the value equal to one. A method according to claims 1 and 2, characterized in that at constant pressure pulse voltage height, the pressure pulse duration corresponds to a pixel energy value A, which is predetermined for each pixel by an associated code, that the maximum pressure pulse duration in a predetermined maximum number M of phases of the same It is possible to divide the phase length such that a phase count value B is preset to a value M-1 which corresponds to the predetermined maximum number M of phases reduced by a value 'one', that the phase count value B is decremented stepwise by a value 'one' and that during For each phase of the number of phases selectable by the phase count B, for printing dots of a print column, successively select all pixel energy values A and compare them to the current phase count B, generating binary pixel data of value 'one' if the phase count B smaller than the selected Pi xenerergiewert A is. Method according to claims 1 to 3, characterized in that the code is a binary code. Method according to claims 1 to 4, characterized in that the column-wise stored pixel energy values are in each case in the form of quadruples of binary coded data and in that a sequential selection of one of all cached quadruples of the printing gaps for a particular heating element in a row of heating elements of the thermal transfer printing head by addressing during each phase a number of phases contributing to the printing of the dots of the print gaps. A method according to claims 1 to 5, characterized in that the pressure pulse duration begins at different times for those heating elements, which a different pixel energy value is assigned and that the pressure pulse duration for all controlled heating elements of the series of heating elements ends at the same time. A method according to claims 1 to 6, characterized in that a STROBE signal remains active during all the pressure pulse duration determining phases. Arrangement for controlling the printing of a thermal transfer printing device with relative movement between a thermal transfer print head and the print material, with a print data controller (4) connected to an encoder (3) and via a bus (5) with at least one microprocessor (6) and memories (8, 9 ) is address, data and control-connected, characterized in that the microprocessor (6) is programmed for energy value calculation and encoding to provide pixel energy data in the pixel energy storage (7), and that the print data controller (4) for pixel energy data processing by decoding into a Code value corresponding number of binary pixel data is formed with the same binary value during printing. Arrangement according to Claim 8, characterized in that the print data controller (4) has at least one pixel energy data processing unit (41, 42) connected to the pixel energy store (7), a DMA controller (43), an address generator (44), a printer controller (45 ) and a phase counter (48), the DMA controller (43) allowing access to the pixel energy data stored as code in the pixel energy storage means (7) to provide the latter pressure columnwise to the at least one pixel energy data processing unit (41, 42) the address generator (44) comprises address reading signal (AR) generation and output means for selecting the cached codes during each phase of a number of phases, and wherein the phase counter (48) provides a phase count to a phase data conditioning unit (413, 423) the code value A and phase count B are compared to generate binary pixel data, which is e from the output D serially fed to at least one shift register (11, 21) of the thermal transfer printhead, wherein binary pixel data with the value 'one' are generated when the phase count B is smaller than the respectively selected code value A. Arrangement according to Claim 9, characterized in that the print data controller (4) has a register for a microprocessor-adjustable register value, wherein the microprocessor only changes the register value of the print data control during parameter changes. Arrangement according to claim 10, characterized in that the register value is the phase length (PL). Arrangement according to claims 8 and 9, characterized in that the at least one pixel data processing unit (41, 42) comprises two latches (411 and 412, 421 and 422) each storing a predetermined number of successive data words with binary pixel energy data of a printing column, the DMA controller (43) and the address generator (44) are control connected to the at least one pixel energy data processing unit (41, 42) to alternately buffer the binary pixel energy data in a column-by-column manner and to provide the cached code for pixel energy data processing during printing; in that the printer controller (45) is connected to the DMA controller (43), to the address generator (44) and to the pixel data processing unit (41, 42) for generating binary pixel data at the output D. Arrangement according to claims 8 to 9 and 12, characterized in that the DMA controller (43) is connected to the microprocessor (6) and the latches (411 and 412, 421 and 422) in a manner that the DMA Control unit (43) has means for generating and outputting address write signals (AW) which, when accessing the binary pixel energy data stored in the pixel energy store (7), write them into the latches (411, 412, 421, 422) of the pixel energy data processing unit (41, 42 ) and that the DMA controller (43) has a cycle counter for a predetermined number of data words. Arrangement according to claims 8 to 9 and 12 to 13, characterized in that the printer controller (45) has means for generating and outputting a switching signal (SO) in order to drive the pixel energy data processing unit (41, 42), whereby the pixel energy data are selected with a value A from the respective first or the respective second of the two latches (411 and 421 or 412 and 422) for a comparison with a phase count value B of a phase counter (48) and that the printer control (45) is connected to the DMA controller (43) via a switching signal for the switching signal (SO) and that the DMA controller (43) comprises means for generating and outputting selection signals (Sel_1.1, Sel_1.2, Sel_2.1 , Sel_2.2) in response to the switching state of the switching signal (SO) in order to buffer the binary pixel data in the respective first or the respective second of the two latches (411 and 421 or 412 and 422), wherein in each case other latches for buffering the binary Pixel energy data of a print column are successively selected by the selection signals. Arrangement according to claims 8 to 9 and 12 to 14, characterized in that the cycle counter of the DMA controller (43) is a word counter for a predetermined number of 16 bit data words started by a DMA start signal in that the means for generating and outputting selection signals of the DMA controller (43) have at least one output means and a first and second comparison means, wherein the first comparison means in response to the SO signal drives at least one output means to reach a first predetermined number of 16-bit data words for the first pixel data processing unit (419 specific selection signal Sel_1.1 or Sel_1.2 and after reaching the first predetermined number of 16-bit data words for the second pixel data processing unit (42) specific selection signal Sel_2 .1 or Sel_2.2 output and wherein the second comparison means after reaching a second predetermined number of 16-bit data In response, a DMA-busy signal is generated with the value 'zero' and connected to a control line which is applied to the cycle counter to terminate the counting of DMA cycles. Arrangement according to claims 8 to 9 and 12 to 15, characterized in that the printer controller (45) is connected to the microprocessor (6) via the bus (5) and that the printer controller (45) has a print column counter and the encoder (3) is connected, wherein after each printed pressure column, the value (V) of the Data string counter is incremented when the encoder clock occurs and wherein the printing of a printed image is terminated when a predetermined value (U) is reached. Arrangement according to claims 8 to 9 and 12 to 16, characterized in that the printer controller (45) is connected to the DMA controller (43) directly via control lines for first DMA control signals (DMA start and DMA busy) with the DMA controller (43) being supplied with the DMA start signal from the printer controller (45) and the DMA controller (43) outputting the DMA busy signal with the value 'zero' to the printer controller (45) to signal that the direct memory access has occurred and that the printer controller (45) is connected to the address generator (44) via a control line for supplying an address generator start signal. Arrangement according to claims 8 to 9 and 12 to 17, characterized in that the DMA controller (43) is connected to the microprocessor (6) via control lines for second DMA control signals (DMA _ACK , DMA _REQ ). Arrangement according to claims 8 to 9 and 12 to 14, characterized in that the latches (421, 422 and 411, 412) are implemented as dual-port RAMs. Arrangement according to claims 8 to 9 and 12, characterized by the fact that a shift clock signal SCL is applied to the clocking of the address generator (44) and that its LH edge is used. Arrangement according to claims 8 to 9 and 12, gekennzeic characterized in that the clocking of the address generator (44) an in-circuit clock signal is applied and that its LH edge is used, which immediately follows the LH edge of the shift clock signal SCL. Arrangement according to claims 8 to 9, characterized in that the phase data conditioning unit (423, 413) has two parallel data inputs F, K, which are connected to the outputs of the two latches (421 and 422, 411 and 412, respectively) provide a binary code value A such that the phase data conditioning unit (413, 423) also has a second parallel data input for a binary coded phase count B and the serial 1-bit data output D. Arrangement according to one of claims 8 to 22, characterized in that the pressure data control (4) is implemented as an application-specific circuit or programmable logic.

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