EP1756860B1 - Method of semiconductor fabrication in corporating disposable spacer into elevated source/drain processing - Google Patents
Method of semiconductor fabrication in corporating disposable spacer into elevated source/drain processing Download PDFInfo
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- EP1756860B1 EP1756860B1 EP05735763A EP05735763A EP1756860B1 EP 1756860 B1 EP1756860 B1 EP 1756860B1 EP 05735763 A EP05735763 A EP 05735763A EP 05735763 A EP05735763 A EP 05735763A EP 1756860 B1 EP1756860 B1 EP 1756860B1
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- spacer
- drain
- gate electrode
- silicon nitride
- forming
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- 239000007943 implant Substances 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 9
- 238000009826 distribution Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 34
- 239000010703 silicon Substances 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 20
- 239000006117 anti-reflective coating Substances 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 210000005069 ears Anatomy 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- -1 silicon oxide compound Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Definitions
- the invention is in the filed of semiconductor fabrication and more specifically in semiconductor fabrication processes employing elevated source/drain processing.
- SOI wafers incorporate a shallow silicon region (in which transistor structures such as the transistor channel are located) overlying a buried, electrically insulating layer such as silicon dioxide.
- the shallow silicon layer may be too shallow to contain the transistor source/drain regions without exhibiting undesirable and performance limiting current crowding. Elevated source/drain structures alleviate this problem by providing a thicker silicon film where the source/drain regions are formed.
- elevated source/drain structures are fabricated with a selective epitaxial process.
- the epitaxial process that forms the elevated source/drain regions introduces an additional thermal cycle into the processing sequence.
- the additional thermal cycle has an undesirable impact on impurity distributions that have already been introduced into the wafer.
- these impurity distributions may include the halo and extension impurity distributions that are well known in the filed of CMOS fabrication. Because it is generally highly desirable to minimize the depth of the halo and extension implant distributions, the additional thermal cycle represented by the epitaxial process is problematic.
- the present invention relates to a semiconductor fabrication process in which a disposable spacer is used in conjunction with elevated source/drain processing to provide a reliable elevated source/drain process sequence.
- a disposable spacer is used in conjunction with elevated source/drain processing to provide a reliable elevated source/drain process sequence.
- the use of an offset spacer in conjunction with a disposable spacer beneficially prevents the formation of unwanted structures, such as "mouse ears" on the gate electrode, during the elevated source/drain formation sequence while still enabling the introduction of shallow implants after the elevated source/drain formation.
- a silicon nitride offset spacer is used to prevent formation of so-called “mouse ears" at the corners of the transistor gate electrode during epitaxial processing of the elevated source/drain.
- a wafer 100 is depicted at a first selected stage of a fabrication process according to the present invention.
- wafer 100 is a silicon-on-insulator (SOI) wafer that includes a silicon layer 108 overlying a buried oxide (BOX) layer 104.
- BOX layer 104 is likely overlying a silicon bulk region (not depicted) of wafer 100.
- Silicon layer 108 is preferably single crystal silicon having a thickness of approximately 700 Angstroms and BOX layer 104 is preferably a silicon oxide compound such as silicon dioxide having a thickness of approximately 1400 Angstroms.
- wafer 100 includes a gate structure overlying silicon layer 108.
- the gate structure includes a gate dielectric 112 overlying silicon layer 108, a conductive gate electrode 110 overlying gate dielectric 112, and a capping layer 114 overlying gate electrode 110.
- gate dielectric 112 is a silicon oxide compound such as thermally formed silicon dioxide and gate electrode 110 is a conventional polysilicon gate electrode.
- gate dielectric 112 may include a "high-K" dielectric material (i.e., a dielectric having a dielectric constant greater than the dielectric constant of silicon dioxide) such as hafnium oxide (HfO) while gate electrode 110 may include one or more metal materials such as titanium, tantalum, and alloys thereof.
- Capping layer 114 preferably provides an antireflective coating (ARC) over gate electrode 110.
- ARC antireflective coating
- capping layer 114 is a silicon nitride film.
- the elevated source/drain processing is initiated by forming an oxide dielectric liner 120 on the exterior of gate electrode 110 and the upper surface of silicon layer 108.
- the liner 120 is a relatively thin silicon oxide liner of approximately 23 Angstroms formed by thermally oxidizing polysilicon gate electrode 110 (and silicon layer 108).
- offset spacer 122 is formed on the sidewall of liner dielectric 120 adjacent the sidewalls of gate electrode 110.
- offset spacer 122 is formed by depositing silicon nitride on wafer 100 using a CVD reactor and thereafter anisotropically etching the deposited film to leave silicon nitride on vertically oriented surfaces such as the sidewalls of liner dielectric 120 while removing the silicon nitride from horizontally oriented surfaces such as the upper surface of liner dielectric 120 over silicon layer 108.
- offset spacer 122 contacts ARC 114 and thereby beneficially encloses or surrounds gate electrode 110 in silicon nitride to provide a protective barrier for the gate electrode during subsequent processing and, more specifically, during subsequent silicon formation processing.
- a 15nm (150 Angstrom) thick layer of silicon nitride is deposited and etch to form offset spacer 122.
- an intermediate liner dielectric of silicon oxide 124 is formed on the sidewalls of offset spacer 122 and the upper surface of liner dielectric 120.
- intermediate liner dielectric 124 is a CVD silicon-oxide film preferably having a thickness of approximately 150 Angstroms.
- first liner dielectric 120 is a thermally formed oxide
- second liner dielectric is a CVD oxide
- the etch rate of first liner dielectric 120 in HF solution is significantly less than the etch rate of second dielectric 124.
- the slower etch rate of liner dielectric 120 will ensure that liner dielectric 120 beneficially remains intact during subsequent processing to protect the gate electrode and provide mechanical support for the offset spacer 122.
- disposable spacer 130 a spacer of silicon nitride, referred to herein as disposable spacer 130, has been formed on the sidewalls of intermediate liner dielectric 124 adjacent the offset spacer 122.
- disposable spacer is formed by depositing approximately (900 Angstroms) of silicon nitride followed by an anisotropic silicon nitride etch.
- Disposable 90nm spacer 130 may then be subjected to a rapid thermal anneal (e.g., 5 seconds at 1060 °C) to "densify" the as-deposited silicon nitride.
- Disposable spacer 130 (in conjunction with capping layer 114 and offset spacer 122) serves as a mask that defines the portions of the underlying silicon wafer 108 on which an elevated source/drain structure will be formed.
- silicon wafer 100 beneficially incorporates disposable spacer 130 that enables the formation of elevated source/drain regions prior to shallow implant processes, such as extension and halo implant processes, that would be negatively impacted by the high temperature process required to form the elevated source/drain epitaxially.
- the inclusion of the offset spacer 122 and ARC 114 protects gate electrode 110 during the high temperature silicon formation process thereby preventing the formation of so-called mouse ears at the corners of the gate electrode.
- wafer 100 as depicted in FIG. 5 is suitable for be subjected to an epitaxial or other high temperature, silicon formation process, such as an elevated source/drain formation process sequence, without jeopardizing the physical dimensions of the gate electrode structure.
- the presently described invention promotes superior repeatability and reliability by providing better protection of the gate electrode.
- the gate electrode 110 of the present invention is sealed within a silicon nitride enclosure formed when offset spacer 122 is formed in contact with ARC 114.
- offset spacer 122 provides a good etch stop during subsequent etch processing and a desirable offset spacer for shallow implants.
- an elevated silicon layer 132 is formed overlying the exposed portions of silicon layer 108 (i.e., the portions of silicon layer 108 covered by neither gate electrode 110 nor disposable spacer 130).
- the preferred embodiment of forming elevated source/drain layer 132 includes epitaxial growth of elevated source/drain layer 132 using a silicon-chloride source such as SiHCL 3 at a temperature in excess of 1000 °C.
- a thickness of elevated source/drain layer 132 in one implementation is in the range of approximately 200 to 300 Angstroms. The presence of disposable spacer 130 during the epitaxial processing prevents formation of the epitaxial layer below the spacer.
- offset spacer 122 and ARC 114 prevent the epitaxial processing from affecting the profile of gate electrode 110.
- a thin (i.e., less than 2,5nm (25 Angstroms)) layer of oxide is thermally grown overlying elevated source/drain 132. This thin oxide, which is subsequently stripped, is a sacrificial layer that consumes contaminants and imperfections at the upper surface of the epitaxial film.
- disposable spacer 130 and intermediate liner dielectric 124 are removed without removing offset spacer 122 to expose portions of silicon layer 108 in close proximity to gate electrode 110 (displaced laterally from gate electrode 110 only by the combined thickness of liner 120 and offset spacer 122).
- Disposable spacer 130 is preferably removed by dipping wafer 100 in a phosphoric acid solution heated to 1 80 °C while second liner dielectric 124 is removed with an HF dip or another suitable etching process. If the HF is properly controlled, the thermally formed first liner dielectric 120 underlying offset spacer 122 will remain intact after CVD second liner dielectric 124 is removed due to differences in their respective etch rates in HF.
- the oxide-nitride-oxide-nitride layering of liner 120, spacer 122, liner 124, and spacer 130 enables the separate removal of each film thereby facilitating the removal of disposable spacer 130 without affecting offset spacer 122.
- the presence of offset spacer 122 beneficially protects the sidewalls of gate electrode 110 during removal of second liner dielectric 124.
- the removal of disposable spacer 130 also removes ARC 114 (as seen in FIG. 7 ).
- the removal of spacer 130 and liner 124 exposes the upper surface of silicon layer 108 proximal to gate electrode 110.
- Halo implant 140 is a angled implant that introduces an impurity of the same species as the well region in which it is introduced.
- Extension implant 142 introduces an opposite type impurity into each well region.
- Halo implant 140 is a P-type dopant such as boron while extension implant 142 is an N-type dopant such as phosphorous or arsenic.
- offset spacer 122 which has a thickness of approximately 100 Angstroms during the shallow implants is beneficial in optimizing the location of the implanted impurity distributions relative to gate electrode 110 and the underlying transistor channel.
- a third liner dielectric 134 and a replacement spacer 136 are formed where disposable spacer 130 and liner 124 existed previously to cover the portion of silicon layer 108 exposed when the disposable spacer was removed.
- the formation of liner 134 and spacer 136 is substantially equivalent to the formation of second liner dielectric 124 and disposable spacer 130.
- third liner dielectric 134 is a silicon oxide layer while replacement spacer 136 is silicon nitride.
- a source/drain implant represented by reference numeral 140 is performed to introduce a source/drain impurity distribution having a relatively high impurity concentration into elevated source/drain 132.
- source/drain implant 140 is an N-type dopant such as arsenic or phosphorous while a P-type dopant is used for PMOS transistors.
- a rapid thermal anneal process may be performed following source/drain implant 140 to activate the implanted species. A likely embodiment of this anneal would expose the wafer 100 to a temperature of approximately 1000 °C for a duration of approximately 5 seconds.
- silicide processing of wafer 100 is performed by depositing a metal such as cobalt that is reactive with silicon over wafer 100.
- the wafer is then heated to react the metal with silicon (where the metal overlies silicon) to form silicide structures identified by reference numeral 150 in a manner that will be familiar to those skilled in semiconductor wafer fabrication.
- Silicide 150 forms overlying the elevated source/drain region 130 as well as overlying silicon gate 110. In the depicted embodiment, the silicide 150 extends entirely through the elevated source/drain 132 and partially into the underlying silicon layer 108.
- the resulting transistor 160 includes a gate electrode 110 overlying a transistor channel region 162.
- a silicided and elevated source/drain region is laterally displaced from gate electrode 110.
- An offset spacer 122 and a replacement spacer 136, both comprised of silicon nitride are located between gate electrode 110 and elevated source/drain 132.
- a first liner oxide 120 is located between offset spacer 122 and gate electrode 110 while the third liner oxide 134 is positioned between offset spacer 122 and replacement spacer 136.
- the specified thickness for the various films and the source gas for the epitaxial formation of elevated source/drain 132 may be different than those specified herein.
- Another example of an alternative is to substitute a different metal for the silicide processing described with respect to FIG. 11 .
Abstract
Description
- The invention is in the filed of semiconductor fabrication and more specifically in semiconductor fabrication processes employing elevated source/drain processing.
- In the field of semiconductor fabrication, the scaling of silicon film thickness in silicon-on-insulator (SOI) technology has necessitated the use of elevated source/drain structures. SOI wafers incorporate a shallow silicon region (in which transistor structures such as the transistor channel are located) overlying a buried, electrically insulating layer such as silicon dioxide. The shallow silicon layer may be too shallow to contain the transistor source/drain regions without exhibiting undesirable and performance limiting current crowding. Elevated source/drain structures alleviate this problem by providing a thicker silicon film where the source/drain regions are formed.
- Generally, elevated source/drain structures are fabricated with a selective epitaxial process. The epitaxial process that forms the elevated source/drain regions, unfortunately, introduces an additional thermal cycle into the processing sequence. The additional thermal cycle has an undesirable impact on impurity distributions that have already been introduced into the wafer. In conventional processes, these impurity distributions may include the halo and extension impurity distributions that are well known in the filed of CMOS fabrication. Because it is generally highly desirable to minimize the depth of the halo and extension implant distributions, the additional thermal cycle represented by the epitaxial process is problematic.
- Accordingly, it would be highly desirable to introduce a method of semiconductor fabrication that incorporates an elevated source/drain processing while simultaneously addressing issued associated with the resulting impact of existing impurity profiles within the wafer. It would be further desirable if the implemented solution were highly repeatable and reliable and if the implemented process did not have any adverse affect on other transistor structures such as the gate electrode.
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US-A-5200352 (Motorola, Inc.), published on 06 April 1993, describes the manufacture of a MOSFET where the extensions are selectively implanted through the use of a disposable spacer 22. - The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
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FIG. 1 is a partial cross sectional view of a semiconductor wafer at a first selected stage of one embodiment of a fabrication process according to the present invention in which a gate electrode is formed overlying a substrate; -
FIG. 2 depicts processing subsequent toFIG. 1 in which a first oxide liner is formed; -
FIG. 3 depicts processing subsequent toFIG. 2 in which an offset spacer is formed adjacent the first oxide liner; -
FIG. 4 depicts processing subsequent toFIG. 3 in which a second oxide liner is formed; -
FIG. 5 depicts processing subsequent toFIG. 4 in which a disposable spacer is formed; -
FIG. 6 depicts processing subsequent toFIG. 5 in which an elevated source/drain is formed; -
FIG. 7 depicts processing subsequent toFIG. 6 in which the disposable spacer and the second oxide liner are removed; -
FIG. 8 depicts processing subsequent toFIG. 7 in which shallow implants are performed; -
FIG. 9 depicts processing subsequent toFIG. 8 in which a replacement oxide liner and a replacement spacer are formed where the disposable spacer previously existed; -
FIG. 10 depicts processing subsequent toFIG. 9 in which a source/drain implant is introduced into the elevated source/drain; and -
FIG. 11 depicts processing subsequent toFIG. 10 in which the gate electrode and source/drain regions are silicided. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
- The present invention relates to a semiconductor fabrication process in which a disposable spacer is used in conjunction with elevated source/drain processing to provide a reliable elevated source/drain process sequence. The use of an offset spacer in conjunction with a disposable spacer beneficially prevents the formation of unwanted structures, such as "mouse ears" on the gate electrode, during the elevated source/drain formation sequence while still enabling the introduction of shallow implants after the elevated source/drain formation. A silicon nitride offset spacer is used to prevent formation of so-called "mouse ears" at the corners of the transistor gate electrode during epitaxial processing of the elevated source/drain. By preventing the formation of unwanted structures, the fabrication process of the present invention beneficially more reliable and reproducible.
- Referring now to the drawings, a sequence of partial cross sectional views of a semiconductor wafer are presented reflecting selected stages of a fabrication process according to one embodiment of the present invention. In
FIG. 1 , awafer 100 is depicted at a first selected stage of a fabrication process according to the present invention. In the depicted embodiment,wafer 100 is a silicon-on-insulator (SOI) wafer that includes asilicon layer 108 overlying a buried oxide (BOX)layer 104.BOX layer 104 is likely overlying a silicon bulk region (not depicted) ofwafer 100.Silicon layer 108 is preferably single crystal silicon having a thickness of approximately 700 Angstroms andBOX layer 104 is preferably a silicon oxide compound such as silicon dioxide having a thickness of approximately 1400 Angstroms. - As depicted in
FIG. 1 ,wafer 100 includes a gate structure overlyingsilicon layer 108. The gate structure includes a gate dielectric 112 overlyingsilicon layer 108, aconductive gate electrode 110 overlying gate dielectric 112, and acapping layer 114 overlyinggate electrode 110. In one embodiment, gate dielectric 112 is a silicon oxide compound such as thermally formed silicon dioxide andgate electrode 110 is a conventional polysilicon gate electrode. In other embodiments, gate dielectric 112 may include a "high-K" dielectric material (i.e., a dielectric having a dielectric constant greater than the dielectric constant of silicon dioxide) such as hafnium oxide (HfO) whilegate electrode 110 may include one or more metal materials such as titanium, tantalum, and alloys thereof.Capping layer 114 preferably provides an antireflective coating (ARC) overgate electrode 110. In one such embodiment, capping layer 114 (also referred to herein as ARC 114) is a silicon nitride film. - Referring now to
FIG. 2 , the elevated source/drain processing according to the present invention is initiated by forming an oxidedielectric liner 120 on the exterior ofgate electrode 110 and the upper surface ofsilicon layer 108. In one embodiment, theliner 120 is a relatively thin silicon oxide liner of approximately 23 Angstroms formed by thermally oxidizing polysilicon gate electrode 110 (and silicon layer 108). - Referring to
FIG. 3 , a relatively thin dielectric spacer referred to herein asoffset spacer 122 is formed on the sidewall of liner dielectric 120 adjacent the sidewalls ofgate electrode 110. In one embodiment,offset spacer 122 is formed by depositing silicon nitride onwafer 100 using a CVD reactor and thereafter anisotropically etching the deposited film to leave silicon nitride on vertically oriented surfaces such as the sidewalls of liner dielectric 120 while removing the silicon nitride from horizontally oriented surfaces such as the upper surface of liner dielectric 120 oversilicon layer 108. In the depicted embodiment,offset spacer 122 contactsARC 114 and thereby beneficially encloses or surroundsgate electrode 110 in silicon nitride to provide a protective barrier for the gate electrode during subsequent processing and, more specifically, during subsequent silicon formation processing. In one embodiment, a 15nm (150 Angstrom) thick layer of silicon nitride is deposited and etch to formoffset spacer 122. - In
FIG. 4 , an intermediate liner dielectric ofsilicon oxide 124 is formed on the sidewalls ofoffset spacer 122 and the upper surface of liner dielectric 120. (Becauseliner dielectrics single reference numeral 124 overlying the silicon layer 108). In one implementation, intermediate liner dielectric 124 is a CVD silicon-oxide film preferably having a thickness of approximately 150 Angstroms. For embodiments in which first liner dielectric 120 is a thermally formed oxide and second liner dielectric is a CVD oxide, it will be appreciated that the etch rate of first liner dielectric 120 in HF solution is significantly less than the etch rate of second dielectric 124. The slower etch rate of liner dielectric 120 will ensure that liner dielectric 120 beneficially remains intact during subsequent processing to protect the gate electrode and provide mechanical support for theoffset spacer 122. - In
FIG. 5 , a spacer of silicon nitride, referred to herein asdisposable spacer 130, has been formed on the sidewalls of intermediate liner dielectric 124 adjacent theoffset spacer 122. In the preferred embodiment, disposable spacer is formed by depositing approximately (900 Angstroms) of silicon nitride followed by an anisotropic silicon nitride etch.Disposable 90nm spacer 130 may then be subjected to a rapid thermal anneal (e.g., 5 seconds at 1060 °C) to "densify" the as-deposited silicon nitride. Disposable spacer 130 (in conjunction withcapping layer 114 and offset spacer 122) serves as a mask that defines the portions of theunderlying silicon wafer 108 on which an elevated source/drain structure will be formed. - As depicted in
FIG. 5 ,silicon wafer 100 beneficially incorporatesdisposable spacer 130 that enables the formation of elevated source/drain regions prior to shallow implant processes, such as extension and halo implant processes, that would be negatively impacted by the high temperature process required to form the elevated source/drain epitaxially. In addition, the inclusion of theoffset spacer 122 and ARC 114 protectsgate electrode 110 during the high temperature silicon formation process thereby preventing the formation of so-called mouse ears at the corners of the gate electrode. Thus,wafer 100 as depicted inFIG. 5 is suitable for be subjected to an epitaxial or other high temperature, silicon formation process, such as an elevated source/drain formation process sequence, without jeopardizing the physical dimensions of the gate electrode structure. - Whereas conventional processes that form elevated source/drain structures prior to shallow implants typically form a nitride spacer, analogous to
spacer 130, directly on a very thin oxide liner that is in contact with the silicon gate electrode may exhibit significant and unwanted silicon formation on the gate electrode during epitaxial processing, the presently described invention promotes superior repeatability and reliability by providing better protection of the gate electrode. Thegate electrode 110 of the present invention is sealed within a silicon nitride enclosure formed when offsetspacer 122 is formed in contact withARC 114. In addition, as described below, offsetspacer 122 provides a good etch stop during subsequent etch processing and a desirable offset spacer for shallow implants. - Turning now to
FIG. 6 , anelevated silicon layer 132 is formed overlying the exposed portions of silicon layer 108 (i.e., the portions ofsilicon layer 108 covered by neithergate electrode 110 nor disposable spacer 130). The preferred embodiment of forming elevated source/drain layer 132 includes epitaxial growth of elevated source/drain layer 132 using a silicon-chloride source such as SiHCL3 at a temperature in excess of 1000 °C. A thickness of elevated source/drain layer 132 in one implementation is in the range of approximately 200 to 300 Angstroms. The presence ofdisposable spacer 130 during the epitaxial processing prevents formation of the epitaxial layer below the spacer. Similarly, the presence of offsetspacer 122 andARC 114 prevent the epitaxial processing from affecting the profile ofgate electrode 110. In one embodiment, following the formation of elevated source/drain 132, a thin (i.e., less than 2,5nm (25 Angstroms)) layer of oxide is thermally grown overlying elevated source/drain 132. This thin oxide, which is subsequently stripped, is a sacrificial layer that consumes contaminants and imperfections at the upper surface of the epitaxial film. - Referring now to
FIG. 7 , following completion of elevated source/drain region 132,disposable spacer 130 and intermediate liner dielectric 124 are removed without removing offsetspacer 122 to expose portions ofsilicon layer 108 in close proximity to gate electrode 110 (displaced laterally fromgate electrode 110 only by the combined thickness ofliner 120 and offset spacer 122).Disposable spacer 130 is preferably removed by dippingwafer 100 in a phosphoric acid solution heated to 180 °C whilesecond liner dielectric 124 is removed with an HF dip or another suitable etching process. If the HF is properly controlled, the thermally formedfirst liner dielectric 120 underlying offsetspacer 122 will remain intact after CVDsecond liner dielectric 124 is removed due to differences in their respective etch rates in HF. - The oxide-nitride-oxide-nitride layering of
liner 120,spacer 122,liner 124, andspacer 130 enables the separate removal of each film thereby facilitating the removal ofdisposable spacer 130 without affecting offsetspacer 122. The presence of offsetspacer 122 beneficially protects the sidewalls ofgate electrode 110 during removal ofsecond liner dielectric 124. For embodiments in whichARC 114 anddisposable spacer 130 are both silicon nitride, the removal ofdisposable spacer 130 also removes ARC 114 (as seen inFIG. 7 ). The removal ofspacer 130 andliner 124 exposes the upper surface ofsilicon layer 108 proximal togate electrode 110. - Referring now to
FIG. 8 , shallow implants including a halo implant represented byreference numeral 140 and an extension implant represented byreference numeral 142 are performed.Halo implant 140 is a angled implant that introduces an impurity of the same species as the well region in which it is introduced.Extension implant 142 introduces an opposite type impurity into each well region. Thus, for NMOS transistors (on P-wells),Halo implant 140 is a P-type dopant such as boron whileextension implant 142 is an N-type dopant such as phosphorous or arsenic. The presence of offsetspacer 122, which has a thickness of approximately 100 Angstroms during the shallow implants is beneficial in optimizing the location of the implanted impurity distributions relative togate electrode 110 and the underlying transistor channel. - Referring now to
FIG. 9 , following the shallow implants, athird liner dielectric 134 and areplacement spacer 136 are formed wheredisposable spacer 130 andliner 124 existed previously to cover the portion ofsilicon layer 108 exposed when the disposable spacer was removed. In one embodiment, the formation ofliner 134 andspacer 136 is substantially equivalent to the formation ofsecond liner dielectric 124 anddisposable spacer 130. In this embodiment, therefore,third liner dielectric 134 is a silicon oxide layer whilereplacement spacer 136 is silicon nitride. - Referring to
FIG. 10 , a source/drain implant represented byreference numeral 140 is performed to introduce a source/drain impurity distribution having a relatively high impurity concentration into elevated source/drain 132. For NMOS transistors, source/drain implant 140 is an N-type dopant such as arsenic or phosphorous while a P-type dopant is used for PMOS transistors. A rapid thermal anneal process may be performed following source/drain implant 140 to activate the implanted species. A likely embodiment of this anneal would expose thewafer 100 to a temperature of approximately 1000 °C for a duration of approximately 5 seconds. - Referring now to
FIG. 11 , silicide processing ofwafer 100 is performed by depositing a metal such as cobalt that is reactive with silicon overwafer 100. The wafer is then heated to react the metal with silicon (where the metal overlies silicon) to form silicide structures identified byreference numeral 150 in a manner that will be familiar to those skilled in semiconductor wafer fabrication.Silicide 150 forms overlying the elevated source/drain region 130 as well as overlyingsilicon gate 110. In the depicted embodiment, thesilicide 150 extends entirely through the elevated source/drain 132 and partially into theunderlying silicon layer 108. - The resulting
transistor 160 includes agate electrode 110 overlying atransistor channel region 162. A silicided and elevated source/drain region is laterally displaced fromgate electrode 110. An offsetspacer 122 and areplacement spacer 136, both comprised of silicon nitride are located betweengate electrode 110 and elevated source/drain 132. Afirst liner oxide 120 is located between offset spacer 122 andgate electrode 110 while thethird liner oxide 134 is positioned between offset spacer 122 andreplacement spacer 136. - In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. As examples, the specified thickness for the various films and the source gas for the epitaxial formation of elevated source/
drain 132 may be different than those specified herein. Another example of an alternative is to substitute a different metal for the silicide processing described with respect toFIG. 11 .
Claims (9)
- A semiconductor fabrication process comprising: forming a gate electrode (110) overlying a substrate (108); forming an oxide liner (120) on sidewalls of the gate electrode; forming an offset spacer (122) of silicon nitride adjacent the oxide liner; forming an intermediate liner (124) of silicon oxide adjacent the offset spacer; forming a disposable spacer (130) of silicon nitride adjacent the intermediate liner; forming an elevated source/drain (132) overlying the substrate (108) and displaced laterally from sidewalls of the gate electrode (110) by the disposable spacer (110); following forming the elevated source/drain removing the intermediate oxide liner and the disposable spacer (130) to expose the upper surface of the substrate and implanting halo (140) or extension implants (142) into the exposed substrate; and following performing the halo (140) or extension implants (142), forming a replacement intermediate oxide liner and a replacement spacer (186) located substantially where the original intermediate oxide liner and disposable spacer (130) were located.
- The process of claim 1, wherein forming the gate electrode (110) includes forming a silicon nitride capping layer overlying a polysilicon gate electrode.
- The process of claim 2, wherein the offset silicon nitride spacer contacts the capping layer to surround the polysilicon gate electrode in silicon nitride.
- The process of claim 1, wherein the offset silicon nitride spacer is formed from a silicon nitride film having a thickness of approximately 15 nm (150 Angstroms).
- The process of claim 4, wherein the disposable silicon nitride spacer is formed from a silicon nitride film having a thickness of approximately 90 nm (900 Angstroms).
- The process of claim 1, further comprising rapid thermally annealing the wafer following formation of the disposable spacer by exposing the wafer to an ambient maintained at a temperature of approximately 1060.degree. C. for a duration of approximately 5 seconds.
- The process of claim 1, further comprising depositing cobalt over the wafer following the source/drain implant and heating the wafer to react the cobalt where it contacts silicon including silicon in the elevated source/drain and silicon in the gate electrode.
- The process of claim 1, further comprising, following formation of the replacement spacer, performing a source/drain implant to introduce a source/drain impurity distribution into the elevated source/drain.
- The process of claim 1, wherein forming the elevated source/drain includes epitaxial formation of the elevated source/drain at a temperature of at least 1000.degree. C.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/839,385 US7125805B2 (en) | 2004-05-05 | 2004-05-05 | Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing |
PCT/US2005/012252 WO2005112099A2 (en) | 2004-05-05 | 2005-04-13 | Method of semiconductor fabrication in corporating disposable spacer into elevated source/drain processing |
Publications (3)
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EP1756860A2 EP1756860A2 (en) | 2007-02-28 |
EP1756860A4 EP1756860A4 (en) | 2008-12-17 |
EP1756860B1 true EP1756860B1 (en) | 2009-11-04 |
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EP05735763A Not-in-force EP1756860B1 (en) | 2004-05-05 | 2005-04-13 | Method of semiconductor fabrication in corporating disposable spacer into elevated source/drain processing |
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US (1) | US7125805B2 (en) |
EP (1) | EP1756860B1 (en) |
JP (1) | JP5048480B2 (en) |
KR (1) | KR20070007900A (en) |
CN (1) | CN1998072B (en) |
AT (1) | ATE447765T1 (en) |
DE (1) | DE602005017490D1 (en) |
TW (1) | TWI377625B (en) |
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KR100668954B1 (en) * | 2004-12-15 | 2007-01-12 | 동부일렉트로닉스 주식회사 | Method for manufacturing of the thin film transistor |
US7745296B2 (en) * | 2005-06-08 | 2010-06-29 | Globalfoundries Inc. | Raised source and drain process with disposable spacers |
US20070056930A1 (en) * | 2005-09-14 | 2007-03-15 | International Business Machines Corporation | Polysilicon etching methods |
US7514331B2 (en) * | 2006-06-08 | 2009-04-07 | Texas Instruments Incorporated | Method of manufacturing gate sidewalls that avoids recessing |
US7510923B2 (en) * | 2006-12-19 | 2009-03-31 | Texas Instruments Incorporated | Slim spacer implementation to improve drive current |
US7550808B2 (en) * | 2007-01-18 | 2009-06-23 | International Business Machines Corporation | Fully siliciding regions to improve performance |
JP2009158677A (en) * | 2007-12-26 | 2009-07-16 | Renesas Technology Corp | Method of manufacturing semiconductor device and method of manufacturing semiconductor device for hybrid transistor |
JP6169222B2 (en) * | 2012-01-23 | 2017-07-26 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5968708B2 (en) | 2012-01-23 | 2016-08-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US9171927B2 (en) | 2013-03-26 | 2015-10-27 | GlobalFoundries, Inc. | Spacer replacement for replacement metal gate semiconductor devices |
CN103412444B (en) * | 2013-07-23 | 2015-08-26 | 北京京东方光电科技有限公司 | A kind of array base palte and preparation method thereof and display panel |
JP6279291B2 (en) * | 2013-11-18 | 2018-02-14 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US9773865B2 (en) | 2014-09-22 | 2017-09-26 | International Business Machines Corporation | Self-forming spacers using oxidation |
US11653498B2 (en) * | 2017-11-30 | 2023-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device with improved data retention |
JP7034834B2 (en) | 2018-05-30 | 2022-03-14 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and their manufacturing methods |
US11437245B2 (en) * | 2020-09-30 | 2022-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium hump reduction |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5200352A (en) * | 1991-11-25 | 1993-04-06 | Motorola Inc. | Transistor having a lightly doped region and method of formation |
US5496750A (en) * | 1994-09-19 | 1996-03-05 | Texas Instruments Incorporated | Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition |
JP2848299B2 (en) * | 1995-12-21 | 1999-01-20 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5847428A (en) * | 1996-12-06 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
TW469648B (en) * | 1999-09-07 | 2001-12-21 | Sharp Kk | Semiconductor device and its manufacture method |
US6555437B1 (en) * | 2001-04-27 | 2003-04-29 | Advanced Micro Devices, Inc. | Multiple halo implant in a MOSFET with raised source/drain structure |
US20020171107A1 (en) * | 2001-05-21 | 2002-11-21 | Baohong Cheng | Method for forming a semiconductor device having elevated source and drain regions |
US6614079B2 (en) * | 2001-07-19 | 2003-09-02 | International Business Machines Corporation | All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS |
JP2004095639A (en) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
US6800530B2 (en) * | 2003-01-14 | 2004-10-05 | International Business Machines Corporation | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors |
US20050048732A1 (en) * | 2003-08-26 | 2005-03-03 | International Business Machines Corporation | Method to produce transistor having reduced gate height |
-
2004
- 2004-05-05 US US10/839,385 patent/US7125805B2/en active Active
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2005
- 2005-04-13 EP EP05735763A patent/EP1756860B1/en not_active Not-in-force
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- 2005-04-13 DE DE602005017490T patent/DE602005017490D1/en active Active
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- 2005-04-13 CN CN200580014349XA patent/CN1998072B/en not_active Expired - Fee Related
- 2005-04-13 JP JP2007511381A patent/JP5048480B2/en not_active Expired - Fee Related
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EP1756860A4 (en) | 2008-12-17 |
DE602005017490D1 (en) | 2009-12-17 |
TWI377625B (en) | 2012-11-21 |
WO2005112099A3 (en) | 2006-04-27 |
US7125805B2 (en) | 2006-10-24 |
KR20070007900A (en) | 2007-01-16 |
US20050250287A1 (en) | 2005-11-10 |
WO2005112099A2 (en) | 2005-11-24 |
JP2007536734A (en) | 2007-12-13 |
CN1998072B (en) | 2010-09-15 |
JP5048480B2 (en) | 2012-10-17 |
TW200625463A (en) | 2006-07-16 |
CN1998072A (en) | 2007-07-11 |
ATE447765T1 (en) | 2009-11-15 |
EP1756860A2 (en) | 2007-02-28 |
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