EP1856720A2 - Verfahren zum herstellen eines bauelements - Google Patents
Verfahren zum herstellen eines bauelementsInfo
- Publication number
- EP1856720A2 EP1856720A2 EP06722565A EP06722565A EP1856720A2 EP 1856720 A2 EP1856720 A2 EP 1856720A2 EP 06722565 A EP06722565 A EP 06722565A EP 06722565 A EP06722565 A EP 06722565A EP 1856720 A2 EP1856720 A2 EP 1856720A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- semiconductor layer
- component
- substrate
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34333—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
- H01L21/0265—Pendeoepitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2301/00—Functional characteristics
- H01S2301/17—Semiconductor lasers comprising special layers
- H01S2301/176—Specific passivation layers on surfaces other than the emission facet
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2304/00—Special growth methods for semiconductor lasers
- H01S2304/12—Pendeo epitaxial lateral overgrowth [ELOG], e.g. for growing GaN based blue laser diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/0207—Substrates having a special shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/021—Silicon based substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/1003—Waveguide having a modified shape along the axis, e.g. branched, curved, tapered, voids
- H01S5/1017—Waveguide having a void for insertion of materials to change optical properties
Definitions
- the invention relates to a method for producing an electrical and / or optical component - for example, an electrical transistor, a laser, a light-emitting diode, a photodetector or an optical waveguide.
- Such a method is known for example from US Patent 5,389,571.
- an AlN intermediate layer is first applied to a silicon substrate.
- GaN layers are then deposited on this AlN intermediate layer, from which a light-emitting diode is formed.
- the function of the AlN interlayer is to avoid three-dimensional growth of the GaN layers; Namely, GaN and silicon have different lattice constants, so that three-dimensional growth would occur if the GaN layers grow directly on the silicon substrate.
- the invention has for its object to provide a method for producing an electrical and / or optical device, in which a particularly good quality of the device is achieved.
- crystal dislocations in the material layers of the device should be reliably avoided.
- a method is provided in which at least one trench is etched into a substrate.
- the trench is laterally overgrown with at least one semiconductor layer in such a way that it is completely covered by the semiconductor layer with the formation of a gas-filled, in particular air-filled, cavity.
- the component is integrated in the semiconductor layer or in a further semiconductor layer applied to the semiconductor layer, the active region of the component being arranged above the hollow space.
- An essential advantage of the method according to the invention is that due to the etching of one or more trenches, a particularly low-dislocation growth of the semiconductor layers is made possible. Namely, the etching of trenches produces a non-planar substrate on which subsequently also such semiconductor layers can be deposited with little dislocation, whose crystal lattice spacings do not match the crystal lattice spacings of the substrate. This is due to the fact that, in the region of the trenches, the deposited semiconductor layers have no contact with the substrate, so that no grid voltages can occur in these areas.
- Another important advantage of the method according to the invention is improved properties of the component, since it is placed over the gas-filled cavity. Namely, in both optical and electrical components, it is regularly advantageous if the electrical and / or electromagnetic fields or waves generated by the components can not penetrate into the substrate, because such penetration for the formation of additional damping and / or training can cause additional capacitive effects; such parasitic effects are avoided in the inventive method, because the components are selectively placed in an area which is removed by a gas, such as air, from the substrate, so that an electrical and optical decoupling is achieved by the substrate.
- a gas such as air
- Silicon is known to be a material very suitable for the production of electrical components, so that it is considered advantageous if a silicon substrate is used as the substrate.
- a nitride layer in particular based on one or more elements of group III of the periodic system, is preferably deposited as the semiconductor layer.
- a nitride layer is preferably deposited as the semiconductor layer.
- GaN layers or GaN-containing layers can be deposited on the substrate as the semiconductor layer.
- a particularly low-dislocation growth of GaN layers or GaN-containing layers on a silicon substrate is achieved, for example, when the surface of the silicon substrate has a (111) orientation and the longitudinal direction of the cavity along a (1 -1 O ) - Substrate orientation or a (1 1 -2) - substrate orientation is arranged. If the component is an optoelectronic component, then the optically active zone of the optoelectronic component is preferably arranged above the cavity.
- the longitudinal direction of the waveguide is preferably arranged parallel to the longitudinal direction of the cavity.
- an optoelectronic component for example, a light-emitting element, in particular a light emitting diode o- a laser, or a detector element, in particular a photodiode can be produced. If the optoelectronic component is an edge-emitting laser, its emission direction is preferably arranged parallel to the longitudinal direction of the cavity.
- a transistor in particular a field effect transistor can be produced.
- the channel region of the transistor is preferably arranged above the cavity.
- the channel region can be arranged perpendicular, parallel or at any other angle to the longitudinal direction of the cavity.
- both a transistor and an optoelectronic component can be produced above the cavity, wherein the two components are electrically connected to form an optoelectronic assembly.
- the substrate is preferably provided with a passivation layer and the semiconductor layer is then deposited directly or indirectly on the passivation layer.
- the passivation layer can for example be used directly as a nucleation layer for the growth of the semiconductor layer.
- the passivation layer may be formed by a conversion of the surface of the substrate.
- the passivation layer is preferably formed electrically conductive.
- the passivation layer can be formed, for example, by a single layer or alternatively by a layer package comprising a plurality of individual passivation layers.
- a layer package comprising a plurality of individual passivation layers.
- an AlN or an Al x Gai_ x N layer or a layer package having at least one AlN and at least one Al x Gai_ x N layer is deposited on the substrate as the passivation layer.
- an AlAs layer can be first deposited, for example; these AlAs layer is then preferably nitrided to form an AlN layer.
- an Al x Ga x N layer on the AlN passivation layer as a further passivation layer or as a semiconductor or "wear layer".
- the growth is preferably interrupted at least once during the growth of the GaN semiconductor layer or the GaN-containing semiconductor layer, and one at each interruption Intermediate layer grown up.
- This intermediate layer is preferably such that it generates a compressive strain.
- AlN layers can be grown as intermediate layers.
- the thickness of each intermediate layer is for example between 7 nm and 9 nm, preferably about 8 nm.
- the growth of the intermediate layers is preferably carried out at a temperature between 900 and 1100 degrees Celsius, preferably at 1000 degrees Celsius. In the following, all temperatures are in degrees Celsius, unless stated otherwise in individual cases.
- a plurality of parallel trenches are etched into the substrate, the spacing of the trenches from one another being selected smaller than the width of the trenches.
- the depth of the trenches is for example at least 1 .mu.m, preferably 2-4 microns.
- the width of the trenches is preferably at least 2 ⁇ m, preferably 5 ⁇ m to 10 ⁇ m.
- the Width of the webs, which are each formed between two adjacent trenches for example, a maximum of 2 microns and is preferably less than 1 micron.
- the trenches are arranged such that the ridges remaining between the trenches form a pillar structure, for example a hexagonal lattice.
- an SOI (silicon-on-insulator) substrate can be used;
- the trench or the trenches can be etched to the buried insulation layer, for example, which would act as an etch stop.
- SOI material causes a particularly good insulation, in particular for transistors.
- the invention also relates to an electrical and / or optical component.
- the invention is based on the object with respect to such a component to obtain a particularly good component behavior. This object is achieved by a device having the features according to claim 33. Advantageous embodiments of the device according to the invention are specified in sub-claims.
- a component is provided with a substrate having at least one trench, the trench having at least one semiconductor layer being laterally overgrown such that it is completely covered by the semiconductor layer to form a gas-filled, in particular air-filled, cavity.
- the active region of the component is integrated in the semiconductor layer or in a further semiconductor layer applied to the semiconductor layer and preferably exclusively-arranged above the cavity.
- the term "active region" is to be understood as meaning, for example, in the case of a light-emitting element, such as a laser or a light-emitting diode, the light-generating region, in the case of a field-effect transistor the channel region, and in the case of a waveguide, the wave-guiding region.
- the deposition of a passivation layer which has already been described in detail above, is incidentally an independent idea of the invention.
- the deposition of the passivation layer prevents leakage of impurities from the substrate during the growth of the semiconductor layer, so that the growth of the semiconductor layer is not is disturbed and a low-dislocation overgrowth of the trench is reliably achieved.
- a method is considered to be inventive in which at least one trench is etched into a substrate, after the etching of the trench, the substrate is provided with a passivation layer, wherein the deposition of the passivation layer is such that all side wall portions of the etched trench completely covered with the passivation layer, at least one semiconductor layer is deposited directly or indirectly on the passivation layer, wherein the trench with the semiconductor layer is laterally overgrown such that it is completely covered by the semiconductor layer to form a gas-filled, in particular air-filled, cavity, and the device in FIG the semiconductor layer or in a further semiconductor layer applied to the semiconductor layer is integrated.
- the deposition of intermediate layers during the deposition of a GaN semiconductor layer or a GaN-containing semiconductor layer represents a further independent aspect of the invention.
- a method is also considered inventive in which at least one trench is etched into a substrate and the trench is laterally overgrown with at least one GaN semiconductor layer or a GaN-containing semiconductor layer in such a way that the trench is protected by the semiconductor layer.
- a gas-filled, in particular air-filled cavity wherein the growth is interrupted at least once during the growth of the semiconductor layer on the substrate and in each case an intermediate layer is grown at each interruption, and in which the construction element is integrated in the semiconductor layer or in a further semiconductor layer applied to the semiconductor layer.
- FIG. 1 shows a first exemplary embodiment of a component according to the invention, with reference to which a first variant of the method according to the invention is explained,
- FIG. 2 shows a second exemplary embodiment of the invention in which the substrate surface is passivated.
- FIG. 3 shows a third exemplary embodiment of the invention, in which intermediate layers are deposited
- Figure 4 shows a fourth embodiment of the invention with a laser structure
- Figure 5 shows a fifth embodiment of the invention with a field effect transistor structure.
- FIGS. 1 to 5 the same reference numerals are used for identical or comparable components.
- FIG. 1 shows a silicon substrate 10 whose substrate surface 20 has a (111) orientation.
- a photolithographically defined photoresist mask in the form of parallel strips oriented in the direction of silicon [1-10] is firstly applied to the surface 20 of the silicon substrate 10 applied. In the illustration according to FIG. 1, these strips would extend in the Z direction. The width of these strips is 2 microns and the distance between the strips in each case 3 microns.
- the surface 20 of the silicon substrate 10 then has trenches, which are identified by the reference numeral 30 in FIG.
- the silicon substrate 10 is cleaned in acetone and propanol and subjected to etching with an H 2 SO 4 : H 2 O 2 : H 2 O mixture and buffered HF solution, with sufficient rinsing between each step with deionized ultrapure water.
- a semiconductor layer for example, a gallium nitrite semiconductor layer 50 is deposited on the thus cleaned silicon substrate 10.
- a semiconductor layer for example, a gallium nitrite semiconductor layer 50 is deposited on the thus cleaned silicon substrate 10.
- the epitaxy it is possible to use all suitable chemical compounds with group III or group V elements which lead to the deposition of the desired gallium nitrite semiconductor layer. Suitable means in this context that the compounds are stable at room temperature, but can be decomposed at the usual for nitrite epitaxy temperatures T> 100 ° C.
- T> 100 ° C for example, trimethyl gallium, trimethyl aluminum, ammonia and arsine can be used.
- a metal organic vapor phase epitaxy (MOCVD) or another epitaxy method, such as MBE or HVPE can be used.
- the deposition of the gallium nitrite semiconductor layer 50 takes place in such a way that the trenches 30 are laterally overgrown. As a result of this lateral overgrowth, a closed, planar covering layer is formed on the nonplanar silicon substrate 10, under which gas, in particular air-filled cavities 60 are formed.
- Electric, electronic or electro-optical components 70 can be arranged in the usual manner known to the semiconductor layer 50 deposited in this way.
- the arrangement of the components 70 on the semiconductor layer 50 takes place such that they are above the gas-filled cavities 60.
- the arrangement of the components 70 above the cavities 60 leads namely to a particularly favorable electrical and / or optical behavior of the components, which will be explained in more detail below in connection with the embodiments according to Figures 4 and 5.
- FIG. 2 shows a second exemplary embodiment of the invention. It can be seen that a passivation layer 100 is first applied to the silicon substrate 10 after the etching of the trenches 30 before the gallium nitrite semiconductor layer 50 is deposited over the entire area on the substrate 10.
- the formation of the passivation layer 100 is carried out as follows: First, an approximately 2 nm thick aluminum arsenite (AlAs) layer is deposited on the non-planar silicon substrate 10 at a temperature of approximately 43O 0 C. Subsequently, the growth is an approximately 30 nm thick AlAs layer at a temperature of 825 0 C.
- the thus formed Aluminiumar- Senit layer packet is nitrided by supplying ammonia at a temperature of about 960 0 C, so that a Aluminum nitrite (AlN) layer or surface is obtained. Thereafter, an approximately 50 nm thick Al x Gal_ x N layer (x> 0) is deposited at a temperature of about 1150 ° C.
- the reactor pressure is preferably about 50 mbar, and the growth rate is preferably greater than 0.3 ⁇ m / h.
- This layer is deposited by adding TMAl (trimethyl-aluminum) and TMGa (trimethyl-gallium) as well as ammonia.
- TMAl trimethyl-aluminum
- TMGa trimethyl-gallium
- the growth rate of the Al x Gai- ⁇ N-layer results from the corresponding offer of TMAl and TMGa.
- Such layers have a high degree of adhesion to the silicon surface 20 of the silicon substrate 10, whereby the entire surface, in particular the side walls 105 of the trenches 30, are completely covered.
- passivation layer 100 The laminate of aluminum nitrite formed in this manner and the Al x Gal x N layer deposited thereon is designated as passivation layer 100 in FIG.
- This passivation layer 100 is then layered as a semiconductor, a GaN layer 50 by supplying TMGa and ammonia at a temperature of 1125 0 C with a vertical growth rate of 0.5 microns / hr and grown a reactor pressure of 200 mbar.
- a conventional semiconductor structure for transistors, light-emitting diodes or laser diodes of (In, Ga, Al) N layers can be deposited as semiconductor components.
- FIG. 3 shows a third exemplary embodiment of the invention. It will be appreciated that as the gallium nitrate semiconductor layer 50 is deposited, additional intermediate layers 110 are deposited.
- the structure according to FIG. 3 is produced in the following steps: The substrate 10 is first heated to a temperature of 720 ° C. under a nitrogen atmosphere. The growth start takes place by pre-flow with TMAl for 10 seconds and subsequent connection of ammonia with a flow of 1.5 l / min at a reactor pressure of about 50 mbar. The resulting AlN nucleation layer simultaneously serves as passivation layer 100 and is therefore grown to 50 nm thick.
- the growth of the gallium nitrite semiconductor layer 50 by feeding TMGa and ammonia begins at a temperature of 125 0 C and a reactor pressure of 200 mbar and a vertical growth rate of 0.5 .mu.m / h.
- the growth of the GaN layer is interrupted after every 0.5 .mu.m - ie a growth time of about 60 minutes vertical GaN growth and it is an about 8 nm thick AlN layer as an intermediate layer 110 at a temperature of 1000 0 C and a reactor pressure of 50 mbar and a growth rate of 160 nm / h grown on the GaN surface.
- a GaN layer is grown again for 60 min. This GaN / AlN deposition is repeated until a closed GaN surface 120 results, to which suitable components 70 can then be deposited.
- two intermediate layers 110 are accommodated in the semiconductor layer 50.
- the number of intermediate layers 110 should be selected such that as low as possible dislocation growth of the gallium nitrite semiconductor layer 50 is achieved.
- FIG. 4 shows a fourth exemplary embodiment of the invention; in this example will be on the Gallium nitrite semiconductor layer 50 optical components in the form of three laser 300 applied.
- the silicon substrate 10 is first provided with the trenches 30 and then passivated with the passivation layer 100. Subsequently, a gallium nitrite semiconductor layer 50 is deposited on the passivated silicon surface 20, whereby the trenches 30 are overgrown to form gas-filled cavities 60. During the deposition of the gallium nitrite semiconductor layer 50, intermediate layers 110 are respectively deposited to prevent crystal dislocations in the growth of the gallium nitride semiconductor layer 50. After the trenches 30 are completely closed, an n-doped contact layer 200 is first applied to the gallium nitrite semiconductor layer 50.
- n-doped contact layer 200 On the n-doped contact layer 200, a light-emitting layer 210 and on it a waveguide sheath layer 220 is deposited. Subsequently, a p-doped contact layer 230, which forms an upper electrode layer of the laser structure, is deposited on the waveguide cladding layer 220.
- the laser structure according to FIG. 4 comprises a total of three edge-emitting lasers 300, which emit the light parallel to the longitudinal direction of the trenches 30 or parallel to the longitudinal direction of the gas-filled cavities 60.
- the optical field distribution - in the y-direction - of the three lasers 300 is also shown schematically in FIG. It can be seen that the optical field distribution ⁇ extends into the gas-filled cavities 60, but remains separated from the silicon substrate 10 due to the high refractive index jump between semiconductor material and gas. Due to the fact that the optical field distribution can not extend into the silicon substrate, additional light attenuation occurs or waveguide attenuation prevented by the silicon substrate 10.
- the deposition of the laterally overgrown gallium nitrite semiconductor layer 50 takes place in accordance with the methods described in connection with FIGS a 50 nm thick AlN nucleation layer.
- the gallium nitrite semiconductor layer 50 is deposited, wherein in addition in each case an 8 nm thin AlN intermediate layer 110 is deposited precisely if each 500 nm gallium nitrite have been grown in the vertical direction. This procedure is repeated until the resulting gallium nitride semiconductor layer 50 completes the trenches 30 completely laterally and the gas filled cavities 60 are completely covered.
- further processes are necessary after completion of the epitaxy, which limit the vertical current flow and / or the lateral optical waveguide to the region above the gas-filled cavities 60 - this is indicated in FIG. 4 by hatched zones 300.
- These other processes can, for.
- As etching processes for defining a Rippenwellen- conductor include or implantation processes for the definition of corresponding current paths.
- the lasers 300 and the optical waveguides which may be connected to the lasers 300 be aligned in such a way that the light above and optionally inside the gas-filled hollow waveguide is aligned.
- the arrangement of the laser 30 and the corresponding arrangement of the light propagation direction ensures that the light can not propagate within the silicon substrate 10; In that propagation of the light within the silicon substrate 10 is avoided, additional waveguide attenuation by the silicon substrate 10 is prevented.
- silicon is strongly absorbing for wavelengths below 1.1 ⁇ m.
- optical waveguide remains spatially separated from the silicon substrate 10; this is achieved by the appropriate arrangement of the optical components - such as lasers, LEDs and waveguides - above the gas-filled cavities 60.
- Another advantage of the arrangement of the laser 300 above the gas-filled cavities 60 is also to be seen in the fact that mirror facets of the laser 300 can also be produced by crystal columns instead of complex etching processes.
- mirror facets of the laser 300 can also be produced by crystal columns instead of complex etching processes.
- a fifth embodiment of the invention is shown;
- a field effect transistor structure 400 having a plurality of field effect transistors 405 is formed on the gallium nitride semiconductor layer 50 deposited.
- the laterally overgrown semiconductor nitride layer 50 is produced in accordance with the exemplary embodiments according to FIGS. 1 to 4, with passivation of the surface 20 of the nonplanar silicon substrate 10 after deposition of the nucleation layer by means of a 50 nm thick AlN layer.
- a GaN layer is vertically grown on the lands 40 to a thickness of 500 nm, and then an 8 nm thin AlN intermediate layer 110 is deposited.
- the following GaN layer is grown mainly laterally until the GaN layer closes, so that the GaN thickness over the AlN intermediate layer 110 remains smaller than about 1 ⁇ m.
- An undoped, approx. 30 nm thick AlGaN covering layer 410 is grown over the entire surface area of the low-defect gallium nitrite semiconductor layer 50 thus obtained.
- the boundary layer between the gallium nitrite semiconductor layer 50 and the AlGaN cover layer 410 is the electrically active zone of the field effect transistor structure 400.
- the conductivity of the field effect transistor structure 400 is generated by polarization charging.
- the photolithographic definitions of the contact regions (source gate drain) on the corresponding laterally overgrown areas or the gas-filled cavities 60 must be limited - this is indicated in the figure 5 by the hatched areas 405.
- a significant advantage of the arrangement of the transistors 405 above the gas-filled cavities 60 is that an electrical separation is achieved by the gas filling to the silicon substrate 10, so that parasitic capacitances are avoided by an electrical coupling to the silicon substrate 10; because the gas-filled cavities 60 cause a high electrical insulation.
- the fact that the gas-filled cavities 60 avoid parasitic capacitances to and in the silicon substrate 10 significantly increases, for example, the usually RC-limited cutoff frequency of the transistors 405. Nevertheless, the transistors 405 are still close enough to the silicon substrate 10 acting as a thermal mass, so that thermal losses or waste heat of the transistors 405 can be dissipated into the substrate 10.
- the gallium nitrite layer 50 By the very low-dislocation growth of the gallium nitrite layer 50, moreover, it is also achieved that relatively few crystal dislocations occur in the channel region of the transistors 405; An additional charge carrier scattering by dislocations is thus also avoided, whereby the transit time-limited cut-off frequency of the transistors 405 is significantly increased.
- the trenches 30 and therefore the cavities 60 are preferably chosen to be as narrow as possible, for example only slightly larger than the transistors 405, in order to ensure the best possible heat dissipation.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102005010821A DE102005010821B4 (de) | 2005-03-07 | 2005-03-07 | Verfahren zum Herstellen eines Bauelements |
PCT/DE2006/000399 WO2006094487A2 (de) | 2005-03-07 | 2006-03-01 | Verfahren zum herstellen eines bauelements |
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EP1856720A2 true EP1856720A2 (de) | 2007-11-21 |
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EP06722565A Withdrawn EP1856720A2 (de) | 2005-03-07 | 2006-03-01 | Verfahren zum herstellen eines bauelements |
Country Status (4)
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US (1) | US20080048196A1 (de) |
EP (1) | EP1856720A2 (de) |
DE (1) | DE102005010821B4 (de) |
WO (1) | WO2006094487A2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US7557002B2 (en) | 2006-08-18 | 2009-07-07 | Micron Technology, Inc. | Methods of forming transistor devices |
US7989322B2 (en) | 2007-02-07 | 2011-08-02 | Micron Technology, Inc. | Methods of forming transistors |
KR101640830B1 (ko) * | 2009-08-17 | 2016-07-22 | 삼성전자주식회사 | 기판 구조체 및 그 제조 방법 |
FR2976120A1 (fr) | 2011-06-01 | 2012-12-07 | St Microelectronics Sa | Procede de fabrication d'un circuit integre comprenant au moins un guide d'ondes coplanaire |
GB201112327D0 (en) | 2011-07-18 | 2011-08-31 | Epigan Nv | Method for growing III-V epitaxial layers |
CN103117294B (zh) | 2013-02-07 | 2015-11-25 | 苏州晶湛半导体有限公司 | 氮化物高压器件及其制造方法 |
US9048091B2 (en) * | 2013-03-25 | 2015-06-02 | Infineon Technologies Austria Ag | Method and substrate for thick III-N epitaxy |
US9018754B2 (en) | 2013-09-30 | 2015-04-28 | International Business Machines Corporation | Heat dissipative electrical isolation/insulation structure for semiconductor devices and method of making |
JP2016100471A (ja) * | 2014-11-21 | 2016-05-30 | 住友電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
US9793389B1 (en) * | 2016-06-15 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company Limited | Apparatus and method of fabrication for GaN/Si transistors isolation |
DE102017108435A1 (de) * | 2017-04-20 | 2018-10-25 | Osram Opto Semiconductors Gmbh | Halbleiterlaserdiode und Verfahren zur Herstellung einer Halbleiterlaserdiode |
US11749790B2 (en) * | 2017-12-20 | 2023-09-05 | Lumileds Llc | Segmented LED with embedded transistors |
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JP3352712B2 (ja) * | 1991-12-18 | 2002-12-03 | 浩 天野 | 窒化ガリウム系半導体素子及びその製造方法 |
EP1104031B1 (de) * | 1999-11-15 | 2012-04-11 | Panasonic Corporation | Nitrid-Halbleiterlaserdiode und deren Herstellungsverfahren |
DE10041285A1 (de) * | 2000-08-22 | 2002-03-07 | Univ Berlin Tech | Verfahren zur Epitaxie von (Indium, Aluminium, Gallium)-nitrid-Schichten auf Fremdsubstraten |
KR100344103B1 (ko) * | 2000-09-04 | 2002-07-24 | 에피밸리 주식회사 | 질화갈륨계 결정 보호막을 형성한 반도체 소자 및 그 제조방법 |
US7052979B2 (en) * | 2001-02-14 | 2006-05-30 | Toyoda Gosei Co., Ltd. | Production method for semiconductor crystal and semiconductor luminous element |
US7514045B2 (en) * | 2002-01-18 | 2009-04-07 | Avery Dennison Corporation | Covered microchamber structures |
EP1970969B1 (de) * | 2002-05-15 | 2010-02-24 | Panasonic Corporation | Lichtemittierendes Halbleiterelement |
US7115896B2 (en) * | 2002-12-04 | 2006-10-03 | Emcore Corporation | Semiconductor structures for gallium nitride-based devices |
US7009272B2 (en) * | 2002-12-28 | 2006-03-07 | Intel Corporation | PECVD air gap integration |
WO2004064212A1 (ja) * | 2003-01-14 | 2004-07-29 | Matsushita Electric Industrial Co. Ltd. | 窒化物半導体素子及びその製造方法、並びに窒化物半導体基板の製造方法 |
US7045849B2 (en) * | 2003-05-21 | 2006-05-16 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
US20060017064A1 (en) * | 2004-07-26 | 2006-01-26 | Saxler Adam W | Nitride-based transistors having laterally grown active region and methods of fabricating same |
-
2005
- 2005-03-07 DE DE102005010821A patent/DE102005010821B4/de not_active Expired - Fee Related
-
2006
- 2006-03-01 WO PCT/DE2006/000399 patent/WO2006094487A2/de not_active Application Discontinuation
- 2006-03-01 EP EP06722565A patent/EP1856720A2/de not_active Withdrawn
-
2007
- 2007-09-07 US US11/851,909 patent/US20080048196A1/en not_active Abandoned
Non-Patent Citations (1)
Title |
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See references of WO2006094487A3 * |
Also Published As
Publication number | Publication date |
---|---|
WO2006094487A3 (de) | 2006-12-28 |
WO2006094487A2 (de) | 2006-09-14 |
DE102005010821A1 (de) | 2006-09-14 |
DE102005010821B4 (de) | 2007-01-25 |
US20080048196A1 (en) | 2008-02-28 |
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