EP2160762A4 - An interconnect implementing internal controls - Google Patents

An interconnect implementing internal controls

Info

Publication number
EP2160762A4
EP2160762A4 EP08780967A EP08780967A EP2160762A4 EP 2160762 A4 EP2160762 A4 EP 2160762A4 EP 08780967 A EP08780967 A EP 08780967A EP 08780967 A EP08780967 A EP 08780967A EP 2160762 A4 EP2160762 A4 EP 2160762A4
Authority
EP
European Patent Office
Prior art keywords
internal controls
implementing internal
interconnect implementing
interconnect
controls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08780967A
Other languages
German (de)
French (fr)
Other versions
EP2160762A1 (en
Inventor
Drew E Wingard
Chien-Chun Chou
Stephen W Hamilton
Ian Andrew Swarbrick
Vida Vakilotojar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sonics Inc
Original Assignee
Sonics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sonics Inc filed Critical Sonics Inc
Priority to EP10157427.5A priority Critical patent/EP2216722B8/en
Priority to EP11186954.1A priority patent/EP2413355B1/en
Publication of EP2160762A1 publication Critical patent/EP2160762A1/en
Publication of EP2160762A4 publication Critical patent/EP2160762A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Logic Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
EP08780967A 2007-06-25 2008-06-25 An interconnect implementing internal controls Withdrawn EP2160762A4 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP10157427.5A EP2216722B8 (en) 2007-06-25 2008-06-25 Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets
EP11186954.1A EP2413355B1 (en) 2007-06-25 2008-06-25 An interconnect that eliminates routing congestion and manages simultaneous transactions

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US94609607P 2007-06-25 2007-06-25
US12/144,883 US8407433B2 (en) 2007-06-25 2008-06-24 Interconnect implementing internal controls
PCT/US2008/068107 WO2009002998A1 (en) 2007-06-25 2008-06-25 An interconnect implementing internal controls

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP10157427.5A Division EP2216722B8 (en) 2007-06-25 2008-06-25 Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets
EP11186954.1A Division EP2413355B1 (en) 2007-06-25 2008-06-25 An interconnect that eliminates routing congestion and manages simultaneous transactions

Publications (2)

Publication Number Publication Date
EP2160762A1 EP2160762A1 (en) 2010-03-10
EP2160762A4 true EP2160762A4 (en) 2011-01-26

Family

ID=40137732

Family Applications (3)

Application Number Title Priority Date Filing Date
EP08780967A Withdrawn EP2160762A4 (en) 2007-06-25 2008-06-25 An interconnect implementing internal controls
EP10157427.5A Active EP2216722B8 (en) 2007-06-25 2008-06-25 Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets
EP11186954.1A Active EP2413355B1 (en) 2007-06-25 2008-06-25 An interconnect that eliminates routing congestion and manages simultaneous transactions

Family Applications After (2)

Application Number Title Priority Date Filing Date
EP10157427.5A Active EP2216722B8 (en) 2007-06-25 2008-06-25 Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets
EP11186954.1A Active EP2413355B1 (en) 2007-06-25 2008-06-25 An interconnect that eliminates routing congestion and manages simultaneous transactions

Country Status (4)

Country Link
US (6) US9292436B2 (en)
EP (3) EP2160762A4 (en)
JP (2) JP2010531518A (en)
WO (1) WO2009002998A1 (en)

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US8407433B2 (en) 2013-03-26
US20170140800A1 (en) 2017-05-18
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EP2216722B1 (en) 2019-06-19
EP2160762A1 (en) 2010-03-10
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