EP2189901A1 - Method and system to enable fast platform restart - Google Patents
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Abstract
Description
- This invention relates to a platform, and more specifically but not exclusively, to enable fast restart of the platform by minimizing hardware initialization of input / output (IO) devices connected with the platform during the restart of the platform.
- During the operation of a platform, it is highly desirable to have continuous uptime or continuous accessibility of the platform. The ability of the platform to run continuously is important to end users and is especially important to the enterprise because it may affect the operations of the enterprise. The uptime and reliability of a platform is often measured and referred to as the 5 9's, i.e. 99.999% availability. In the enterprise, when a platform is unavailable for greater than 5¼ minutes in one year, it cannot be designated as meeting the 5 9's. The sale of a platform targeted for the enterprise is often determined by the ability of the platform to meet the 5 9's.
- One of the factors affecting the uptime of a platform is the need to restart or reset the platform. When the platform is being restarted, the time taken for the restart is considered as downtime and it affects the availability of the platform. Some of the myriad reasons for the need to restart the platform include reinitializing the operating system (OS) running on the platform due to the loading of new OS drivers, new software or new software patches. The OS may determine that it needs to restart the platform to update its registry keys or to restart the OS environment.
- However, in certain instances, it may not be necessary to restart the whole platform to allow the OS to update its registry keys or to restart the OS environment. In one instance, when there are no hardware changes to the platform and when only software changes to the platform are required, it is not necessary to restart the whole platform and reinitialize all the hardware again. Conventional platforms, however, perform a full platform reset even when there are no hardware changes to the platform and when only software changes to the platform are required.
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Figure 1A depicts a priorart restart sequence 100 of a conventional platform that supports legacy based basic input / output system (BIOS).Timeline 105 shows a time reference of therestart sequence 100. When the conventional platform is powered on attime 0, it enters thephase 110 of early initialization. In thephase 110, the central processing unit (CPU) is powered up and it executes the BIOS code that resides at its reset vector. The BIOS may perform basic checks of the platform such as power on self tests (POST) and memory tests. After the checks are done, the BIOS initiates thenext phase 115 of hardware initialization. The BIOS detects the IO devices connected or plugged in the platform and performs initialization tasks such as peripheral component interconnect (PCI) enumeration, launching option read only memory (ROM) or polling IO devices in thephase 115. - When the
phase 115 of hardware initialization is completed, the OS is launched in thephase 120. During the operation of the platform, a software initiated reset request or a warm reset may be encountered.Phase 125 depicts the platform receiving a warm reset request. On receipt of the warm reset request, the platform performs a full platform reset and enters again thephase 130 of early initialization, thephase 135 of hardware initialization and thephase 140 of launching the OS. - The features and advantages of embodiments of the invention will become apparent from the following detailed description of the subject matter in which:
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Figure 1A depicts a restart sequence of a conventional platform (prior art); -
Figure 1B depicts a restart sequence of a platform in accordance with one embodiment of the invention; -
Figure 2 depicts a boot flow of a platform; -
Figure 3 depicts a restart sequence of a platform in accordance with one embodiment of the invention; -
Figure 4 depicts a flowchart of a platform restart in accordance with one embodiment of the invention; -
Figure 5A depicts a flowchart of a platform restart in accordance with one embodiment of the invention; -
Figure 5B depicts a flowchart of a platform restart in accordance with one embodiment of the invention; -
Figure 6 depicts a system implementing the fast platform restart in accordance with one embodiment of the invention. - Reference in the specification to "one embodiment" or "an embodiment" of the invention means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
- Embodiments of the invention enable a platform to perform a fast reset or restart by minimizing the hardware initialization of IO devices connected with the platform during the restart of the platform. A platform includes, but is not limited to, a server, a desktop computer, a mobile computer, a workstation, or any computing device that can receive a warm reset request to restart the computing device. The platform contains IO devices that include, but are not limited to, hard disk drives, solid state drives, memory modules, processors, chipsets, video display cards, sound cards, compact disc drives, floppy disk drives, or any other IO devices that perform functions for the platform. A warm reset request is a software initiated reset request (SIRR) that is initiated by the OS running on the platform or by a local or a remote user of the platform. An event in the OS that triggers the warm reset in the platform includes, but is not limited to, receiving a reboot or restart request from a local or remote user of the platform and a restart request after the OS installs a new software module or a new software patch.
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Figure 1B depicts arestart sequence 150 of a platform that supports legacy based BIOS in accordance with one embodiment of the invention. Thephase 160 of early initialization is similar to thephase 130 described infigure 1A . In one embodiment, the BIOS of the platform is modified to detect and to trap a warm reset request of the platform. Thephase 160 performs early initialization of basic checks of the platform such as power on self tests (POST) and memory tests. After the checks are done, the modified BIOS initiates thenext phase 165 of hardware initialization. The hardware initialization ofphase 165 is similar to the hardware initialization ofphase 115. - In another embodiment, the BIOS of the platform is modified to save the previous hardware state of some or all of the IO devices connected to the platform in the
phase 165. The hardware state of the IO devices includes, but is not limited to, the register settings of the IO devices, and the configuration settings determined by the BIOS during PCI enumeration. - For example, when the BIOS performs PCI enumeration and detects a hard disk drive connected to the platform, the BIOS requests information from the hard disk drive such as the type of hard disk drive, or the mode (master or slave) of the drive for example. The BIOS determines the optimal settings for the transfer speed based on the information that it gets from the hard disk drive. The optimal settings for the hard disk drive are saved by the modified BIOS so that the optimal settings for the hard disk can be re-programmed during a restart of the platform. By having the optimal settings saved, it avoids the need of the BIOS to request information from the hard disk drive and determine the optimal setting each time the platform is restarted during a warm reset.
- After
phase 165 of hardware initialization completes, the OS is launched inphase 170 and a warm reset request by the OS is sent to the platform inphase 175. Inphase 180 of early initialization, the modified BIOS detects and traps the warm reset request. When the warm reset request is trapped, the modified BIOS converts the warm reset request into a CPU only initialization reset request. By converting the warm reset request into a CPU only initialization reset request, the IO devices in the platform no longer receive a reset request to perform self initialization. The full BIOS code executed inphase 130 offigure 1A is not executed by the CPU inphase 180 offigure 1B . The modified BIOS code ofphase 180 performs a basic CPU initialization and restores the IO devices in the platform to their previous hardware states by reprogramming the IO devices with their previous hardware state saved inphase 165. In one embodiment, the BIOS reprograms the registers of the IO device with the saved register setting of the previous hardware state of the IO device. - After
phase 180 completes, the platform bypasses the conventionalhardware initialization phase 135 and entersphase 190 to re-launch or restart the same version of the OS that was loaded previously inphase 170.Timelines restart sequence 150 as compared to therestart sequence 100. The time required to perform a restart of the platform infigure 1B (phase 180 and phase 190) is shorter than the time required to perform a restart of the platform infigure 1A (phase 130,phase 135 and phase 140). - With a small BIOS code that is executed in
phase 180 of early initialization and minimizing the need of the IO devices in the platform to perform self initialization, the restarting of the platform is performed in a fast manner. The platform offigure 1B does not perform a full platform reset when there are no hardware changes to the platform and when only software changes to the platform are required. Rather, when a warm reset request is received by the platform, only part of the platform necessary for a software event to reinitialize itself is reset. - In one embodiment of the invention, the platform overhead associated with the restarting of the platform is reduced. The minimization of the hardware initialization in the platform is one way of reducing the platform overheads and other methods to reduce the platform overheads can also be performed to allow a fast restart of the platform. A faster restart of the platform yields the ability to ensure more platforms in the enterprise can maintain the 5 9's due to lower platform overhead associated with the installation of software patches and regular maintenance.
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Figure 2 depicts aboot flow 200 of a platform that supports extensible firmware interface (EFI) or unified EFI (UEFI). In one embodiment, the UEFI in the platform is implemented based on Intel® Platform Innovation Framework for EFI and hereinafter referred to as the "Framework". Theboot flow 200 includes, but is not limited to, thephase 201 when the platform is powered on, thephase 202 when the platform is initialized, thephase 203 when the OS is booting, thephase 204 when a warm reset request is received by the OS. Theboot flow 200 goes back to thephase 201 when the platform is restarting. - During the power on
phase 201 of theboot flow 200, the platform enters the security (SEC)phase 210 of the Framework. The pre-verifier 210 handles all platform restart events that includes, but are not to, applying power to the platform from an unpowered state, restarting the platform from an active state and receiving various exception conditions. The next phase in theboot flow 200 is theplatform initialization phase 202. Theplatform initialization phase 202 includes the pre-EFI initialization (PEI)phase 220 and the Driver Execution Environment (DXE)phase 230 of the Framework. - After the
SEC phase 210, thePEI phase 220 configures the platform to meet the minimum prerequisites for theDXE phase 230 of the Framework architecture. During thePEI phase 220, thePEI core 222 initializes key IO devices such as theCPU 224, thechipset 226 and themotherboard 228. ThePEI core 222 also initializes all other key IO devices in the platform that are not shown infigure 2 . After the PEI phase, theEFI driver dispatcher 232 loads the device drivers, bus drivers or serial drivers 236 of the IO devices connected in the platform during theDXE phase 230. Thearchitectural protocols 234 are also loaded at this phase.Elements architectural protocols 246. - After the
DXE phase 230, the boot device select (BDS)phase 240 is entered. Theboot manager 242 determines the mass storage drive to boot an OS for the platform and also which OS to be loaded in the platform when multiple operating systems are present or installed in the platform. Theboot flow 200 enters the OS boot phase and the platform enters the transient system load (TSL)phase 250 of the Framework. Theboot manager 242 loads the transient OS boot loader 256 and the transient OS boot loader 256 starts thetransient OS environment 254. OSabsent applications 252 may be launched by thetransient OS environment 254. The finalOS boot loader 258 is launched after the transient OS boot loader 256 is completed. - In one embodiment, the
boot manager 242 is modified to load the image of the final OS loader twice and to copy the image into a cache. In other embodiments, theboot manager 242 loads the final OS boot loader twice and saves the first copy of the final OS boot loader image as an unaltered memory based source and launches the second copy of the final OS boot loader image. In other embodiments, a part image or a whole image of the OS may also be copied as an unaltered memory based source to allow restoration of the part or whole image of the OS. - The platform enters the run time (RT) phase when the final
OS boot loader 258 initiates thefinal OS environment 262 and executes OSpresent applications 264. When a warm reset request is received by the OS during the RT phase, theboot flow 200 goes back to the power onphase 201 to restart the platform and enters again theplatform initialization 202 phase and theOS boot phase 203. -
Figure 3 depict arestart sequence 300 of a platform in accordance with one embodiment of the invention. The platform receives awarm reset request 304 from the OS. In one embodiment, thewarm reset request 304 is followed from theboot flow 200. The platform enters the power onphase 301 when the warm reset request is received. The pre-verifier 312 is modified to detect and trap any warm reset request. The pre-verifier 312 is also modified to convert the warm reset into a CPU only initialization reset request when the warm reset is trapped. - When the pre-verifier 312 detects the
warm reset 304, it traps thewarm reset 304 and converts thewarm reset 304 into a CPU only initialization reset request. The platform initializes the CPU and the pre-verifier restores the IO devices in the platform to their previous hardware states. In one embodiment, the pre-verifier calls the block_IO.reset function of the Framework that restores each IO device to a known state. Therestart sequence 300 avoids theplatform initialization phase 302 and thePEI phase 320 andDXE phase 330 are not executed as the IO devices in the platform are restored by the pre-verifier 312 to a known hardware state or its previous hardware state. - The steps of executing the
PEI core 322, of initializing theCPU 324,chipset 326 and themotherboard 328 are not performed and they are represented by dashed lines. In addition, theEFI driver dispatcher 332, device drivers 336 and thearchitectural protocols 334 are not re-loaded and they are also represented by dashed lines. The pre-verifier 312 calls theboot manager 342 in theBDS phase 340. In one embodiment, theboot manager 342 restores the finalOS boot loader 358 with the copy of the final OS boot loader image saved during theBDS phase 340. In other embodiments, theboot manager 342 may also be modified to load additional images from the boot disk of the platform to speed up the restart of the platform. - The steps of executing the transient
OS boot loader 356, thetransient OS environment 354, and the OS absentapplications 352 are not performed as the previous OS loader image is used and they are represented as dashed lines. The finalOS boot loader 358 is executed using the copy of the final OS boot loader image saved during theBDS phase 340 and thefinal OS environment 362 and OSpresent applications 364 are executed in theRT phase 360. -
Figure 4 depicts a flow diagram of the restart sequence of a platform in accordance to one embodiment of the invention. Atstep 405, a warm reset request is received by the OS running on the platform. In some embodiments, the warm reset request to restart the platform is triggered by an installation of an application in the OS or is triggered by a local or remote user of the platform. The OS initiates the transition of the platform into a power off state. In some embodiments, the OS initiates the transition of the platform into system power state 5 (S5). - In
step 410, the platform starts to perform a shutdown of the OS and the OS flushes the dirty data in the OS to a mass storage device. The mass storage device includes, but is not limited to, a hard disk drive, a fast flash drive, a solid state memory, universal serial bus (USB) drive, or any form of data storage means for the platform. No write back to the mass storage device is performed. In one embodiment, the dirty data is flushed to a write back (WB) cache. - After the dirty data is flushed in
step 410, the OS shutdowns and triggers a warm reset instep 415. In one embodiment, the warm reset is triggered by writing to an onboard keyboard controller via port 64h to perform a warm reset of the platform. Instep 420, the platform executes a custom fast restart flow through the BIOS. In one embodiment, the customfast restart flow 420 is performed by the modifiedBIOS 180 discussed infigure 1B . In other embodiments, the customfast restart flow 420 is performed by the pre-verifier 312 discussed infigure 3 . Both the modifiedBIOS 180 andpre-verifier 312 detects and traps the warm reset request and converts the warm reset into a CPU only initialization reset request. The IO devices in the platform are restored to a previous hardware state by the modifiedBIOS 180 orpre-verifier 312. - In
step 425, the modified BIOS issues an interrupt 19h (hex) to load the OS. In another embodiment, the pre-verifier launchesboot manager 342 to restore the OS boot loader with a copy of the previous OS loader image. The OS boot loader hits a fast flash drive by issuing an interrupt 13h (hex) instep 430. The OS is booted using native drivers instep 435 and the OS restart completes instep 440. -
Figure 5A illustrates the flowchart of the restart sequence of a platform that supports legacy based BIOS or the Framework according to one embodiment of the invention. Instep 502, the platform enters an early initialization phase and the CPU and memory of the platform are powered up. The CPU executes the BIOS code that resides at its reset vector and performs basic checks of the platform such as power on self tests (POST) and memory tests. Instep 504, the flow checks if fast restart of the platform is supported. If no, the flow goes through normal hardware initialization of the platform instep 508. During the normal hardware initialization, IO devices connected or plugged in the platform are detected and tasks such as peripheral component interconnect (PCI) enumeration, launching option read only memory (ROM) or polling IO devices are executed. If yes, the flow checks if the current hardware configuration of the platform is different from the platform's previous hardware configuration atstep 506. - If the hardware configuration is changed, the flow goes to step 508 to perform normal initialization of the platform. If the hardware configuration is not changed, the flow goes to step 510 to detect if there is a warm reset request. If yes, the flow goes to step 5B.
Step 5B is discussed infigure 5B . If no, the flow goes to step 512 to perform normal initialization of the platform. In one embodiment, thesteps BIOS 180 discussed infigure 1B . In another embodiment, thesteps pre-verifier 312 offigure 3 . Step 512 of normal initialization is executed during thePEI 320 phase and theDXE 330 phase. Althoughsteps - After
step 512, the flow goes to step 514 to check if the platform supports legacy based BIOS. If yes, the flow goes to step 518 to copy the data in the legacy based BIOS memory region of the platform into a buffer. The data in the legacy based BIOS memory region includes, but is not limited to, data in the BIOS data area (BDA) and data in the extended BIOS data area (EBDA). In one embodiment, the buffer is indicated as unavailable to the OS or to an OS loader in a memory map of the platform. In another embodiment, the copied data is prefixed with a signature and placed at a particular memory granularity of the buffer such that it is discoverable by the platform. - If the platform does not support legacy based BIOS in
step 514, the flow goes to step 516. Step 516 loads the OS loader twice and saves the first copy of the OS loader image as an unaltered memory based source and launches the second copy of the OS loader image. In other embodiments, a part image or a whole image of the OS may also be copied as an unaltered memory based source to allow restoration of the part or whole image of the OS. Instep 520, the flow checks if the OS loader is attempting to transition into runtime. If no, the flow continues the OS initialization of the platform instep 522. If yes, the flow maintains the boot services memory to facilitate ability of the platform to retain its firmware infrastructure during the restart of the platform instep 524. - In one embodiment, the
steps boot manager 342 in the BDS phase of a platform that supports EFI or the Framework. The boot manager does not deconstruct the boot services memory when it receives a call to the function ExitBootServices of the Framework. Fromsteps step 526. Instep 528, the flow receives a reset and goes back to step 502 to perform early initialization of the platform. -
Figure 5B illustrates the flowchart whenstep 510 detect that there is a warm reset request. In one embodiment, thesteps BIOS 180 discussed infigure 1B . In another embodiment, thesteps pre-verifier 312 offigure 3 . Instep 552, the modifiedBIOS 180 orpre-verifier 312 detects and traps the warm reset request. The modifiedBIOS 180 or pre-verifier 312 also converts the warm reset request into a CPU only initialization reset request. The CPU is initialized to its previous state or to a known state. Instep 554, the flow checks if the platform supports legacy based BIOS. If yes, the modifiedBIO 180 switches the CPU of the platform into real mode and reprograms the advanced programmable interrupt controller (APIC) instep 556. The modifiedBIOS 180 restores the legacy based BIOS memory region to its previous values using the copied data of its previous values instep 518. Instep 558 the modified BIOS 18 initiates a boot strap loader via interrupt 19h (hex) to launch the OS to restart the platform. - If the platform does not supports legacy based BIOS and supports EFI or the Framework, the pre-verifier 312 switches the CPU of the platform into protected mode and reprograms the advanced programmable interrupt controller (APIC) in
step 560. The pre-verifier 312 instep 562 restores the IO devices in the platform to their previous hardware state or to a known state. In one embodiment, the pre-verifier 312 calls a block_io reset function of the Framework that reset each IO device to a known state or previous hardware state. The block_io reset function may be implemented for each IO device or implemented collectively for all IO devices. - In
step 564, the OS loader of the platform is restored with the copy of the previous OS loader image saved instep 516. The OS is launched with the OS loader image saved instep 516. Althoughstep 564 restores only the OS loader image, in other embodiments,step 564 may restore other images that allow the platform to restart in a fast manner.Step step 5A. Althoughflowcharts -
Figure 6 illustrates a block diagram of asystem 600 to implement the methods disclosed herein according to an embodiment. Thesystem 600 includes but is not limited to, a desktop computer, a laptop computer, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, an Internet appliance or any other type of computing device. In another embodiment, thesystem 600 used to implement the methods disclosed herein may be a system on a chip (SOC) system. - The
system 600 includes achipset 635 with amemory controller 630 and an input/output (I/O)controller 640. A chipset typically provides memory and I/O management functions, as well as a plurality of general purpose and/or special purpose registers, timers, etc. that are accessible or used by aprocessor 625. Theprocessor 625 may be implemented using one or more processors. - The
memory controller 630 performs functions that enable theprocessor 625 to access and communicate with amain memory 615 that includes avolatile memory 610 and anon-volatile memory 620 via abus 665. In one embodiment of the invention, the modifiedBIOS 180 is stored in thenon-volatile memory 620. In other embodiment of the invention, the pre-verifier 312 is stored in thenon-volatile memory 620. - The
volatile memory 610 includes but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Thenon-volatile memory 620 includes but is not limited by, flash memory, Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and/or any other desired type of memory device. -
Memory 615 stores information and instructions to be executed by theprocessor 625.Memory 615 may also stores temporary variables or other intermediate information while theprocessor 625 is executing instructions. - The
system 600 includes but is not limited to, aninterface circuit 655 that is coupled withbus 665. Theinterface circuit 655 is implemented using any type of well known interface standard including, but is not limited to, an Ethernet interface, a universal serial bus (USB), a third generation input/output interface (3GIO) interface, and/or any other suitable type of interface. - One or
more input devices 645 are connected to theinterface circuit 655. The input device(s) 645 permit a user to enter data and commands into theprocessor 625. For example, the input device(s) 645 is implemented using but is not limited to, a keyboard, a mouse, a touch-sensitive display, a track pad, a track ball, and/or a voice recognition system. - One or
more output devices 650 connect to theinterface circuit 655. For example, the output device(s) 650 are implemented using but are not limited to, light emitting displays (LEDs), liquid crystal displays (LCDs), cathode ray tube (CRT) displays, printers and/or speakers). Theinterface circuit 655 includes a graphics driver card. - The
system 600 also includes one or moremass storage devices 660 to store software and data. Examples of such mass storage device(s) 660 include but are not limited to, floppy disks and drives, hard disk drives, fast flash disk drives, solid state hard drives, compact disks and drives, and digital versatile disks (DVD) and drives. - The
interface circuit 655 includes a communication device such as a modem or a network interface card to facilitate exchange of data with external computers via a network. The communication link between thesystem 600 and the network may be any type of network connection such as an Ethernet connection, a digital subscriber line (DSL), a telephone line, a cellular telephone system, a coaxial cable, etc. - Access to the input device(s) 645, the output device(s) 650, the mass storage device(s) 660 and/or the network is typically controlled by the I/
O controller 640 in a conventional manner. In particular, the I/O controller 640 performs functions that enable theprocessor 625 to communicate with the input device(s) 645, the output device(s) 650, the mass storage device(s) 660 and/or the network via thebus 665 and theinterface circuit 655. - While the components shown in Figure 16 are depicted as separate blocks within the
system 600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although thememory controller 630 and the I/O controller 640 are depicted as separate blocks within thechipset 635, one of ordinary skill in the relevant art will readily appreciate that thememory controller 630 and the I/O controller 640 may be integrated within a single semiconductor circuit. - Although examples of the embodiments of the disclosed subject matter are described, one of ordinary skill in the relevant art will readily appreciate that many other methods of implementing the disclosed subject matter may alternatively be used. For example, the order of execution of the blocks in the flow diagrams may be changed, and/or some of the blocks in block/flow diagrams described may be changed, eliminated, or combined.
- In the preceding description, various aspects of the disclosed subject matter have been described. For purposes of explanation, specific numbers, systems and configurations were set forth in order to provide a thorough understanding of the subject matter. However, it is apparent to one skilled in the relevant art having the benefit of this disclosure that the subject matter may be practiced without the specific details. In other instances, well-known features, components, or modules were omitted, simplified, combined, or split in order not to obscure the disclosed subject matter.
- Various embodiments of the disclosed subject matter may be implemented in hardware, firmware, software, or combination thereof, and may be described by reference to or in conjunction with program code, such as instructions, functions, procedures, data structures, logic, application programs, design representations or formats for simulation, emulation, and fabrication of a design, which when accessed by a machine results in the machine performing tasks, defining abstract data types or low-level hardware contexts, or producing a result.
- While the disclosed subject matter has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the subject matter, which are apparent to persons skilled in the art to which the disclosed subject matter pertains are deemed to lie within the scope of the disclosed subject matter.
Claims (15)
- A method to restart a platform comprising:trapping a software initiated reset request (SIRR) of the platform;restoring an input/output (IO) device coupled with the platform to a previous hardware state responsive to the trapping; andlaunching an operating system (OS) to restart the platform responsive to the restoration.
- The method of claim 1 further comprising:initializing the platform;converting the SIRR into a central processing unit (CPU) only initialization reset request when the SIRR is trapped; andinitializing the CPU responsive to the conversion.
- The method of claim 2, wherein initializing the platform comprises at least one of saving at least one register setting of the previous hardware state of the IO device, of saving a copy of a previous OS loader image, wherein a basic IO system (BIOS) of the platform supports extensible firmware interface (EFI), of determining that an OS loader of the platform is attempting to transition into runtime; and maintaining boot services memory to facilitate ability of the platform to retain its firmware infrastructure during the restart of the platform, wherein a basic IO system (BIOS) of the platform supports extensible firmware interface (EFI), and of copying data associated with a legacy based basic IO system (BIOS) memory region of the platform into a buffer, wherein the buffer is indicated as unavailable to the OS or to an OS loader in a memory map.
- The method of claim 3, wherein restoring the input/output (IO) device comprises reprogramming each of the at least one register of the IO device with the saved register setting of the previous hardware state of the IO device.
- The method of claim 4 further comprising at least one of restoring an OS loader of the platform with the copy of the previous OS loader image, and of restoring the legacy based BIOS memory region of the platform with the copied data; and initiating a boot strap loader to launch the OS to restart the platform.
- An article comprising: a computer readable medium having instructions stored thereon which, when executed, cause a processor to restart a platform by performing the following method:trapping a software initiated reset request (SIRR) of the platform;restoring an input/output (IO) device coupled with the platform to a previous hardware state responsive to the trapping; andlaunching an operating system (OS) to restart the platform responsive to the restoration.
- The article of claim 6 further comprising:initializing the platform;converting the SIRR into a central processing unit (CPU) only initialization reset request when the SIRR is trapped; andinitializing the CPU responsive to the conversion.
- The article of claim 7, wherein initializing the platform comprises at least one of saving at least one register setting of the previous hardware state of the IO device, of saving a copy of a previous OS loader image, wherein a basic IO system (BIOS) of the platform supports extensible firmware interface (EFI), of determining that an OS loader of the platform is attempting to transition into runtime; and maintaining boot services memory to facilitate ability of the platform to retain its firmware infrastructure during the restart of the platform, wherein a basic IO system (BIOS) of the platform supports extensible firmware interface (EFI), and of copying data associated with a legacy based basic IO system (BIOS) memory region of the platform into a buffer, wherein the buffer is indicated as unavailable to the OS or to an OS loader in a memory map.
- The article of claim 8, wherein restoring the input/output (IO) device comprises reprogramming each of the at least one register of the IO device with the saved register setting of the previous hardware state of the IO device.
- The article of claim 6 further comprising at least one of restoring an OS loader of the platform with the copy of the previous OS loader image, and of restoring the legacy based BIOS memory region of the platform with the copied data; and initiating a boot strap loader to launch the OS to restart the platform.
- A platform comprising:an input/output (IO) device coupled with the platform;an operating system (OS) coupled with the platform; anda basic input/output system (BIOS) module coupled with the IO device to:trap a software initiated reset request (SIRR) of the OS;restore the IO device to a previous hardware state responsive to the trapping; andlaunch the OS to restart the platform responsive to the restoration.
- The platform of claim 11 further comprising a central processing unit (CPU) coupled with the platform and wherein the BIOS module is further to:initialize the platform;convert the SIRR into a CPU only initialization reset request when the SIRR is trapped; andinitialize the CPU responsive to the conversion.
- The platform of claim 12, wherein the BIOS module to initialize the platform comprises at least one of saving at least one register setting of the previous hardware state of the IO device, of saving a copy of a previous OS loader image, wherein the BIOS module supports extensible firmware interface (EFI), of determining that an OS loader of the platform is attempting to transition into runtime; and maintain boot services memory to facilitate ability of the platform to retain its firmware infrastructure during the restart of the platform, wherein the BIOS module supports extensible firmware interface (EFI), and of copying data associated with a legacy based BIOS memory region of the platform into a buffer, wherein the buffer is indicated as unavailable to the OS or to an OS loader in a memory map.
- The platform of claim 13, wherein the BIOS module to restore the IO device is to reprogram each of the at least one register of the IO device with the saved register setting of the previous hardware state of the IO device.
- The platform of claim 11, wherein the BIOS module is further to restore an OS loader of the platform with the copy of the previous OS loader image or to restore the legacy based BIOS memory region of the platform with the copied data; and initiate a boot strap loader to launch the OS to restart the platform.
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EP2189901B1 (en) | 2019-06-26 |
CN101814035B (en) | 2013-09-04 |
JP5368947B2 (en) | 2013-12-18 |
JP2010123125A (en) | 2010-06-03 |
CN101814035A (en) | 2010-08-25 |
US8296553B2 (en) | 2012-10-23 |
US20100125723A1 (en) | 2010-05-20 |
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