EP2849225A3 - System and method for providing a redistribution metal layer in an integrated circuit - Google Patents

System and method for providing a redistribution metal layer in an integrated circuit Download PDF

Info

Publication number
EP2849225A3
EP2849225A3 EP14191744.3A EP14191744A EP2849225A3 EP 2849225 A3 EP2849225 A3 EP 2849225A3 EP 14191744 A EP14191744 A EP 14191744A EP 2849225 A3 EP2849225 A3 EP 2849225A3
Authority
EP
European Patent Office
Prior art keywords
metal layer
integrated circuit
providing
passivation layer
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP14191744.3A
Other languages
German (de)
French (fr)
Other versions
EP2849225A2 (en
Inventor
Danielle A Thomas
Harry Michael Siegel
Antonio A Do Bento Vieira
Anthony M Chiu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of EP2849225A2 publication Critical patent/EP2849225A2/en
Publication of EP2849225A3 publication Critical patent/EP2849225A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05546Dual damascene structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base

Abstract

A method for fabricating an integrated circuit comprising: fabricating a first portion of an active circuit area and an associated metal pad on a base substrate; depositing a passivation layer above the first portion of the active circuit area and above the metal pad, wherein at least portions of an upper surface of the passivation layer is nonplanar; etching at least one via through the passivation layer to the metal pad; etching a metal layer pattern into the passivation layer; and depositing a metal layer onto the metal layer pattern in the passivation layer to form a redistribution metal layer
EP14191744.3A 2002-03-06 2003-03-06 System and method for providing a redistribution metal layer in an integrated circuit Withdrawn EP2849225A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/091,743 US7096581B2 (en) 2002-03-06 2002-03-06 Method for providing a redistribution metal layer in an integrated circuit
EP03251346.7A EP1351294B1 (en) 2002-03-06 2003-03-06 System and method for providing a redistribution metal layer in an integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP03251346.7A Division EP1351294B1 (en) 2002-03-06 2003-03-06 System and method for providing a redistribution metal layer in an integrated circuit

Publications (2)

Publication Number Publication Date
EP2849225A2 EP2849225A2 (en) 2015-03-18
EP2849225A3 true EP2849225A3 (en) 2015-04-01

Family

ID=27787738

Family Applications (2)

Application Number Title Priority Date Filing Date
EP14191744.3A Withdrawn EP2849225A3 (en) 2002-03-06 2003-03-06 System and method for providing a redistribution metal layer in an integrated circuit
EP03251346.7A Expired - Lifetime EP1351294B1 (en) 2002-03-06 2003-03-06 System and method for providing a redistribution metal layer in an integrated circuit

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP03251346.7A Expired - Lifetime EP1351294B1 (en) 2002-03-06 2003-03-06 System and method for providing a redistribution metal layer in an integrated circuit

Country Status (3)

Country Link
US (3) US7096581B2 (en)
EP (2) EP2849225A3 (en)
JP (1) JP4401089B2 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002100254A2 (en) 2001-06-12 2002-12-19 Pelikan Technologies, Inc. Method and apparatus for lancet launching device integrated onto a blood-sampling cartridge
US7015590B2 (en) * 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
KR100541396B1 (en) * 2003-10-22 2006-01-11 삼성전자주식회사 Method For Forming Solder Bump Structure Having Three-Dimensional UBM
US7208843B2 (en) * 2005-02-01 2007-04-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Routing design to minimize electromigration damage to solder bumps
US7253528B2 (en) 2005-02-01 2007-08-07 Avago Technologies General Ip Pte. Ltd. Trace design to minimize electromigration damage to solder bumps
KR100642643B1 (en) * 2005-03-18 2006-11-10 삼성전자주식회사 Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits
DE102005041283B4 (en) * 2005-08-31 2017-12-14 Globalfoundries Inc. Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device
FR2894716A1 (en) * 2005-12-09 2007-06-15 St Microelectronics Sa INTEGRATED CIRCUIT CHIP WITH EXTERNAL PLATES AND METHOD OF MANUFACTURING SUCH CHIP
US7635643B2 (en) * 2006-04-26 2009-12-22 International Business Machines Corporation Method for forming C4 connections on integrated circuit chips and the resulting devices
US8212357B2 (en) * 2008-08-08 2012-07-03 International Business Machines Corporation Combination via and pad structure for improved solder bump electromigration characteristics
US20110156260A1 (en) * 2009-12-28 2011-06-30 Yu-Hua Huang Pad structure and integrated circuit chip with such pad structure
US8269348B2 (en) * 2010-02-22 2012-09-18 Texas Instruments Incorporated IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch
US8362612B1 (en) * 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8951833B2 (en) * 2011-06-17 2015-02-10 Wafertech, Llc Defect free deep trench method for semiconductor chip
US8426984B2 (en) * 2011-09-13 2013-04-23 Chipbond Technology Corporation Substrate structure with compliant bump and manufacturing method thereof
US9362243B2 (en) * 2014-05-21 2016-06-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and forming the same
US10008461B2 (en) * 2015-06-05 2018-06-26 Micron Technology, Inc. Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
US10366958B2 (en) 2017-12-28 2019-07-30 Texas Instruments Incorporated Wire bonding between isolation capacitors for multichip modules

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037664A (en) * 1997-08-20 2000-03-14 Sematech Inc Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
GB2364170A (en) * 1999-12-16 2002-01-16 Lucent Technologies Inc Dual damascene bond pad structure for lowering stress and allowing circuitry under pads

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4723197A (en) * 1985-12-16 1988-02-02 National Semiconductor Corporation Bonding pad interconnection structure
US4990464A (en) * 1988-12-30 1991-02-05 North American Philips Corp. Method of forming improved encapsulation layer
JPH0661498A (en) * 1992-08-05 1994-03-04 Nec Corp Non-volatile semiconductor storage
US6262438B1 (en) * 1996-11-04 2001-07-17 Semiconductor Energy Laboratory Co., Ltd. Active matrix type display circuit and method of manufacturing the same
KR100295240B1 (en) * 1997-04-24 2001-11-30 마찌다 가쯔히꼬 Semiconductor device
US6025277A (en) * 1997-05-07 2000-02-15 United Microelectronics Corp. Method and structure for preventing bonding pad peel back
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6218302B1 (en) * 1998-07-21 2001-04-17 Motorola Inc. Method for forming a semiconductor device
US6762115B2 (en) * 1998-12-21 2004-07-13 Megic Corporation Chip structure and process for forming the same
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
SG93278A1 (en) * 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
US6500750B1 (en) * 1999-04-05 2002-12-31 Motorola, Inc. Semiconductor device and method of formation
US6803302B2 (en) * 1999-11-22 2004-10-12 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a mechanically robust pad interface
US6380555B1 (en) * 1999-12-24 2002-04-30 Micron Technology, Inc. Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor components
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6180445B1 (en) * 2000-04-24 2001-01-30 Taiwan Semiconductor Manufacturing Company Method to fabricate high Q inductor by redistribution layer when flip-chip package is employed
US6407002B1 (en) * 2000-08-10 2002-06-18 Taiwan Semiconductor Manufacturing Company Partial resist free approach in contact etch to improve W-filling
US6551856B1 (en) * 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW584950B (en) * 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
US7115998B2 (en) * 2002-08-29 2006-10-03 Micron Technology, Inc. Multi-component integrated circuit contacts

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037664A (en) * 1997-08-20 2000-03-14 Sematech Inc Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
GB2364170A (en) * 1999-12-16 2002-01-16 Lucent Technologies Inc Dual damascene bond pad structure for lowering stress and allowing circuitry under pads

Also Published As

Publication number Publication date
EP1351294B1 (en) 2014-11-05
US7096581B2 (en) 2006-08-29
US7786582B2 (en) 2010-08-31
EP1351294A3 (en) 2006-09-27
US20060234423A1 (en) 2006-10-19
JP4401089B2 (en) 2010-01-20
JP2004031912A (en) 2004-01-29
US20030167632A1 (en) 2003-09-11
US8163645B2 (en) 2012-04-24
US20100297841A1 (en) 2010-11-25
EP2849225A2 (en) 2015-03-18
EP1351294A2 (en) 2003-10-08

Similar Documents

Publication Publication Date Title
EP2849225A3 (en) System and method for providing a redistribution metal layer in an integrated circuit
EP1439576A3 (en) Through hole manufacturing method
WO2003098688A3 (en) Structural design of under bump metallurgy for high reliability bumped packages
EP1160856A3 (en) Flip chip type semiconductor device and method of manufacturing the same
WO2004059808A3 (en) Methods of forming semiconductor devices including mesa structures and multiple passivation layers and related devices
EP1933376A3 (en) Transfer material, method for producing the same and wiring substrate produced by using the same
EP1263062A3 (en) Organic semiconductor device and process of manufacturing the same
EP0898308A3 (en) A method for forming a metal interconnection in a semiconductor device
EP1333494A3 (en) Semiconductor device and method of fabricating a semiconductor assembly
EP1267398A3 (en) Barrier cap for under bump metal
EP1109226A3 (en) Semiconductor device and its manufacturing method capable of reducing low frequency noise
EP1388902A3 (en) Fabricating method of Gunn diode
EP1513170A3 (en) A spiral inductor formed in a semiconductor substrate and a method for forming the inductor
EP1317000A3 (en) Semiconductor device having leadless package structure
EP0924756A3 (en) Method of encapsulating a wire bonded die
EP1517364A4 (en) Semiconductor device and its producing method
EP0855737A3 (en) Integrated processing for an etch module using a hard mask technique
TW200501377A (en) Under bump metallurgy structure
MY140980A (en) Semiconductor package
EP1148543A3 (en) Semiconductor device and process of manufacturing the same
EP2192616A3 (en) Quantum semiconductor device and method for fabricating the same
EP1316998A3 (en) Bumpless Chip Scale Device (CSP) and board assembly
EP1313143A3 (en) Perimeter anchored thick film pad
TW200503194A (en) Ball grid array package substrate and method for manufacturing the same
EP1387394A3 (en) Process of final passivation of integrated circuit devices

Legal Events

Date Code Title Description
PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20141104

AC Divisional application: reference to earlier application

Ref document number: 1351294

Country of ref document: EP

Kind code of ref document: P

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/60 20060101ALI20150226BHEP

Ipc: H01L 23/31 20060101ALI20150226BHEP

Ipc: H01L 23/485 20060101AFI20150226BHEP

RIN1 Information on inventor provided before grant (corrected)

Inventor name: DO BENTO VIEIRA, ANTONIO A

Inventor name: CHIU, ANTHONY M

Inventor name: THOMAS, DANIELLE A

Inventor name: SIEGEL, HARRY MICHAEL

R17P Request for examination filed (corrected)

Effective date: 20150930

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB IT

17Q First examination report despatched

Effective date: 20160912

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20170124