US20010000013A1 - High performance sub-system design and assembly - Google Patents
High performance sub-system design and assembly Download PDFInfo
- Publication number
- US20010000013A1 US20010000013A1 US09/729,152 US72915200A US2001000013A1 US 20010000013 A1 US20010000013 A1 US 20010000013A1 US 72915200 A US72915200 A US 72915200A US 2001000013 A1 US2001000013 A1 US 2001000013A1
- Authority
- US
- United States
- Prior art keywords
- integrated circuit
- circuit chip
- chip
- test
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- This invention relates to structures and methods of assembly of integrated circuit chips into interconnected multiple chip circuits. More particularly, this invention relates to “chip-on-chip” structures connected physically and electrically.
- DRAM embedded Dynamic Random Access Memory
- a “chip-on-chip” structure is a viable alternative to embedded DRAM. With multiple chips connected in intimate contact, the process parameters that maximize the performance of the DRAM chip and the logic gates can be applied during manufacture.
- FIG. 1 for a description of a “chip-on-chip” structure 100 .
- Such a “chip-on-chip” structure is described in U.S. Pat. No. 5,534,465 (Frye et al.).
- a first integrated circuit chip 105 is attached physically and electrically to a second integrated circuit chip 110 by means of an area array of solder bumps 115 .
- the process of forming an area array of solder bumps 115 is well known in the art and is discussed in Frye et al. 465.
- the second chip 110 is then secured physically to a substrate 120 .
- Electrical connections 125 between the second integrated circuit chip 110 and external circuitry are created as either wire bonds or tape automated bonds.
- the module further has a ball grid array 130 to secure the structure to a next level of packaging containing the external circuitry.
- an encasing material 135 is placed over the “chip-on-chip” structure 100 to provide environmental protection for the “chip-on-chip” 100 .
- U.S. Pat. No. 5,481,205 (Frye et al.) teaches a structure for making temporary connections to integrated circuit chips having “solder bumps” or connection structures such as ball grid arrays. The temporary connections allow temporary contacting of the integrated circuit chip during testing of the integrated circuit chip.
- ESD electrostatic discharge
- U.S. Pat. No. 5,731,945 and U.S. Pat. No. 5,807,791 teach a method for fabricating programmable ESD protection circuits for multichip semiconductor structures.
- the interchip interface circuit on each integrated circuit chip is formed with an ESD protection circuit and a switch to selectively connect the ESD protection circuit to an input/output pad. This allows multiple identical chips to be interconnected and redundant ESD protection removed.
- circuits at the periphery of integrated circuit chips generally are specialized to meet the requirements standardized specifications. These include relatively high current and voltage drivers and receivers for communicating on relatively long transmission line media. Alternately, as shown in U.S. Pat. No. 5,461,333 (Condon et al.) the interface may be differential to allow lower voltages on the transmission line media. This requires two input/output pads for transfer of signals.
- U.S. Pat. No. 5,818,748 (Bertin et al.) illustrates a separation of chip function onto separate integrated circuits chips. This allows the optimization of the circuits.
- EEPROM is on one integrated circuits chip and drivers and decoders are on another. The chips are placed face to face and secured with force responsive self-interlocking micro-connectors.
- FIGS. 2 a and 2 b show multiple “chip-on-chip” structures 100 constructed on a wafer. Not shown is the forming of the first integrated circuit chip on a silicon wafer. The first integrated circuit chip is tested on the wafer and nonfunctioning chips are identified. The wafer is separated into the individual chips. The functioning first integrated circuit chips 105 then are “flip-chip” mounted on the second integrated circuit chip 110 on the wafer 200 . The wafer 200 is then separated into the “chip-on-chip” structures 100 . The “chip-on-chip” structures 100 are then mounted on the modules as above described.
- An object of this invention is to provide a multiple integrated circuit chip structure where the interchip communication between integrated circuit chips of the structure have no ESD protection circuits and no input/output circuitry.
- the interchip communication is between internal circuits with a minimal electrical load.
- Another object of this invention is to provide a circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with test systems during assembly and test.
- a multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted a second integrated circuit chip to physically and electrically connect the first integrated circuit chip to the second integrated circuit chip.
- the first integrated circuit chip may be mounted to the second integrated circuit chip by means of an area array of solder bumps.
- the first integrated circuit chip has interchip interface circuits connected to the second integrated circuit chip to communicate between internal circuits of the first and second integrated circuit chips and test circuits.
- the test circuits are connected to the internal circuits of the first integrated circuit chip to provide stimulus and response to the internal circuits during testing procedures.
- the second integrated circuit chip has input/output interface circuitry to communicate with external circuitry connected to the second integrated circuit chip and to protect the second integrated circuit chip from electrostatic discharge voltages. Further, the second integrated circuit has interchip interface circuits connected to the first integrated circuit chip to communicate between the internal circuits of the first and second integrated circuit chips, and with test circuits. The test circuits are connected to the internal circuits of the second integrated circuit chip to provide stimulus to and response from the internal circuits during testing and burn-in procedures.
- the interchip interface circuitry has an internal interface circuit for transferring electrical signals between the internal circuits of the second integrated circuit chip to the first integrated circuit chip.
- the interchip interface circuitry further has a mode select switch to selectively connect between the internal circuits of the first integrated circuits chip and the second integrated circuits chip or to the test interface circuits.
- the mode switch has three terminals and a control terminal. The first terminal is connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry, and the third terminal connected to test circuits.
- a mode selector is connected to the control terminal. The state of the mode selector determines the connection between the first terminal and thus the output of the internal interface circuit, the second terminal and thus the internal circuitry, and the third terminal and thus the test interface.
- the first terminal is connected to the second terminal such that the internal circuits of the first and second integrated circuits are connected through their respective internal interfaces.
- the internal circuits are connected to the test circuits.
- the test circuits are formed of a test interface circuit and an ESD protection device.
- the test interface circuit connected to communicate test signals from external test circuitry to the first and second integrated circuit chips.
- the ESD protection device protects the first and second integrated circuit chips from electrostatic discharge voltages.
- the test interface circuit is connected to the external test circuitry through an input/output pad temporarily connected to the external test circuitry during test and burn-in.
- the first integrated circuit chip could be fabricated using a first type of semiconductor process and the second integrated circuit chip would be fabricated with a second type of semiconductor process that is not compatible with the first type of semiconductor process.
- the first integrated circuit chip could be an array of memory cells and the second integrated circuit chip would contain electronic circuitry formed with a process not compatible with a process of the array of memory cells.
- the second integrated circuit chip is an array of memory cells and the first integrated circuit chip contains electronic circuitry formed with a process not compatible with a process of the array of memory cells.
- FIG. 1 shows a cross-sectional view of a “chip-on-chip” structure of the prior art.
- FIGS. 2 a and 2 b are respectively top view and a cross-sectional view of a “chip-on-chip” structure formed on a semiconductor wafer of the prior art.
- FIG. 3 is a cross-sectional view of a “chip-on-chip” structure, schematically the circuitry contained on each chip of the chip-on-chip structure of this invention.
- FIGS. 4 a-d are schematics of the interchip interface circuits of this invention.
- FIGS. 5 a and 5 b are schematic drawings of an embodiment of the interchip interface of this invention.
- FIGS. 6 a and 6 b are top surface views of the first and second integrated circuit chips of FIG. 3 showing test pads and interchip input/output pads of this invention.
- a “chip-on-chip” structure 300 is shown in FIG. 3.
- a first integrated circuit chip 305 is attached to a second integrated circuit chip 310 by means of an area array of solder bumps 315 as described above.
- the second integrated circuit chip 310 is secured physically to the module 320 .
- the electrical connections 325 are either wire bonds or TAB bonds.
- the module 320 has a ball grid array 330 to attach the “chip-on-chip” structure within the module to a next level of electronic package.
- the first integrated circuit chip 305 has internal circuits 335 , which are the functional electronic components of the first integrated circuit chip 305 .
- the internal circuits 335 may be DRAM, logic, or other integrated circuits.
- the second integrated circuit chip 310 has the internal circuits 365 .
- the internal circuits 365 are the functional electronic components of the second integrated circuit chips 310 . These internal circuits also may be DRAM, logic, or other integrated circuits.
- the internal circuits 335 are connected to the interchip interface circuits 340 .
- the interchip interface circuits 340 are connected through the input/output pads 345 to the area array of solder bumps 315 and thus to the second chip 310 . This connection is functional during normal operation, when the first integrated circuit chip 305 is mounted to the second integrated circuit chip 310 .
- the interchip interface circuit 340 also is connected to the test interface 350 .
- the test interface circuit 350 is connected to the test input/output pads 355 .
- the test interface circuit 350 is functionally active during testing procedures, when test system probes are brought in contact with the test input/output pads 355 .
- the test system probes provide test stimuli and receive response from the internal circuits 335 .
- the mode select 390 for the first integrated circuit chip 305 is accomplished by placing an appropriate logic level on the mode select input/output pads 391 and 392 .
- the mode select input/output pad 391 is brought to a first logic level ( 0 ) to cause the interchip interface circuit 340 to transfer signals between the internal circuits 335 and the test interface 350 .
- the test signals are then transferred between the test interface 350 and the test input/output pad 355 as described above.
- the mode select line 390 is brought to a second logic level ( 1 ) through the mode select input/output pad 392 .
- the second logic level ( 1 ) is a voltage equal to the power supply voltage source V DD and is achieved by connecting the mode select input output pad 392 to the mode select input/output pad 393 on the second integrated circuit chip 310 through the solder ball 394 .
- the mode select input/output pad 393 is connected directly to the power supply voltage source V DD to achieve the second logic level ( 1 ).
- the interchip interface 340 transfers signals of the internal circuits 335 to the input/output pads 345 to the second integrated circuit chip 310 as described above.
- the internal circuits 365 of the second integrated circuit chip 310 likewise are connected to the interchip interface circuits 360 .
- the interchip interface circuits 360 are connected to the input/output pads 370 and thus to the first integrated circuit chip 310 through the area array of solder bumps 315 .
- the interchip interface circuits 360 are connected to the test interface circuits 375 .
- the internal circuits 365 of the second integrated circuit chip 310 are connected to the input/output interface 385 .
- the input/output interface is connected to the input/output pad 395 , which is connected to the module 320 through the bondwire 325 .
- the input/output interface provides the circuitry to transfer signals between the internal circuits 365 and the external circuits attached through the next packaging level to the ball grid array 330 and thus to the wirebond 325 .
- the second integrated circuit chip 310 is tested prior to separation of a wafer containing the second integrated circuit chip 310 , by bringing test probes or needles of the test system in contact with the input/output pads 395 and the test input/output pads 377 . Subsequent to dicing of the wafer into individual second integrated circuit chips 310 , the individual second integrated circuit chips 310 are mounted in a burn-in apparatus. The burn-in apparatus again is brought in contact with the input/output pads 395 and the test input/output pads 377 to provide stressing signals to the circuits of the second integrated circuit chip 310 .
- the mode select 380 for the second integrated circuit chip 310 is accomplished by placing an appropriate logic level on the mode select input/output pads 381 and 382 .
- the mode select input/output pad 381 is brought to a first logic level ( 0 ) to cause the interchip interface circuit 360 to transfer signals between the internal circuits 365 and the test interface 375 .
- the test signals are then transferred between the test interface 375 and the test input/output pad 377 as described above.
- the mode select line 380 is brought to a second logic level ( 1 ) through the mode select input/output pad 382 .
- the second logic level ( 1 ) is achieved by connecting the mode select input output pad 382 to the mode select input/output pad 383 on the second integrated circuit chip 310 through the solder ball 384 .
- the mode select input/output pad 383 is connected directly to the power supply voltage source V DD to achieve the second logic level ( 1 ).
- the interchip interface 360 transfers signals of the internal circuits 365 to the input/output pads 370 to the first integrated circuit chip 305 as described above.
- the input/output interface circuit 385 has an input/output buffer 389 connected to the internal circuits 365 .
- the input/output buffer 389 is either a driver or receiver necessary to translate the signal levels of the internal circuits 365 to the signal levels of the external circuits and the signal levels of the external circuits to the signal levels of the internal circuit 365 .
- the input/output buffer is connected to the input/output pad 395 and to the ESD protection circuit 387 .
- the ESD protection circuit 387 clamps excess ESD voltages to prevent damage to the input/output buffer 389 and the internal circuits 365 from ESD voltages brought in contact with the input/output pad 395 from the external environment.
- FIGS. 4 a and 4 d show schematically the connections of the interchip interface 340 and the test interface 350 of the first integrated circuit chip 305 of FIG. 3.
- FIG. 4 a illustrates a path of a signal originated within the internal circuits 400 of the first integrated circuit chip and
- FIG. 4 d illustrates a path of a signal originated externally and received by the internal circuits 462 of the first integrated circuit chip.
- the interchip interface 340 is comprised of a mode switch 402 and a mode selector 404 .
- the signal 400 originating from the internal circuit of the first integrated circuit chip is connected to a first terminal of the mode switch 402 .
- the second terminal of the mode switch 402 is connected directly to an input/output pad of the first integrated circuit chip and thus to the internal circuits of the second integrated circuit chip, as described above.
- the third terminal of the mode switch 402 is connected to the test interface 350 .
- the test interface circuit 350 is composed of the test circuit 406 connected to an input of a driver circuit 410 .
- the output of the driver circuit is connected to a test input/output pad 412 and to the ESD protection circuit 414 .
- the ESD protection circuit 414 operates as the ESD protection circuit 387 of FIG. 3 and clamps excessive ESD voltage to protect the test interface circuit 350 from damage during handling of the wafer containing the first integrated circuit chip for manufacturing, assembly, and testing.
- the control terminal of the mode switch 402 is connected to a mode selector 404 to control the function of the interchip interface 340 .
- the mode selector 404 When the mode selector 404 is at a first logic state, the internal circuits 400 of the first integrated circuit chip are connected to the input/output 408 and thus to the internal circuits of the second integrated circuit chip.
- the mode selector 404 When the mode selector 404 is at a second logic state, the internal circuits 400 of the first integrated circuit chip are connected to the test interface circuit 350 .
- the mode selector 404 is set to the second state during the testing procedures of the wafer containing the first integrated circuit chip. Conversely, when the mode selector 404 is set to the first logic state during the normal operation of the “chip-on-chip” structure.
- the signals originating in the internal circuits of the second integrated circuit chip are transferred to the chip pad 454 of the first integrated circuit.
- the chip pad 454 is connected to the first terminal of the mode switch 456 .
- the test interface circuit 350 is connected to the second terminal of the mode switch 456 .
- the third terminal of the mode switch 456 is connected to the internal circuits 462 of the first integrated circuit chip.
- the control terminal of the mode switch 456 is connected to the mode selector 458 to control the function of the interchip interface 340 . If the control terminal of the mode switch 458 is at the first logic state, the chip pad 454 of the first integrated circuit chip and thus internal circuits of the second integrated circuit chip are connected to the internal circuits of the first integrated circuit chip. Conversely, if the control terminal of the mode switch 458 is at the second logic state, the test interface circuit 350 is connected to the internal circuit of the first integrated circuit chip.
- the mode selector 458 is set to the second logic state during the testing procedures of the wafer containing the first integrated circuit chip and the mode selector 458 is set to the first logic state during the normal operation of the “chip-on-chip” structure.
- FIGS. 4 b and 4 c show schematically the connections of the interchip interface 360 and the test interface 375 of the second integrated circuit chip 310 of FIG. 3.
- FIG. 4 b illustrates a path of a signal originated within the internal circuits 430 of the second integrated circuit chip and
- FIG. 4 c illustrates a path of a signal originated externally and received by the internal circuits 432 of the second integrated circuit chip.
- FIG. 4 b shows the instance where the signals originate on the first integrated circuit chip and are transferred through to the input/output pad 422 of the second integrated circuit chip.
- the input/output pad 422 is connected to the first terminal of the mode switch 424 .
- the test interface circuit 375 is connected to the second terminal of the mode switch 424 .
- the third terminal of the mode switch 424 is connected to the internal circuits 430 of the second integrated circuit chip.
- the control terminal of the mode switch 424 is connected to the mode selector 426 , which operates as described above. If the mode selector 426 is at the first logic state, the signals from the internal circuit of the first integrated circuit chip are connected through the input/output pad 422 to the internal circuits 430 of the second integrated circuit chip.
- the mode selector is at the second logic state, the test signals from an external test system are transferred through the test interface 350 to the internal circuits 430 of the second integrated circuit chip.
- the mode selector 426 is set to the first logic state during normal operation and is set to the second logic state during testing procedures.
- the test interface is similar to that described in FIG. 4 d .
- the test signals originating in an external test system are applied to a test input/output pad 416 .
- the test input/output pad 416 is connected to a receiver 420 an ESD protection circuit 418 .
- the receiver 420 translates the test signals to signal levels acceptable by the test circuit 428 and the internal circuits 430 of the second integrated circuit chip.
- the ESD protection circuit 418 clamps ESD voltages applied to the test pad 416 to prevent damage to the second integrated circuit chip.
- the test circuits 428 format the test signals for application to the internal circuits 436 of the second integrated circuit chip.
- FIG. 4 c shows the instance where the signals originate in the internal circuits 432 of the second integrated circuit chip and are transferred through chip pad 438 to the first integrated circuit chip.
- the first terminal of the mode switch 436 receives the signals from the internal circuits 432 of the second integrated circuit chip.
- the second terminal of the mode switch 436 is connected to the chip pad 438 .
- the third terminal is connected to the test interface 375 .
- the control terminal is connected to the mode selector 434 .
- the mode selector 434 determines the connection of the internal circuits 432 to either the chip pad 438 or the test interface circuit 375 . If the mode selector 434 is at the first logic state, the internal circuits 432 are connected through the chip pad 438 to the internal circuits of the first integrated circuit chip. Alternately, if the mode selector 434 is set to the second logic state, the internal circuits 432 are connected to the test interface circuit 375 .
- the mode selector 434 is set to the first logic state during normal system operation and to the second logic state during testing procedures.
- FIGS. 5 a and 5 b illustrate the structure of an embodiment of the mode switch and the mode selector shown in FIGS. 3 and 4 a-d .
- FIG. 5 a shows the mode switch 500 and mode selector 520 for signals originated from the internal circuits 508 from the first or second integrated circuit chips.
- FIG. 5 b shows the mode switch 500 and mode selector 520 for signals originated externally and transferred to the internal circuits 508 of the first or second integrated circuit chips.
- the first terminal of the mode switch 500 is connected to the internal circuits 508 , the second terminal of the mode switch 500 is connected to the test interface circuit 510 and the third terminal of the mode switch 500 is connected to the interchip input/output pad 530 .
- the mode switch is comprised of the pass switches 502 and 504 and inverter 506 .
- the pass switch 502 is the parallel combination of the n-channel metal oxide semiconductor (NMOS) transistor 502 a and p-channel metal oxide semiconductor (PMOS) transistor 502 b .
- the pass switch 504 is the parallel combination of the NMOS transistor 504 a and the PMOS transistor 504 b .
- the first terminal of the mode switch 500 and thus the internal circuits 508 are connected to the drains of the pass switches 502 and 504 .
- the sources of the pass switch 502 are connected to the third terminal of the mode switch 500 and thus to the interchip input/output pad 530 .
- the sources of the pass switch 504 are connected to the second terminal of the mode switch 500 and thus to the test interface circuit 510 .
- the gates of the NMOS transistor 504 a and the PMOS transistor 502 b are connected to the output of the inverter 506 .
- the gates of the NMOS transistor 502 a , PMOS transistor 504 b , and the input of the inverter 506 are connected to the control terminal of the mode switch 500 and thus to the mode selector 520 .
- the control terminal of the mode switch 500 When the control terminal of the mode switch 500 is at the first logic state, in this case a voltage level approaching that of the power supply voltage source V DD , the pass switch 502 is turned on and the pass switch 504 is turned off, This effectively connects the internal circuits 508 to the interchip input/output pad 530 . In this logic state, the extra electrical load is from the drain of the pass switch 502 and the pass switch 504 . This electrical load is very small and thus highly improved performance can be expected over the prior art. Conversely, when the control terminal of the mode switch 500 is at the second logic state, in this case a voltage level approaching that of the substrate biasing voltage source V SS , the pass switch 504 is turned on and the pass switch 502 is turned off. The internal circuits are now effectively connected to the test interface circuit 510 .
- the test interface circuit 510 is comprised of the test circuit 512 , the driver circuit 514 , and the ESD protection circuit 516 .
- the test interface circuit functions as described in FIGS. 4 a and 4 c.
- the mode select circuit is the interchip input/output pad 522 and the test input/output pad 524 connected together and to the control terminal of the mode switch 500 .
- the interchip input/output pad 522 is connected as described in FIG. 3 to a mating interchip input/output pad 562 that are joined by a solder bump or ball.
- the mating interchip input/output pad 562 is on the mating chip 560 and is connected to the power supply voltage source V DD to provide the first logic state to the control terminal of the mode switch 500 during normal operation.
- the test input/output pad is connected to the test system 550 during the testing procedures. During the test procedures, a test probe or needle 552 is brought in contact with the test input/output pad.
- the test probe or needle 552 is connected on a probe card 554 within the test system 550 to the substrate biasing voltage source V SS to provide the second logic state to the control terminal of the mode switch 500 .
- the test interface circuit 510 in this case is comprised of the test circuits 512 , the receiver 518 , and the ESD protection circuit and functions as described in FIGS. 4 b and 4 d.
- test signals originating from the external circuits are applied to the interchip input/output pad 530 and transferred through the pass switch 502 to the internal circuits 508 during normal operation. Likewise, the test signals are transferred from the test interface 510 through the pass switch 504 to the internal circuits 508 during the test procedures.
- FIG. 6 a shows a top surface view of the first integrated circuit chip 600 illustrating the placement of the test input/output pads 605 and the interchip input/output pads 610 .
- the interchip input/output pads 610 form an area array of solder bails or bumps 315 of FIG. 3.
- the test input/output pads 605 are peripherally arranged so that the test probes or needles of the test system can conveniently make contact with the test input/output pads 605 .
- FIG. 6 b shows the top surface view of the second integrated circuit chip 615 illustrating the placement of the interchip input/output pads 625 and the external input/output pads 620 .
- the interchip input/output pads 625 form the area array to mate with the interchip input/output pads 610 of FIG. 5 a .
- the first integrated circuit chip 600 is mounted “face-to face” to the second integrated circuit chip 615 .
- the test input/output pads 605 must have nothing on the surface of the second integrated circuit chip 625 in their “shadow.”
- the test input/output pads 630 and the external input/output pads 620 are formed in the periphery of the second integrated circuit chip 615 .
- the external input/output pads 620 must be placed outside the shadow of the first integrated circuit chip 600 .
- the test input/output pads 630 are placed conveniently so that test probes or needles of a test system can contact the test input/output pads 630 .
- the test input/output pads 605 and 630 are connected as shown in FIGS. 5 a and 5 b to the test interface 510 .
- the test input/output pads 605 and 630 transfer stimulus and response signals between the test system 550 and either the first integrated circuit chip 600 or second integrated circuit chip 615 .
Abstract
Description
- 1. 1. Field of the Invention
- 2. This invention relates to structures and methods of assembly of integrated circuit chips into interconnected multiple chip circuits. More particularly, this invention relates to “chip-on-chip” structures connected physically and electrically.
- 3. 2. Description of the Related Art
- 4. The manufacture of embedded Dynamic Random Access Memory (DRAM) requires that process parameters that enhance the performance of the logic or the DRAM, if separately formed on semiconductor chips, be compromised when DRAM is embedded into an array of logic gates on the same semiconductor chip. This compromise has limited the application of embedded DRAM. If there is no compromise in the process parameters to enhance the performance of logic or the DRAM embedded DRAM, the manufacture process becomes very complicated and costly. Moreover, because of the structure of the embedded DRAM and the logic, burn-in of the embedded DRAM is not possible and embedding of DRAM with logic is not a reliable design solution.
- 5. A “chip-on-chip” structure is a viable alternative to embedded DRAM. With multiple chips connected in intimate contact, the process parameters that maximize the performance of the DRAM chip and the logic gates can be applied during manufacture. Refer to FIG. 1 for a description of a “chip-on-chip”
structure 100. Such a “chip-on-chip” structure is described in U.S. Pat. No. 5,534,465 (Frye et al.). A first integratedcircuit chip 105 is attached physically and electrically to a second integratedcircuit chip 110 by means of an area array ofsolder bumps 115. The process of forming an area array ofsolder bumps 115 is well known in the art and is discussed in Frye et al. 465. Thesecond chip 110 is then secured physically to a substrate 120.Electrical connections 125 between the second integratedcircuit chip 110 and external circuitry (not shown) are created as either wire bonds or tape automated bonds. The module further has aball grid array 130 to secure the structure to a next level of packaging containing the external circuitry. Generally, anencasing material 135 is placed over the “chip-on-chip”structure 100 to provide environmental protection for the “chip-on-chip” 100. - 6. U.S. Pat. No. 5,481,205 (Frye et al.) teaches a structure for making temporary connections to integrated circuit chips having “solder bumps” or connection structures such as ball grid arrays. The temporary connections allow temporary contacting of the integrated circuit chip during testing of the integrated circuit chip.
- 7. The handling of wafers from which the integrated circuit chips are formed and the handling of the integrated circuit chip themselves causes the integrated circuit chips to be subjected to electrostatic discharge (ESD) voltages. Even though connections between the first integrated
circuit chip 105 and the second integratedcircuit chip 110 are relatively short and under normal operation would not be subjected to ESD voltages, require ESD protection circuitry to be formed within the interchip interface circuit to provide protection or necessary driving capacity for the first integratedcircuit chip 105 and the second integratedcircuit chip 110 during burn-in and other manufacturing monitoring processes. - 8. U.S. Pat. No. 5,731,945 and U.S. Pat. No. 5,807,791 (Bertin et al.) teach a method for fabricating programmable ESD protection circuits for multichip semiconductor structures. The interchip interface circuit on each integrated circuit chip is formed with an ESD protection circuit and a switch to selectively connect the ESD protection circuit to an input/output pad. This allows multiple identical chips to be interconnected and redundant ESD protection removed.
- 9. The circuits at the periphery of integrated circuit chips generally are specialized to meet the requirements standardized specifications. These include relatively high current and voltage drivers and receivers for communicating on relatively long transmission line media. Alternately, as shown in U.S. Pat. No. 5,461,333 (Condon et al.) the interface may be differential to allow lower voltages on the transmission line media. This requires two input/output pads for transfer of signals.
- 10. U.S. Pat. No. 5,818,748 (Bertin et al.) illustrates a separation of chip function onto separate integrated circuits chips. This allows the optimization of the circuits. In this case, EEPROM is on one integrated circuits chip and drivers and decoders are on another. The chips are placed face to face and secured with force responsive self-interlocking micro-connectors.
- 11.FIGS. 2a and 2 b show multiple “chip-on-chip”
structures 100 constructed on a wafer. Not shown is the forming of the first integrated circuit chip on a silicon wafer. The first integrated circuit chip is tested on the wafer and nonfunctioning chips are identified. The wafer is separated into the individual chips. The functioning first integratedcircuit chips 105 then are “flip-chip” mounted on the second integratedcircuit chip 110 on thewafer 200. Thewafer 200 is then separated into the “chip-on-chip”structures 100. The “chip-on-chip”structures 100 are then mounted on the modules as above described. - 12. An object of this invention is to provide a multiple integrated circuit chip structure where the interchip communication between integrated circuit chips of the structure have no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits with a minimal electrical load.
- 13. Another object of this invention is to provide a circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with test systems during assembly and test.
- 14. To accomplish these and other objects, a multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted a second integrated circuit chip to physically and electrically connect the first integrated circuit chip to the second integrated circuit chip. The first integrated circuit chip may be mounted to the second integrated circuit chip by means of an area array of solder bumps. The first integrated circuit chip has interchip interface circuits connected to the second integrated circuit chip to communicate between internal circuits of the first and second integrated circuit chips and test circuits. The test circuits are connected to the internal circuits of the first integrated circuit chip to provide stimulus and response to the internal circuits during testing procedures.
- 15. The second integrated circuit chip has input/output interface circuitry to communicate with external circuitry connected to the second integrated circuit chip and to protect the second integrated circuit chip from electrostatic discharge voltages. Further, the second integrated circuit has interchip interface circuits connected to the first integrated circuit chip to communicate between the internal circuits of the first and second integrated circuit chips, and with test circuits. The test circuits are connected to the internal circuits of the second integrated circuit chip to provide stimulus to and response from the internal circuits during testing and burn-in procedures.
- 16. The interchip interface circuitry has an internal interface circuit for transferring electrical signals between the internal circuits of the second integrated circuit chip to the first integrated circuit chip. The interchip interface circuitry further has a mode select switch to selectively connect between the internal circuits of the first integrated circuits chip and the second integrated circuits chip or to the test interface circuits. The mode switch has three terminals and a control terminal. The first terminal is connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry, and the third terminal connected to test circuits. A mode selector is connected to the control terminal. The state of the mode selector determines the connection between the first terminal and thus the output of the internal interface circuit, the second terminal and thus the internal circuitry, and the third terminal and thus the test interface. During normal operation, the first terminal is connected to the second terminal such that the internal circuits of the first and second integrated circuits are connected through their respective internal interfaces. During test and burn-in, the internal circuits are connected to the test circuits.
- 17. The test circuits are formed of a test interface circuit and an ESD protection device. The test interface circuit connected to communicate test signals from external test circuitry to the first and second integrated circuit chips. The ESD protection device protects the first and second integrated circuit chips from electrostatic discharge voltages. The test interface circuit is connected to the external test circuitry through an input/output pad temporarily connected to the external test circuitry during test and burn-in.
- 18. The first integrated circuit chip could be fabricated using a first type of semiconductor process and the second integrated circuit chip would be fabricated with a second type of semiconductor process that is not compatible with the first type of semiconductor process. As an example, the first integrated circuit chip could be an array of memory cells and the second integrated circuit chip would contain electronic circuitry formed with a process not compatible with a process of the array of memory cells. Alternatively, the second integrated circuit chip is an array of memory cells and the first integrated circuit chip contains electronic circuitry formed with a process not compatible with a process of the array of memory cells. Fabricating the first integrated circuit chip using its optimum semiconductor process, fabricating the second integrated circuit chip using its optimum semiconductor process, and then joining the first and second integrated circuit chips by this invention creates a multiple chip integrated circuit structure having maximum performance with minimum cost.
- 19.FIG. 1 shows a cross-sectional view of a “chip-on-chip” structure of the prior art.
- 20.FIGS. 2a and 2 b are respectively top view and a cross-sectional view of a “chip-on-chip” structure formed on a semiconductor wafer of the prior art.
- 21.FIG. 3 is a cross-sectional view of a “chip-on-chip” structure, schematically the circuitry contained on each chip of the chip-on-chip structure of this invention.
- 22.FIGS. 4 a-d are schematics of the interchip interface circuits of this invention.
- 23.FIGS. 5a and 5 b are schematic drawings of an embodiment of the interchip interface of this invention.
- 24.FIGS. 6a and 6 b are top surface views of the first and second integrated circuit chips of FIG. 3 showing test pads and interchip input/output pads of this invention.
- 25. A “chip-on-chip”
structure 300 is shown in FIG. 3. A firstintegrated circuit chip 305 is attached to a secondintegrated circuit chip 310 by means of an area array of solder bumps 315 as described above. The secondintegrated circuit chip 310 is secured physically to themodule 320. Theelectrical connections 325 are either wire bonds or TAB bonds. Themodule 320 has aball grid array 330 to attach the “chip-on-chip” structure within the module to a next level of electronic package. - 26. The first
integrated circuit chip 305 hasinternal circuits 335, which are the functional electronic components of the firstintegrated circuit chip 305. Theinternal circuits 335 may be DRAM, logic, or other integrated circuits. Likewise, the secondintegrated circuit chip 310 has theinternal circuits 365. Theinternal circuits 365 are the functional electronic components of the second integrated circuit chips 310. These internal circuits also may be DRAM, logic, or other integrated circuits. To transfer signals between theinternal circuits 335 of the firstintegrated circuit chip 305 and theinternal circuits 365 of thesecond chip 310 or to an external test system, theinternal circuits 335 are connected to theinterchip interface circuits 340. Theinterchip interface circuits 340 are connected through the input/output pads 345 to the area array of solder bumps 315 and thus to thesecond chip 310. This connection is functional during normal operation, when the firstintegrated circuit chip 305 is mounted to the secondintegrated circuit chip 310. - 27. The
interchip interface circuit 340 also is connected to thetest interface 350. Thetest interface circuit 350 is connected to the test input/output pads 355. Thetest interface circuit 350 is functionally active during testing procedures, when test system probes are brought in contact with the test input/output pads 355. The test system probes provide test stimuli and receive response from theinternal circuits 335. - 28. The mode select 390 for the first
integrated circuit chip 305 is accomplished by placing an appropriate logic level on the mode select input/output pads integrated circuit chip 305 is in contact with a test system during wafer testing or die testing during burn-in, the mode select input/output pad 391 is brought to a first logic level (0) to cause theinterchip interface circuit 340 to transfer signals between theinternal circuits 335 and thetest interface 350. The test signals are then transferred between thetest interface 350 and the test input/output pad 355 as described above. - 29. When the first
integrated circuit chip 305 is mounted to the secondintegrated circuit chip 310, the modeselect line 390 is brought to a second logic level (1) through the mode select input/output pad 392. The second logic level (1) is a voltage equal to the power supply voltage source VDD and is achieved by connecting the mode selectinput output pad 392 to the mode select input/output pad 393 on the secondintegrated circuit chip 310 through thesolder ball 394. The mode select input/output pad 393 is connected directly to the power supply voltage source VDD to achieve the second logic level (1). When the modeselect line 390 is at the second logic level (1), theinterchip interface 340 transfers signals of theinternal circuits 335 to the input/output pads 345 to the secondintegrated circuit chip 310 as described above. - 30. The
internal circuits 365 of the secondintegrated circuit chip 310 likewise are connected to theinterchip interface circuits 360. Theinterchip interface circuits 360 are connected to the input/output pads 370 and thus to the firstintegrated circuit chip 310 through the area array of solder bumps 315. Theinterchip interface circuits 360 are connected to thetest interface circuits 375. - 31. The
internal circuits 365 of the secondintegrated circuit chip 310 are connected to the input/output interface 385. The input/output interface is connected to the input/output pad 395, which is connected to themodule 320 through thebondwire 325. The input/output interface provides the circuitry to transfer signals between theinternal circuits 365 and the external circuits attached through the next packaging level to theball grid array 330 and thus to thewirebond 325. - 32. The second
integrated circuit chip 310 is tested prior to separation of a wafer containing the secondintegrated circuit chip 310, by bringing test probes or needles of the test system in contact with the input/output pads 395 and the test input/output pads 377. Subsequent to dicing of the wafer into individual secondintegrated circuit chips 310, the individual secondintegrated circuit chips 310 are mounted in a burn-in apparatus. The burn-in apparatus again is brought in contact with the input/output pads 395 and the test input/output pads 377 to provide stressing signals to the circuits of the secondintegrated circuit chip 310. Then, when the firstintegrated circuit chip 305 is mounted to the secondintegrated circuit chip 310, operation of the whole “chip-on-chip”assembly 300 is verified by attaching testing probes or contacts to theball grid array 330. Signals from the testing probes are transferred between the circuits of the whole “chip-on-chip”assembly 300 through thebond wires 325 to the input/output pads 395. - 33. The mode select 380 for the second
integrated circuit chip 310 is accomplished by placing an appropriate logic level on the mode select input/output pads integrated circuit chip 310 is in contact with a test system during wafer testing or die testing during burn-in, the mode select input/output pad 381 is brought to a first logic level (0) to cause theinterchip interface circuit 360 to transfer signals between theinternal circuits 365 and thetest interface 375. The test signals are then transferred between thetest interface 375 and the test input/output pad 377 as described above. - 34. When the first
integrated circuit chip 305 is mounted to the secondintegrated circuit chip 310, the modeselect line 380 is brought to a second logic level (1) through the mode select input/output pad 382. The second logic level (1) is achieved by connecting the mode selectinput output pad 382 to the mode select input/output pad 383 on the secondintegrated circuit chip 310 through the solder ball 384. The mode select input/output pad 383 is connected directly to the power supply voltage source VDD to achieve the second logic level (1). When the modeselect line 380 is at the second logic level (1), theinterchip interface 360 transfers signals of theinternal circuits 365 to the input/output pads 370 to the firstintegrated circuit chip 305 as described above. - 35. The input/
output interface circuit 385 has an input/output buffer 389 connected to theinternal circuits 365. The input/output buffer 389 is either a driver or receiver necessary to translate the signal levels of theinternal circuits 365 to the signal levels of the external circuits and the signal levels of the external circuits to the signal levels of theinternal circuit 365. The input/output buffer is connected to the input/output pad 395 and to theESD protection circuit 387. TheESD protection circuit 387 clamps excess ESD voltages to prevent damage to the input/output buffer 389 and theinternal circuits 365 from ESD voltages brought in contact with the input/output pad 395 from the external environment. - 36.FIGS. 4a and 4 d show schematically the connections of the
interchip interface 340 and thetest interface 350 of the firstintegrated circuit chip 305 of FIG. 3. FIG. 4a illustrates a path of a signal originated within theinternal circuits 400 of the first integrated circuit chip and FIG. 4d illustrates a path of a signal originated externally and received by theinternal circuits 462 of the first integrated circuit chip. - 37. Referring now to FIG. 4a, the
interchip interface 340 is comprised of amode switch 402 and amode selector 404. Thesignal 400 originating from the internal circuit of the first integrated circuit chip is connected to a first terminal of themode switch 402. The second terminal of themode switch 402 is connected directly to an input/output pad of the first integrated circuit chip and thus to the internal circuits of the second integrated circuit chip, as described above. The third terminal of themode switch 402 is connected to thetest interface 350. Thetest interface circuit 350 is composed of thetest circuit 406 connected to an input of adriver circuit 410. - 38. The output of the driver circuit is connected to a test input/
output pad 412 and to theESD protection circuit 414. TheESD protection circuit 414 operates as theESD protection circuit 387 of FIG. 3 and clamps excessive ESD voltage to protect thetest interface circuit 350 from damage during handling of the wafer containing the first integrated circuit chip for manufacturing, assembly, and testing. - 39. The control terminal of the
mode switch 402 is connected to amode selector 404 to control the function of theinterchip interface 340. When themode selector 404 is at a first logic state, theinternal circuits 400 of the first integrated circuit chip are connected to the input/output 408 and thus to the internal circuits of the second integrated circuit chip. When themode selector 404 is at a second logic state, theinternal circuits 400 of the first integrated circuit chip are connected to thetest interface circuit 350. Themode selector 404 is set to the second state during the testing procedures of the wafer containing the first integrated circuit chip. Conversely, when themode selector 404 is set to the first logic state during the normal operation of the “chip-on-chip” structure. - 40. Referring to FIG. 4d, the signals originating in the internal circuits of the second integrated circuit chip are transferred to the
chip pad 454 of the first integrated circuit. Thechip pad 454 is connected to the first terminal of themode switch 456. Thetest interface circuit 350 is connected to the second terminal of themode switch 456. The third terminal of themode switch 456 is connected to theinternal circuits 462 of the first integrated circuit chip. The control terminal of themode switch 456 is connected to themode selector 458 to control the function of theinterchip interface 340. If the control terminal of themode switch 458 is at the first logic state, thechip pad 454 of the first integrated circuit chip and thus internal circuits of the second integrated circuit chip are connected to the internal circuits of the first integrated circuit chip. Conversely, if the control terminal of themode switch 458 is at the second logic state, thetest interface circuit 350 is connected to the internal circuit of the first integrated circuit chip. - 41. As described above, the
mode selector 458 is set to the second logic state during the testing procedures of the wafer containing the first integrated circuit chip and themode selector 458 is set to the first logic state during the normal operation of the “chip-on-chip” structure. - 42.FIGS. 4b and 4 c show schematically the connections of the
interchip interface 360 and thetest interface 375 of the secondintegrated circuit chip 310 of FIG. 3. FIG. 4b illustrates a path of a signal originated within theinternal circuits 430 of the second integrated circuit chip and FIG. 4c illustrates a path of a signal originated externally and received by theinternal circuits 432 of the second integrated circuit chip. - 43.FIG. 4b shows the instance where the signals originate on the first integrated circuit chip and are transferred through to the input/
output pad 422 of the second integrated circuit chip. The input/output pad 422 is connected to the first terminal of themode switch 424. Thetest interface circuit 375 is connected to the second terminal of themode switch 424. The third terminal of themode switch 424 is connected to theinternal circuits 430 of the second integrated circuit chip. The control terminal of themode switch 424 is connected to themode selector 426, which operates as described above. If themode selector 426 is at the first logic state, the signals from the internal circuit of the first integrated circuit chip are connected through the input/output pad 422 to theinternal circuits 430 of the second integrated circuit chip. Alternately, if the mode selector is at the second logic state, the test signals from an external test system are transferred through thetest interface 350 to theinternal circuits 430 of the second integrated circuit chip. Again, as described above, themode selector 426 is set to the first logic state during normal operation and is set to the second logic state during testing procedures. - 44. The test interface is similar to that described in FIG. 4d. The test signals originating in an external test system are applied to a test input/
output pad 416. The test input/output pad 416 is connected to areceiver 420 anESD protection circuit 418. Thereceiver 420 translates the test signals to signal levels acceptable by thetest circuit 428 and theinternal circuits 430 of the second integrated circuit chip. - 45. The
ESD protection circuit 418 clamps ESD voltages applied to thetest pad 416 to prevent damage to the second integrated circuit chip. Thetest circuits 428 format the test signals for application to theinternal circuits 436 of the second integrated circuit chip. - 46.FIG. 4c shows the instance where the signals originate in the
internal circuits 432 of the second integrated circuit chip and are transferred throughchip pad 438 to the first integrated circuit chip. The first terminal of themode switch 436 receives the signals from theinternal circuits 432 of the second integrated circuit chip. The second terminal of themode switch 436 is connected to thechip pad 438. The third terminal is connected to thetest interface 375. The control terminal is connected to themode selector 434. - 47. As described above, the
mode selector 434 determines the connection of theinternal circuits 432 to either thechip pad 438 or thetest interface circuit 375. If themode selector 434 is at the first logic state, theinternal circuits 432 are connected through thechip pad 438 to the internal circuits of the first integrated circuit chip. Alternately, if themode selector 434 is set to the second logic state, theinternal circuits 432 are connected to thetest interface circuit 375. - 48. The
mode selector 434 is set to the first logic state during normal system operation and to the second logic state during testing procedures. - 49.FIGS. 5a and 5 b illustrate the structure of an embodiment of the mode switch and the mode selector shown in FIGS. 3 and 4a-d. FIG. 5a shows the
mode switch 500 andmode selector 520 for signals originated from theinternal circuits 508 from the first or second integrated circuit chips. Alternately, FIG. 5b shows themode switch 500 andmode selector 520 for signals originated externally and transferred to theinternal circuits 508 of the first or second integrated circuit chips. - 50. Referring now to FIG. 5a, the first terminal of the
mode switch 500 is connected to theinternal circuits 508, the second terminal of themode switch 500 is connected to thetest interface circuit 510 and the third terminal of themode switch 500 is connected to the interchip input/output pad 530. - 51. The mode switch is comprised of the pass switches 502 and 504 and
inverter 506. Thepass switch 502 is the parallel combination of the n-channel metal oxide semiconductor (NMOS)transistor 502 a and p-channel metal oxide semiconductor (PMOS)transistor 502 b. Likewise, thepass switch 504 is the parallel combination of theNMOS transistor 504 a and thePMOS transistor 504 b. The first terminal of themode switch 500 and thus theinternal circuits 508 are connected to the drains of the pass switches 502 and 504. The sources of thepass switch 502 are connected to the third terminal of themode switch 500 and thus to the interchip input/output pad 530. The sources of thepass switch 504 are connected to the second terminal of themode switch 500 and thus to thetest interface circuit 510. The gates of theNMOS transistor 504 a and thePMOS transistor 502 b are connected to the output of theinverter 506. The gates of theNMOS transistor 502 a,PMOS transistor 504 b, and the input of theinverter 506 are connected to the control terminal of themode switch 500 and thus to themode selector 520. - 52. When the control terminal of the
mode switch 500 is at the first logic state, in this case a voltage level approaching that of the power supply voltage source VDD, thepass switch 502 is turned on and thepass switch 504 is turned off, This effectively connects theinternal circuits 508 to the interchip input/output pad 530. In this logic state, the extra electrical load is from the drain of thepass switch 502 and thepass switch 504. This electrical load is very small and thus highly improved performance can be expected over the prior art. Conversely, when the control terminal of themode switch 500 is at the second logic state, in this case a voltage level approaching that of the substrate biasing voltage source VSS, thepass switch 504 is turned on and thepass switch 502 is turned off. The internal circuits are now effectively connected to thetest interface circuit 510. - 53. The
test interface circuit 510 is comprised of thetest circuit 512, thedriver circuit 514, and theESD protection circuit 516. The test interface circuit functions as described in FIGS. 4a and 4 c. - 54. The mode select circuit is the interchip input/
output pad 522 and the test input/output pad 524 connected together and to the control terminal of themode switch 500. The interchip input/output pad 522 is connected as described in FIG. 3 to a mating interchip input/output pad 562 that are joined by a solder bump or ball. The mating interchip input/output pad 562 is on themating chip 560 and is connected to the power supply voltage source VDD to provide the first logic state to the control terminal of themode switch 500 during normal operation. The test input/output pad is connected to thetest system 550 during the testing procedures. During the test procedures, a test probe orneedle 552 is brought in contact with the test input/output pad. The test probe orneedle 552 is connected on aprobe card 554 within thetest system 550 to the substrate biasing voltage source VSS to provide the second logic state to the control terminal of themode switch 500. - 55. The fundamental connections shown in FIG. 5b are as described in FIG. 5a except the test signal originates from the test system attached to the input/
output pad 540. Thetest interface circuit 510 in this case is comprised of thetest circuits 512, thereceiver 518, and the ESD protection circuit and functions as described in FIGS. 4b and 4 d. - 56. Signals originating from the external circuits are applied to the interchip input/
output pad 530 and transferred through thepass switch 502 to theinternal circuits 508 during normal operation. Likewise, the test signals are transferred from thetest interface 510 through thepass switch 504 to theinternal circuits 508 during the test procedures. - 57.FIG. 6a shows a top surface view of the first
integrated circuit chip 600 illustrating the placement of the test input/output pads 605 and the interchip input/output pads 610. The interchip input/output pads 610 form an area array of solder bails orbumps 315 of FIG. 3. The test input/output pads 605 are peripherally arranged so that the test probes or needles of the test system can conveniently make contact with the test input/output pads 605. - 58.FIG. 6b shows the top surface view of the second
integrated circuit chip 615 illustrating the placement of the interchip input/output pads 625 and the external input/output pads 620. The interchip input/output pads 625 form the area array to mate with the interchip input/output pads 610 of FIG. 5a. The firstintegrated circuit chip 600 is mounted “face-to face” to the secondintegrated circuit chip 615. The test input/output pads 605 must have nothing on the surface of the secondintegrated circuit chip 625 in their “shadow.” - 59. The test input/
output pads 630 and the external input/output pads 620 are formed in the periphery of the secondintegrated circuit chip 615. The external input/output pads 620 must be placed outside the shadow of the firstintegrated circuit chip 600. The test input/output pads 630 are placed conveniently so that test probes or needles of a test system can contact the test input/output pads 630. The test input/output pads test interface 510. The test input/output pads test system 550 and either the firstintegrated circuit chip 600 or secondintegrated circuit chip 615. - 60. While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
Claims (37)
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/729,152 US6303996B2 (en) | 1999-03-01 | 2000-12-04 | High performance sub-system design and assembly |
US09/849,039 US6586266B1 (en) | 1999-03-01 | 2001-05-04 | High performance sub-system design and assembly |
US10/420,596 US7378735B2 (en) | 1999-03-01 | 2003-04-22 | High performance sub-system design and assembly |
US12/098,467 US7535102B2 (en) | 1999-03-01 | 2008-04-07 | High performance sub-system design and assembly |
US12/353,252 US7868463B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,251 US7923848B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,255 US7868454B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,254 US7999381B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US13/174,317 US8399988B2 (en) | 1999-03-01 | 2011-06-30 | High performance sub-system design and assembly |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/258,911 US6180426B1 (en) | 1999-03-01 | 1999-03-01 | High performance sub-system design and assembly |
US09/729,152 US6303996B2 (en) | 1999-03-01 | 2000-12-04 | High performance sub-system design and assembly |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/258,911 Division US6180426B1 (en) | 1999-03-01 | 1999-03-01 | High performance sub-system design and assembly |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/849,039 Continuation-In-Part US6586266B1 (en) | 1999-03-01 | 2001-05-04 | High performance sub-system design and assembly |
US10/420,596 Continuation-In-Part US7378735B2 (en) | 1999-03-01 | 2003-04-22 | High performance sub-system design and assembly |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010000013A1 true US20010000013A1 (en) | 2001-03-15 |
US6303996B2 US6303996B2 (en) | 2001-10-16 |
Family
ID=22982662
Family Applications (7)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/258,911 Expired - Lifetime US6180426B1 (en) | 1999-03-01 | 1999-03-01 | High performance sub-system design and assembly |
US09/729,152 Expired - Lifetime US6303996B2 (en) | 1999-03-01 | 2000-12-04 | High performance sub-system design and assembly |
US12/353,252 Expired - Fee Related US7868463B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,255 Expired - Fee Related US7868454B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,254 Expired - Fee Related US7999381B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,251 Expired - Fee Related US7923848B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US13/174,317 Expired - Fee Related US8399988B2 (en) | 1999-03-01 | 2011-06-30 | High performance sub-system design and assembly |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/258,911 Expired - Lifetime US6180426B1 (en) | 1999-03-01 | 1999-03-01 | High performance sub-system design and assembly |
Family Applications After (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/353,252 Expired - Fee Related US7868463B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,255 Expired - Fee Related US7868454B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,254 Expired - Fee Related US7999381B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US12/353,251 Expired - Fee Related US7923848B2 (en) | 1999-03-01 | 2009-01-13 | High performance sub-system design and assembly |
US13/174,317 Expired - Fee Related US8399988B2 (en) | 1999-03-01 | 2011-06-30 | High performance sub-system design and assembly |
Country Status (2)
Country | Link |
---|---|
US (7) | US6180426B1 (en) |
TW (2) | TW461065B (en) |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020063251A1 (en) * | 2000-11-28 | 2002-05-30 | Sadashige Sugiura | Semiconductor device and testing method therefor |
US20030156442A1 (en) * | 2002-02-19 | 2003-08-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and multi-chip module comprising the semiconductor memory device |
US20050045378A1 (en) * | 2003-08-29 | 2005-03-03 | Heng Mung Suan | Stacked microfeature devices and associated methods |
US20050194643A1 (en) * | 2002-12-20 | 2005-09-08 | Williams Richard K. | Testable electrostatic discharge protection circuits |
US20050200005A1 (en) * | 2002-06-27 | 2005-09-15 | Fujitsu Limited | Semiconductor device, semiconductor package, and method for testing semiconductor device |
US20050258528A1 (en) * | 2004-05-24 | 2005-11-24 | Honeywell International Inc. | Method and system for stacking integrated circuits |
US20070222055A1 (en) * | 2004-05-24 | 2007-09-27 | Honeywell International Inc. | Method and System for Stacking Integrated Circuits |
US20070235888A1 (en) * | 2006-04-06 | 2007-10-11 | Nam-Jung Her | Film type package and display apparatus having the same |
US20070267754A1 (en) * | 2005-09-01 | 2007-11-22 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US20080081457A1 (en) * | 2006-09-29 | 2008-04-03 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US20090166846A1 (en) * | 2007-12-28 | 2009-07-02 | Micron Technology, Inc. | Pass-through 3d interconnect for microelectronic dies and associated systems and methods |
US20090283898A1 (en) * | 2008-05-15 | 2009-11-19 | Janzen Jeffery W | Disabling electrical connections using pass-through 3d interconnects and associated systems and methods |
US20100117242A1 (en) * | 2008-11-10 | 2010-05-13 | Miller Gary L | Technique for packaging multiple integrated circuits |
US20120228760A1 (en) * | 2011-03-11 | 2012-09-13 | Altera Corporation | Systems including an i/o stack and methods for fabricating such systems |
US8322031B2 (en) | 2004-08-27 | 2012-12-04 | Micron Technology, Inc. | Method of manufacturing an interposer |
US20220037218A1 (en) * | 2020-07-31 | 2022-02-03 | Sitronix Technology Corp. | Test pad structure of chip |
Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DK1102559T3 (en) * | 1998-09-30 | 2003-09-29 | Cygnus Therapeutic Systems | Method and apparatus for predicting physiological values |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US6495442B1 (en) | 2000-10-18 | 2002-12-17 | Magic Corporation | Post passivation interconnection schemes on top of the IC chips |
US6936531B2 (en) | 1998-12-21 | 2005-08-30 | Megic Corporation | Process of fabricating a chip structure |
US6507117B1 (en) * | 1999-01-29 | 2003-01-14 | Rohm Co., Ltd. | Semiconductor chip and multichip-type semiconductor device |
US6356958B1 (en) | 1999-02-08 | 2002-03-12 | Mou-Shiung Lin | Integrated circuit module has common function known good integrated circuit die with multiple selectable functions |
US6180426B1 (en) * | 1999-03-01 | 2001-01-30 | Mou-Shiung Lin | High performance sub-system design and assembly |
US6586266B1 (en) * | 1999-03-01 | 2003-07-01 | Megic Corporation | High performance sub-system design and assembly |
US6555398B1 (en) * | 1999-10-22 | 2003-04-29 | Magic Corporation | Software programmable multiple function integrated circuit module |
US6512289B1 (en) * | 2000-05-09 | 2003-01-28 | Xilinx, Inc. | Direct current regulation on integrated circuits under high current design conditions |
US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
US7271489B2 (en) | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US6590225B2 (en) * | 2001-01-19 | 2003-07-08 | Texas Instruments Incorporated | Die testing using top surface test pads |
US6613606B1 (en) * | 2001-09-17 | 2003-09-02 | Magic Corporation | Structure of high performance combo chip and processing method |
JP2003185710A (en) * | 2001-10-03 | 2003-07-03 | Matsushita Electric Ind Co Ltd | Multi-chip module, semiconductor chip, and method of testing interchip connection in multi-chip module |
US7067914B2 (en) * | 2001-11-09 | 2006-06-27 | International Business Machines Corporation | Dual chip stack method for electro-static discharge protection of integrated circuits |
US6798073B2 (en) * | 2001-12-13 | 2004-09-28 | Megic Corporation | Chip structure and process for forming the same |
US7932603B2 (en) | 2001-12-13 | 2011-04-26 | Megica Corporation | Chip structure and process for forming the same |
US7170179B1 (en) * | 2002-04-29 | 2007-01-30 | Cypress Semiconductor Corp. | Chip select method through double bonding |
JP3657246B2 (en) * | 2002-07-29 | 2005-06-08 | Necエレクトロニクス株式会社 | Semiconductor device |
JP4105524B2 (en) * | 2002-10-23 | 2008-06-25 | 株式会社東芝 | Semiconductor device |
JP3632691B2 (en) * | 2003-01-30 | 2005-03-23 | セイコーエプソン株式会社 | Test circuit, integrated circuit, and test method |
JP4419049B2 (en) * | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | Memory module and memory system |
EP1617473A1 (en) * | 2004-07-13 | 2006-01-18 | Koninklijke Philips Electronics N.V. | Electronic device comprising an ESD device |
US7786591B2 (en) * | 2004-09-29 | 2010-08-31 | Broadcom Corporation | Die down ball grid array package |
US7557597B2 (en) * | 2005-06-03 | 2009-07-07 | International Business Machines Corporation | Stacked chip security |
US7808075B1 (en) * | 2006-02-07 | 2010-10-05 | Marvell International Ltd. | Integrated circuit devices with ESD and I/O protection |
US9299634B2 (en) * | 2006-05-16 | 2016-03-29 | Broadcom Corporation | Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages |
US9013035B2 (en) * | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
KR100794313B1 (en) * | 2006-12-27 | 2008-01-11 | 삼성전자주식회사 | Semiconductor memory device having bump pads and test method thereof |
JP2009047272A (en) * | 2007-08-22 | 2009-03-05 | Aisin Aw Co Ltd | Fluid gearing with lock-up clutch |
US7872346B1 (en) * | 2007-12-03 | 2011-01-18 | Xilinx, Inc. | Power plane and land pad feature to prevent human metal electrostatic discharge damage |
JP2009295750A (en) * | 2008-06-04 | 2009-12-17 | Toshiba Corp | Semiconductor device |
KR101524186B1 (en) * | 2008-07-14 | 2015-06-01 | 삼성전자주식회사 | Semiconductor chip, wiring substrate for semiconductor package, semiconductor package having the semiconductor chip and display device having the semiconductor package |
US8080862B2 (en) * | 2008-09-09 | 2011-12-20 | Qualcomm Incorporate | Systems and methods for enabling ESD protection on 3-D stacked devices |
US8698139B2 (en) * | 2008-11-25 | 2014-04-15 | Qualcomm Incorporated | Die-to-die power consumption optimization |
US8536893B2 (en) * | 2009-03-09 | 2013-09-17 | Qualcomm Incorporated | Circuit for measuring magnitude of electrostatic discharge (ESD) events for semiconductor chip bonding |
CN202758883U (en) | 2009-05-26 | 2013-02-27 | 拉姆伯斯公司 | Stacked semiconductor device assembly |
US8084853B2 (en) * | 2009-09-25 | 2011-12-27 | Mediatek Inc. | Semiconductor flip chip package utilizing wire bonding for net switching |
JP2011112411A (en) * | 2009-11-25 | 2011-06-09 | Elpida Memory Inc | Semiconductor device |
KR101110818B1 (en) * | 2009-12-28 | 2012-02-24 | 주식회사 하이닉스반도체 | Semiconductor integrated circuit |
KR101086499B1 (en) * | 2009-12-29 | 2011-11-25 | 주식회사 하이닉스반도체 | Semiconductor integrated circuit |
KR101097464B1 (en) * | 2009-12-29 | 2011-12-23 | 주식회사 하이닉스반도체 | Semiconductor integrated circuit |
JP2011249366A (en) * | 2010-05-21 | 2011-12-08 | Panasonic Corp | Semiconductor device and manufacturing method thereof |
CN101915892B (en) * | 2010-08-27 | 2012-06-27 | 钰创科技股份有限公司 | Chip test circuit |
US8797057B2 (en) * | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
JP5257722B2 (en) * | 2011-10-17 | 2013-08-07 | 株式会社村田製作所 | High frequency module |
ITVI20110343A1 (en) * | 2011-12-30 | 2013-07-01 | St Microelectronics Srl | SYSTEM AND ADAPTER FOR TESTING CHIPS WITH INTEGRATED CIRCUITS IN A PACKAGE |
US9019668B2 (en) | 2011-12-30 | 2015-04-28 | Industrial Technology Research Institute | Integrated circuit having a charged-device model electrostatic discharge protection mechanism |
US8685761B2 (en) * | 2012-02-02 | 2014-04-01 | Harris Corporation | Method for making a redistributed electronic device using a transferrable redistribution layer |
US8987787B2 (en) * | 2012-04-10 | 2015-03-24 | Macronix International Co., Ltd. | Semiconductor structure and method for manufacturing the same |
US9871012B2 (en) | 2012-08-31 | 2018-01-16 | Qualcomm Incorporated | Method and apparatus for routing die signals using external interconnects |
US9076807B2 (en) * | 2012-09-11 | 2015-07-07 | Analog Devices, Inc. | Overvoltage protection for multi-chip module and system-in-package |
US9500700B1 (en) * | 2013-11-15 | 2016-11-22 | Xilinx, Inc. | Circuits for and methods of testing the operation of an input/output port |
US10036774B2 (en) * | 2014-12-04 | 2018-07-31 | Arm Limited | Integrated circuit device comprising environment-hardened die and less-environment-hardened die |
US10256227B2 (en) | 2016-04-12 | 2019-04-09 | Vishay-Siliconix | Semiconductor device having multiple gate pads |
US10411006B2 (en) * | 2016-05-09 | 2019-09-10 | Infineon Technologies Ag | Poly silicon based interface protection |
US10784204B2 (en) | 2016-07-02 | 2020-09-22 | Intel Corporation | Rlink—die to die channel interconnect configurations to improve signaling |
US10886171B2 (en) | 2016-07-02 | 2021-01-05 | Intel Corporation | Rlink-on-die interconnect features to enable signaling |
DE102016118709B3 (en) * | 2016-10-04 | 2018-01-25 | Infineon Technologies Ag | PROTECTION DEVICE BEFORE ELECTROSTATIC DISCHARGE AND ELECTRONIC SWITCHING DEVICE |
WO2020048381A1 (en) * | 2018-09-03 | 2020-03-12 | Changxin Memory Technologies, Inc. | Chip test device and method |
CN109557453B (en) * | 2018-11-28 | 2021-04-27 | 郑州云海信息技术有限公司 | Multi-master-control-chip identification processing method and system |
US11217541B2 (en) | 2019-05-08 | 2022-01-04 | Vishay-Siliconix, LLC | Transistors with electrically active chip seal ring and methods of manufacture |
US11218144B2 (en) | 2019-09-12 | 2022-01-04 | Vishay-Siliconix, LLC | Semiconductor device with multiple independent gates |
CN110676244B (en) * | 2019-10-15 | 2020-06-16 | 杭州见闻录科技有限公司 | Chip packaging method and packaging structure |
EP3840543A1 (en) * | 2019-12-20 | 2021-06-23 | Knowledge Development for POF SL | Fiber optic connector |
Family Cites Families (67)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2920232A (en) | 1958-08-18 | 1960-01-05 | Gen Electric | Display device with storage |
CA854886A (en) | 1967-01-13 | 1970-10-27 | West Colin | Electroluminescent device and their manufacture |
US3634714A (en) | 1970-02-16 | 1972-01-11 | G T Schijeldahl Co | Electroluminescent display device with apertured electrodes |
JPS58118123A (en) | 1982-01-06 | 1983-07-14 | Hitachi Ltd | Semicondutor integrated circuit |
US4608592A (en) * | 1982-07-09 | 1986-08-26 | Nec Corporation | Semiconductor device provided with a package for a semiconductor element having a plurality of electrodes to be applied with substantially same voltage |
JPS63126263A (en) | 1986-11-17 | 1988-05-30 | Hitachi Ltd | Semiconductor integrated circuit device |
JP2531827B2 (en) | 1990-04-25 | 1996-09-04 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US5334874A (en) | 1991-09-13 | 1994-08-02 | Metzler Richard A | Electronic device package |
US5365790A (en) | 1992-04-02 | 1994-11-22 | Motorola, Inc. | Device with bonded conductive and insulating substrates and method therefore |
KR940001341A (en) * | 1992-06-29 | 1994-01-11 | 디. 아이. 캐플란 | Instant connection for quick electrical access to electronic devices |
US5461333A (en) * | 1993-03-15 | 1995-10-24 | At&T Ipm Corp. | Multi-chip modules having chip-to-chip interconnections with reduced signal voltage level and swing |
US6674562B1 (en) | 1994-05-05 | 2004-01-06 | Iridigm Display Corporation | Interferometric modulation of radiation |
KR100307602B1 (en) * | 1993-08-30 | 2001-12-15 | 가나이 쓰도무 | Semiconductor integrated circuit device and manufacturing method thereof |
JPH07264042A (en) | 1994-03-17 | 1995-10-13 | Fujitsu Ltd | High speed interface circuit |
TW369712B (en) * | 1994-10-14 | 1999-09-11 | Ibm | Structure and method for connecting to integrated circuitry |
US5534465A (en) * | 1995-01-10 | 1996-07-09 | At&T Corp. | Method for making multichip circuits using active semiconductor substrates |
US5731945A (en) | 1995-02-22 | 1998-03-24 | International Business Machines Corporation | Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes |
EP0767492A3 (en) | 1995-10-02 | 1998-09-09 | Altera Corporation | Integrated circuit test system |
US5818748A (en) * | 1995-11-21 | 1998-10-06 | International Business Machines Corporation | Chip function separation onto separate stacked chips |
US5696466A (en) | 1995-12-08 | 1997-12-09 | The Whitaker Corporation | Heterolithic microwave integrated impedance matching circuitry and method of manufacture |
TW334581B (en) | 1996-06-04 | 1998-06-21 | Handotai Energy Kenkyusho Kk | Semiconductor integrated circuit and fabrication method thereof |
JP3152635B2 (en) | 1996-09-09 | 2001-04-03 | 三洋電機株式会社 | Master slice type basic cell, semiconductor integrated circuit device, flip-flop circuit, exclusive OR circuit, multiplexer and adder |
US5929510A (en) | 1996-10-31 | 1999-07-27 | Sarnoff Corporation | Integrated electronic circuit |
US6025618A (en) * | 1996-11-12 | 2000-02-15 | Chen; Zhi Quan | Two-parts ferroelectric RAM |
US7830588B2 (en) | 1996-12-19 | 2010-11-09 | Qualcomm Mems Technologies, Inc. | Method of making a light modulating display device and associated transistor circuitry and structures thereof |
US5903168A (en) * | 1997-03-21 | 1999-05-11 | Industrial Technology Research Institiute | Switchable MCM CMOS I/O buffers |
US5872489A (en) | 1997-04-28 | 1999-02-16 | Rockwell Science Center, Llc | Integrated tunable inductance network and method |
JP4027465B2 (en) | 1997-07-01 | 2007-12-26 | 株式会社半導体エネルギー研究所 | Active matrix display device and manufacturing method thereof |
US5880987A (en) * | 1997-07-14 | 1999-03-09 | Micron Technology, Inc. | Architecture and package orientation for high speed memory devices |
US6020760A (en) * | 1997-07-16 | 2000-02-01 | Altera Corporation | I/O buffer circuit with pin multiplexing |
JP3838393B2 (en) | 1997-09-02 | 2006-10-25 | 株式会社半導体エネルギー研究所 | Display device with built-in image sensor |
US6072943A (en) * | 1997-12-30 | 2000-06-06 | Lsi Logic Corporation | Integrated bus controller and terminating chip |
JP3099802B2 (en) | 1998-04-09 | 2000-10-16 | 日本電気株式会社 | Semiconductor storage device |
JPH11307719A (en) * | 1998-04-20 | 1999-11-05 | Mitsubishi Electric Corp | Semiconductor device |
US6169418B1 (en) | 1998-06-24 | 2001-01-02 | S3 Incorporated | Efficient routing from multiple sources to embedded DRAM and other large circuit blocks |
TW396419B (en) | 1998-06-30 | 2000-07-01 | Tsmc Acer Semiconductor Mfg Co | A method of manufacturing resistors with high ESD resistance and salicide CMOS transistor |
JP2000022072A (en) | 1998-07-07 | 2000-01-21 | Matsushita Electric Ind Co Ltd | Multichip module |
US6356958B1 (en) | 1999-02-08 | 2002-03-12 | Mou-Shiung Lin | Integrated circuit module has common function known good integrated circuit die with multiple selectable functions |
US6180426B1 (en) * | 1999-03-01 | 2001-01-30 | Mou-Shiung Lin | High performance sub-system design and assembly |
US6586266B1 (en) * | 1999-03-01 | 2003-07-01 | Megic Corporation | High performance sub-system design and assembly |
US6397361B1 (en) | 1999-04-02 | 2002-05-28 | International Business Machines Corporation | Reduced-pin integrated circuit I/O test |
JP2001022072A (en) | 1999-07-07 | 2001-01-26 | Fuji Photo Film Co Ltd | Positive type photoresist composition for exposure with far ultraviolet ray |
TW411608B (en) | 1999-05-13 | 2000-11-11 | Taiwan Semiconductor Mfg | Manufacture of short channel metal oxide semiconductor transistor with improving electrostatic discharge protecting resistance function |
JP3756041B2 (en) | 1999-05-27 | 2006-03-15 | Hoya株式会社 | Manufacturing method of multilayer printed wiring board |
TW442834B (en) | 1999-10-15 | 2001-06-23 | Megic Corp | Integrated circuit module capable of selecting multiple functions |
US20020071169A1 (en) | 2000-02-01 | 2002-06-13 | Bowers John Edward | Micro-electro-mechanical-system (MEMS) mirror device |
US6989600B2 (en) | 2000-04-20 | 2006-01-24 | Renesas Technology Corporation | Integrated circuit device having reduced substrate size and a method for manufacturing the same |
JP2002134658A (en) | 2000-10-24 | 2002-05-10 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
WO2002063681A1 (en) | 2001-02-08 | 2002-08-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and its manufacturing method |
US6973709B2 (en) | 2001-04-19 | 2005-12-13 | Chunghwa Picture Tubes | Method of manufacturing printed-on-display antenna for wireless device |
JP4092890B2 (en) | 2001-05-31 | 2008-05-28 | 株式会社日立製作所 | Multi-chip module |
TW560017B (en) | 2001-07-12 | 2003-11-01 | Hitachi Ltd | Semiconductor connection substrate |
TW563142B (en) | 2001-07-12 | 2003-11-21 | Hitachi Ltd | Thin film capacitor, and electronic circuit component |
US6673698B1 (en) | 2002-01-19 | 2004-01-06 | Megic Corporation | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers |
JP3998984B2 (en) | 2002-01-18 | 2007-10-31 | 富士通株式会社 | Circuit board and manufacturing method thereof |
JP2003332560A (en) | 2002-05-13 | 2003-11-21 | Semiconductor Energy Lab Co Ltd | Semiconductor device and microprocessor |
AU2003237668A1 (en) | 2002-05-23 | 2003-12-12 | Schott Ag | Method for producing a component comprising a conductor structure that is suitable for use at high frequencies and corresponding component |
JP2004079701A (en) | 2002-08-14 | 2004-03-11 | Sony Corp | Semiconductor device and its manufacturing method |
JP4554152B2 (en) | 2002-12-19 | 2010-09-29 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor chip |
JP4138529B2 (en) | 2003-02-24 | 2008-08-27 | 浜松ホトニクス株式会社 | Semiconductor device and radiation detector using the same |
US7115488B2 (en) | 2003-08-29 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
US7657242B2 (en) | 2004-09-27 | 2010-02-02 | Qualcomm Mems Technologies, Inc. | Selectable capacitance circuit |
US7653371B2 (en) | 2004-09-27 | 2010-01-26 | Qualcomm Mems Technologies, Inc. | Selectable capacitance circuit |
KR100689410B1 (en) | 2005-01-07 | 2007-03-08 | 삼성전자주식회사 | Semi-automatic sliding device for sliding type mobile phone |
US9158106B2 (en) | 2005-02-23 | 2015-10-13 | Pixtronix, Inc. | Display methods and apparatus |
JP5003082B2 (en) | 2006-09-26 | 2012-08-15 | 富士通株式会社 | Interposer and manufacturing method thereof |
US7787130B2 (en) | 2008-03-31 | 2010-08-31 | Qualcomm Mems Technologies, Inc. | Human-readable, bi-state environmental sensors based on micro-mechanical membranes |
-
1999
- 1999-03-01 US US09/258,911 patent/US6180426B1/en not_active Expired - Lifetime
-
2000
- 2000-01-07 TW TW089100185A patent/TW461065B/en not_active IP Right Cessation
- 2000-12-04 US US09/729,152 patent/US6303996B2/en not_active Expired - Lifetime
-
2001
- 2001-08-23 TW TW089100185A patent/TW502420B/en not_active IP Right Cessation
-
2009
- 2009-01-13 US US12/353,252 patent/US7868463B2/en not_active Expired - Fee Related
- 2009-01-13 US US12/353,255 patent/US7868454B2/en not_active Expired - Fee Related
- 2009-01-13 US US12/353,254 patent/US7999381B2/en not_active Expired - Fee Related
- 2009-01-13 US US12/353,251 patent/US7923848B2/en not_active Expired - Fee Related
-
2011
- 2011-06-30 US US13/174,317 patent/US8399988B2/en not_active Expired - Fee Related
Cited By (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020063251A1 (en) * | 2000-11-28 | 2002-05-30 | Sadashige Sugiura | Semiconductor device and testing method therefor |
US20030156442A1 (en) * | 2002-02-19 | 2003-08-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and multi-chip module comprising the semiconductor memory device |
US20050205983A1 (en) * | 2002-02-19 | 2005-09-22 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and multi-chip module comprising the semiconductor memory device |
US7072241B2 (en) | 2002-02-19 | 2006-07-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and multi-chip module comprising the semiconductor memory device |
US8080873B2 (en) * | 2002-06-27 | 2011-12-20 | Fujitsu Semiconductor Limited | Semiconductor device, semiconductor package, and method for testing semiconductor device |
US20050200005A1 (en) * | 2002-06-27 | 2005-09-15 | Fujitsu Limited | Semiconductor device, semiconductor package, and method for testing semiconductor device |
US20050194643A1 (en) * | 2002-12-20 | 2005-09-08 | Williams Richard K. | Testable electrostatic discharge protection circuits |
US7432555B2 (en) * | 2002-12-20 | 2008-10-07 | Advanced Analogic Technologies, Inc. | Testable electrostatic discharge protection circuits |
US11887970B2 (en) | 2003-08-29 | 2024-01-30 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US8400780B2 (en) | 2003-08-29 | 2013-03-19 | Micron Technology, Inc. | Stacked microfeature devices |
US20100258939A1 (en) * | 2003-08-29 | 2010-10-14 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US7742313B2 (en) | 2003-08-29 | 2010-06-22 | Micron Technology, Inc. | Stacked microfeature devices |
US20050045378A1 (en) * | 2003-08-29 | 2005-03-03 | Heng Mung Suan | Stacked microfeature devices and associated methods |
US7071421B2 (en) * | 2003-08-29 | 2006-07-04 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US11373979B2 (en) | 2003-08-29 | 2022-06-28 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US10062667B2 (en) | 2003-08-29 | 2018-08-28 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US9515046B2 (en) | 2003-08-29 | 2016-12-06 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US20070222055A1 (en) * | 2004-05-24 | 2007-09-27 | Honeywell International Inc. | Method and System for Stacking Integrated Circuits |
US20050258528A1 (en) * | 2004-05-24 | 2005-11-24 | Honeywell International Inc. | Method and system for stacking integrated circuits |
US7863720B2 (en) * | 2004-05-24 | 2011-01-04 | Honeywell International Inc. | Method and system for stacking integrated circuits |
US7700409B2 (en) * | 2004-05-24 | 2010-04-20 | Honeywell International Inc. | Method and system for stacking integrated circuits |
US8322031B2 (en) | 2004-08-27 | 2012-12-04 | Micron Technology, Inc. | Method of manufacturing an interposer |
US7915736B2 (en) | 2005-09-01 | 2011-03-29 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US20070267754A1 (en) * | 2005-09-01 | 2007-11-22 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US20070235888A1 (en) * | 2006-04-06 | 2007-10-11 | Nam-Jung Her | Film type package and display apparatus having the same |
US20080080113A1 (en) * | 2006-09-29 | 2008-04-03 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US8373202B2 (en) | 2006-09-29 | 2013-02-12 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US7969006B2 (en) | 2006-09-29 | 2011-06-28 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US7989954B2 (en) * | 2006-09-29 | 2011-08-02 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US8004083B2 (en) | 2006-09-29 | 2011-08-23 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US8021918B2 (en) | 2006-09-29 | 2011-09-20 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US20080081457A1 (en) * | 2006-09-29 | 2008-04-03 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US20080080111A1 (en) * | 2006-09-29 | 2008-04-03 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US20080080112A1 (en) * | 2006-09-29 | 2008-04-03 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US20080081458A1 (en) * | 2006-09-29 | 2008-04-03 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US8618580B2 (en) | 2006-09-29 | 2013-12-31 | Megit Acquisition Corp. | Integrated circuit chips with fine-line metal and over-passivation metal |
US20080111242A1 (en) * | 2006-09-29 | 2008-05-15 | Megica Corporation | Integrated circuit chips with fine-line metal and over-passivation metal |
US10020287B2 (en) | 2007-12-28 | 2018-07-10 | Micron Technology, Inc. | Pass-through interconnect structure for microelectronic dies and associated systems and methods |
US9209158B2 (en) | 2007-12-28 | 2015-12-08 | Micron Technology, Inc. | Pass-through 3D interconnect for microelectronic dies and associated systems and methods |
US8084854B2 (en) | 2007-12-28 | 2011-12-27 | Micron Technology, Inc. | Pass-through 3D interconnect for microelectronic dies and associated systems and methods |
US20090166846A1 (en) * | 2007-12-28 | 2009-07-02 | Micron Technology, Inc. | Pass-through 3d interconnect for microelectronic dies and associated systems and methods |
US9607930B2 (en) | 2008-05-15 | 2017-03-28 | Micron Technologies, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
US8772086B2 (en) | 2008-05-15 | 2014-07-08 | Micron Technology, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
US9343368B2 (en) | 2008-05-15 | 2016-05-17 | Micron Technology, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
US8253230B2 (en) * | 2008-05-15 | 2012-08-28 | Micron Technology, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
US8404521B2 (en) | 2008-05-15 | 2013-03-26 | Micron Technology, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
US20090283898A1 (en) * | 2008-05-15 | 2009-11-19 | Janzen Jeffery W | Disabling electrical connections using pass-through 3d interconnects and associated systems and methods |
US20100117242A1 (en) * | 2008-11-10 | 2010-05-13 | Miller Gary L | Technique for packaging multiple integrated circuits |
US8786080B2 (en) * | 2011-03-11 | 2014-07-22 | Altera Corporation | Systems including an I/O stack and methods for fabricating such systems |
US20120228760A1 (en) * | 2011-03-11 | 2012-09-13 | Altera Corporation | Systems including an i/o stack and methods for fabricating such systems |
CN102684681A (en) * | 2011-03-11 | 2012-09-19 | 阿尔特拉公司 | Systems including an i/o stack and methods for fabricating such systems |
US20220037218A1 (en) * | 2020-07-31 | 2022-02-03 | Sitronix Technology Corp. | Test pad structure of chip |
US11694983B2 (en) * | 2020-07-31 | 2023-07-04 | Sitronix Technology Corporation | Test pad structure of chip |
TWI812987B (en) * | 2020-07-31 | 2023-08-21 | 矽創電子股份有限公司 | Test pad structure of chip |
Also Published As
Publication number | Publication date |
---|---|
US7999381B2 (en) | 2011-08-16 |
US20090114914A1 (en) | 2009-05-07 |
US20090121220A1 (en) | 2009-05-14 |
US6303996B2 (en) | 2001-10-16 |
TW502420B (en) | 2002-09-11 |
US7923848B2 (en) | 2011-04-12 |
US6180426B1 (en) | 2001-01-30 |
US20090121221A1 (en) | 2009-05-14 |
TW461065B (en) | 2001-10-21 |
US20090134391A1 (en) | 2009-05-28 |
US7868463B2 (en) | 2011-01-11 |
US7868454B2 (en) | 2011-01-11 |
US20110254001A1 (en) | 2011-10-20 |
US8399988B2 (en) | 2013-03-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6180426B1 (en) | High performance sub-system design and assembly | |
US6586266B1 (en) | High performance sub-system design and assembly | |
US6121677A (en) | Reduced size integrated circuits and methods using test pads located in scribe regions of integrated circuits wafers | |
US6833626B2 (en) | Multichip module structure | |
EP0174224B1 (en) | Chip on chip type integrated circuit device | |
US20130076387A1 (en) | Semiconductor chip, semiconductor device, and method of measuring the same | |
US20070200585A1 (en) | Semiconductor wafer, semiconductor chip, semiconductor device, and wafer testing method | |
US6556409B1 (en) | Integrated circuit including ESD circuits for a multi-chip module and a method therefor | |
JP5085829B2 (en) | Integrated circuit chip structure | |
US7969169B2 (en) | Semiconductor integrated circuit wafer, semiconductor integrated circuit chip, and method of testing semiconductor integrated circuit wafer | |
JP2002228725A (en) | Semiconductor chip, multi-chip module and connection test method | |
JP2011100898A (en) | Semiconductor device | |
US9502385B2 (en) | Semiconductor device and connection checking method for semiconductor device | |
JP5908545B2 (en) | High performance subsystem design and assembly | |
JP2012156513A (en) | Design and assembly of high-performance subsystem | |
JP2010239137A (en) | Design and assembly of high-performance subsystem | |
US7193314B2 (en) | Semiconductor devices and substrates used in thereof | |
KR0169819B1 (en) | Apparatus for fabricating known good die | |
JPH0314265A (en) | Semiconductor device | |
JPS60200537A (en) | Semiconductor device with exclusive testing terminal |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAT HOLDER CLAIMS SMALL ENTITY STATUS, ENTITY STATUS SET TO SMALL (ORIGINAL EVENT CODE: LTOS); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO SMALL (ORIGINAL EVENT CODE: SMAL); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: MEGICA CORPORATION, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, MOU-SHIUNG, DR.;REEL/FRAME:023119/0387 Effective date: 20090728 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
SULP | Surcharge for late payment | ||
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: MEGIT ACQUISITION CORP., CALIFORNIA Free format text: MERGER;ASSIGNOR:MEGICA CORPORATION;REEL/FRAME:031283/0198 Effective date: 20130611 |
|
AS | Assignment |
Owner name: QUALCOMM INCORPORATED, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGIT ACQUISITION CORP.;REEL/FRAME:033303/0124 Effective date: 20140709 |