US20010000627A1 - Active matrix display device having multiple gate electrode portions - Google Patents

Active matrix display device having multiple gate electrode portions Download PDF

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US20010000627A1
US20010000627A1 US09/736,139 US73613900A US2001000627A1 US 20010000627 A1 US20010000627 A1 US 20010000627A1 US 73613900 A US73613900 A US 73613900A US 2001000627 A1 US2001000627 A1 US 2001000627A1
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gate electrode
channel forming
region
forming region
channel
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US6426517B2 (en
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Masahiko Hayakawa
Yosuke Tsukamoto
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Definitions

  • the present invention relates to a semiconductor device using a thin-film semiconductor. More particularly, the present invention relates to a structure of a gate electrode in an insulated gate type transistor.
  • TFT thin-film transistor
  • a thin-film transistor using a crystalline silicon film as an active layer has a high mobility (field effect mobility), it has such a defect that an off-state current (current flowing when the TFT is in an off-state) is large. Further, the thin-film transistor has a problem that when the mobility becomes high, a withstand voltage becomes low so that deterioration becomes noticeable.
  • a thin-film transistor is made equivalently to have such a structure (also called as a multi-gate structure) that a plurality of thin-film transistors are connected in series to each other, so that an applied voltage is distributed to each of the plurality of thin-film transistors.
  • FIG. 4 is a structural view showing an active layer and a gate electrode of a thin-film transistor manufactured by using the technique disclosed in the above publication.
  • reference numeral 401 denotes a source region
  • 402 denotes a drain region.
  • Gate electrodes 403 to 406 are formed above the active layer through a gate insulating film (not shown). At this time, the gate electrodes 403 to 406 are formed integrally so that they are connected electrically.
  • Channel forming regions 407 to 410 are formed just under the gate electrodes 403 to 406 into shapes corresponding to those of the gate electrodes 403 to 406 . It is characterized in that the structure is substantially composed of a plurality of thin-film transistors commonly connected in series.
  • An object of the present invention is to prevent breakdown or deterioration of a semiconductor device equivalently having such a structure that a plurality of semiconductor devices are connected in series to each other, by relieving the concentration of electric field on one of the plurality of semiconductor devices close to a drain side.
  • Another object of the present invention is to prevent deterioration from occurring at a center portion of an active layer, by suppressing an electric current flowing through the vicinity of the center of the active layer.
  • a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with the active layer through the gate insulating film, and is characterized in that the gate electrode has a structure which can be regarded substantially as a plurality of gate electrodes integrally formed, and that among said plurality of gate electrodes, the one closest to the drain region has the narrowest width.
  • the fact that the width of the gate electrode closest to the drain region is the narrowest implies the fact that the width of the channel forming region (in other words, channel length) formed just under the gate electrode is the narrowest.
  • a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with the active layer through the gate insulating film, and is characterized in that the gate electrode has a structure which can be regarded substantially as a plurality of gate electrodes integrally formed, and that the widths of the plurality of gate electrodes sequentially become narrower as it comes to close to the drain region.
  • the above feature implies that the widths of the channel forming regions sequentially become narrower as it comes close to the drain region.
  • These structures are intended to decrease the resistance component of the channel forming region by narrowing the width of the gate electrode close to the drain region, that is, the width of the channel forming region, so that a voltage applied to the channel forming region is lowered.
  • a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with said active layer through said gate insulating film, and is characterized in that a width of the gate electrode is varied in a channel width direction of the active layer.
  • a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with said active layer through said gate insulating film, and is characterized in that a width of the gate electrode becomes wider as it comes close to a center portion of the active layer from an end of the active layer in a channel width direction.
  • the above two structures are intended to suppress the amount of flowing current by widening the width of the gate electrode at the vicinity of the center of the active layer so that the channel forming region is widened and the resistance component is increased at the vicinity of the center of the active layer.
  • the gist of the present invention is to intentionally change the width of the channel forming region in the active layer, so that the resistance component of the channel forming region is set to have a desired characteristic. That is, the present invention is a technique to distribute a voltage applied to the channel forming region and to control the amount of current flowing through a specified portion of the channel forming region.
  • FIG. 1 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 1;
  • FIG. 2 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 2;
  • FIG. 3 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 3;
  • FIG. 4 is a view for explaining the structure of an active layer and a gate electrode of the prior art
  • FIG. 5 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 4.
  • FIG. 6 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 5.
  • FIGS. 7A to 7 F are views for explaining examples of electronic instruments of Embodiment 7.
  • a first invention is a technique to prevent an electric field from concentrating onto a channel forming region close to a drain region in a thin-film transistor having a multi-gate structure.
  • the structure as shown in FIG. 1 is adopted.
  • channel forming regions 106 to 108 are formed into the shapes corresponding to that of gate electrodes. Since gate widths become narrow in the sequence of the gate electrodes 103 , 104 and 105 , channel lengths become shorter in the sequence of the channel forming regions 106 , 107 and 108 (the channel forming region 108 is the shortest).
  • a second invention is a technique to prevent deterioration or breakdown from proceeding first in the vicinity of a center of an active layer.
  • the structure as shown in FIG. 5 is adopted.
  • a gate electrode 503 is patterned into such a shape that the width of the gate electrode in the vicinity of the center of the active layer becomes the widest. As a result, a channel length of a channel forming region 504 becomes the widest in the vicinity of the center of the active layer.
  • the amount of current flowing through the vicinity of the active layer can be suppressed so that the amount of generated heat can be decreased. Accordingly, it is possible to prevent the deterioration phenomenon which appears to be caused by heat accumulation.
  • a thin-film transistor will be exemplified as a semiconductor device, and the structures of an active layer and a gate electrode of a thin-film transistor using the first invention will be described.
  • a gate electrode has a triple-gate type multi-gate electrode structure in which a gate electrode is divided into three at a region where the gate electrode overlaps with an active layer, the gate electrode is not limited to this structure.
  • reference numeral 101 denotes a source region
  • 102 denotes a drain region, which are formed by adding impurity elements (phosphorus, boron, etc.) imparting one conductivity.
  • reference numeral 103 denotes a gate electrode with a width “a”
  • 104 denotes a gate electrode with a width “b”
  • 105 denotes a gate electrode with a width “c”. As shown in FIG. 1, the gate electrodes 103 to 105 are electrically connected to each other.
  • regions 106 to 108 are channel forming regions formed correspondingly to the gate electrodes 103 to 105 , and are substantially intrinsic regions (undoped region) where impurity elements are not intentionally added.
  • the structure of the first invention is featured that the widths of the gate electrodes (widths of the channel forming regions) become narrower as it comes close to the drain region 102 .
  • the widths of the gate electrodes become narrower in the sequence of “a”, “b” and “c”.
  • the scope of the first invention is not limited to the shape of the active layer and the gate electrodes shown in FIG. 1, but a user may arbitrarily determine the shape. Also, it is necessary for a user to experimentally obtain specific values of the widths of the channel forming regions and the like.
  • the same effect as in the first invention can be obtained even if only the gate electrode closest to the drain region is made thinner than all of the other gate electrodes and all of the other gate electrodes are made to have the same width.
  • a channel forming region is substantially intrinsic, it behaves as a region having high resistance. Thus, even if a thin-film transistor is in an on-state, it is conceivable that as a channel length becomes longer, its resistance component becomes higher. That is, in the structure shown in FIG. 1, it is conceivable that the resistance of the channel forming region 108 is the lowest.
  • a first difference from FIG. 1 is that the active layer has a zigzag or serpentine shape. Such a shape is effective in lowering an area occupied by the active layer.
  • a second difference from FIG. 1 is the shape of a gate electrode.
  • a channel forming region with a desired width can be formed.
  • a gate electrode portion indicated by reference numeral 201 is formed in order to form a channel forming region 106 with a channel length “a”.
  • gate electrode portions 202 and 203 are formed, respectively.
  • the shape of the active layer and the shape of the gate electrode to which the first invention can be applied are not limited to those shown in this embodiment. It is needless to say that a user may adequately determine the shape according to the necessity.
  • the structure shown in the first or second embodiment is effective when the positions of a source region and a drain region are fixed.
  • the source and drain regions are fixed when a driving circuit of an active matrix type electro-optical device is formed.
  • the first invention can not be effected by the structures described in the first and second embodiments.
  • channel lengths of channel forming regions 306 and 307 are made a channel length “a” which is shorter than the channel length “b”. If the gate electrodes are made to have a symmetrical structure between a source side and a drain side, it is desirable for keeping the symmetry of a TFT operation.
  • reference numeral 501 denotes a source region
  • 502 denotes a drain region
  • 503 denotes a gate electrode.
  • the gate electrode 503 has a structure in which a width of electrode is locally widened. As a result, the width of a channel forming region 504 which is formed in correspondence with the shape of the gate electrode 503 becomes wider as it comes close to the center of an active layer from end portions of the active layer in a channel width direction (direction shown by arrows in the drawing).
  • the present inventors considered the phenomenon that deterioration started from the vicinity of a center of an active layer in a thin-film transistor using the active layer having a wide channel width, and assumed that the phenomenon was greatly affected by heat accumulation which was caused by difficulty of heat radiation from the vicinity of the center of the active layer.
  • the inventors considered it to be important that the channel length at the vicinity of the center of the active layer should be elongated to form a region having a large resistance component to suppress the amount of current flowing therethrough.
  • This embodiment shows a technique invented based on the above findings of the present inventors, and shows an example in which the shape of the gate electrode 503 above the active layer is locally changed (widened), so that a large current is prevented from flowing through the vicinity of the center of the active layer.
  • the gist of the second invention is that the channel length close to the center of the active layer is elongated so as to suppress the heat generation due to a large electric current. Therefore, if the gist is kept, the structure and shape of the gate electrode may be arbitrarily designed according to the necessity of a user.
  • the feature of an active layer shown in FIG. 6 is that slits are locally provided. That is, parts of the active layer are hollowed out, so that three active layers with narrow channel widths are substantially electrically connected in parallel to each other. The number of the slits may be appropriately changed.
  • reference numeral 601 denotes a source region
  • 602 denotes a drain region
  • 603 denotes a gate electrode
  • 604 to 606 denote channel forming regions formed just under the gate electrode 603 .
  • the channel forming regions 604 and 606 have channel lengths of the same width, and the channel forming region 605 has a channel length longer than other regions.
  • the feature of this embodiment is that since the slits are provided in the active layer, generated heat can be easily dissipated. Thus, the amount of flowing current can be decreased by the second invention so that the generation of intense heat is suppressed, and heat dissipation can be further effectively carried out by providing the slits.
  • This embodiment is an especially useful technique for a thin-film transistor and the like for a driving circuit which handles a large current and brings high speed operation.
  • a thin-film transistor described in the first to sixth embodiments can constitute an active matrix type electro-optical device (liquid crystal display device, EL display device, EC display device, and the like).
  • the first invention is effective for the pixel matrix circuit to which a high voltage is applied
  • the second invention is effective for the driving circuit which handles a large current.
  • a thin-film transistor using the present invention can be applied to electronic instruments and the like in which the above electro-optical device is used as a display medium.
  • the electronic instruments will be described below with reference to drawings.
  • FIGS. 7A to 7 F As semiconductor devices using the present invention, there are enumerated a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer, and the like. Brief description thereof will be presented with reference to FIGS. 7A to 7 F.
  • FIG. 7A shows a mobile computer which is constituted by a main body 2001 , a camera portion 2002 , an image receiving portion 2003 , an operation switch 2004 , and a display device 2005 .
  • the present invention can be applied to the display device 2005 and an integrated circuit incorporated into the device.
  • FIG. 7B shows a head mount display which is constituted by a main body 2101 , a display device 2102 , and a band portion 2103 .
  • the display device 2102 is formed of two comparatively compact ones.
  • the present invention can be applied to the display device 2102 and an integrated circuit incorporated into the device.
  • FIG. 7C shows a car navigation unit which is constituted by a main body 2201 , a display device 2202 , an operation switch 2203 , and an antenna 2204 .
  • the present invention can be applied to the display device 2202 and an integrated circuit inside the device.
  • FIG. 7D shows a potable telephone which is constituted by a main body 2301 , an audio output portion 2302 , an audio input portion 2303 , a display device 2304 , an operation switch 2305 , and an antenna 2306 .
  • the present invention can be applied to the display device 2304 and an integrated circuit inside the device.
  • FIG. 7E shows a video camera which is constituted by a main body 2401 , a display device 2402 , an audio input portion 2403 , an operation switch 2404 , a battery 2405 , and an image receiving portion 2406 .
  • the present invention can be applied to the display device 2402 and an integrated circuit inside the device.
  • FIG. 7F shows a front projector which is constituted by a main body 2501 , a light source 2502 , a reflection type display device 2503 , an optical system 2504 , and a screen 2505 . Since the screen 2505 is a large picture screen used for presentation, high resolution is required for the display device 2503 .
  • the present invention can be applied to the reflection type display device 2503 and an integrated circuit inside the device.
  • semiconductor device used in the present specification implies “a driving device using a semiconductor”.
  • the above electro-optical devices and electronic instruments are also included in the category of the semiconductor device.
  • the present invention is a useful technique in technology or industry.
  • the present invention is effected, it is possible to relieve the phenomenon in which an electric field is locally concentrated in a thin-film transistor formed of a multi-gate structure. That is, it becomes possible to prevent deterioration that tends to occur at a high rate as it comes close to a drain region.

Abstract

In a thin-film transistor of multi-gate structure, the width of a channel forming region 108 closest to a drain region 102 is made the narrowest. This prevents a transistor structure closest to the drain region from first deteriorating. Further, the channel length at the vicinity of a center of an active layer is intentionally widened, so that the amount of current flowing through the vicinity of the center of the active layer is decreased and the deteriorating phenomenon due to heat accumulation is prevented. Therefore, a semiconductor device with a high reliability is realized.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a semiconductor device using a thin-film semiconductor. More particularly, the present invention relates to a structure of a gate electrode in an insulated gate type transistor. [0002]
  • 2. Description of the Related Art [0003]
  • As a semiconductor device using a thin-film semiconductor, attention is attached to a thin-film transistor (TFT). Especially, in recent years, a TFT capable of performing high speed operation by using a crystalline silicon film (for example, polysilicon film), has been put into a practical use. [0004]
  • Although a thin-film transistor using a crystalline silicon film as an active layer has a high mobility (field effect mobility), it has such a defect that an off-state current (current flowing when the TFT is in an off-state) is large. Further, the thin-film transistor has a problem that when the mobility becomes high, a withstand voltage becomes low so that deterioration becomes noticeable. [0005]
  • As means for solving such problems, there is known a technique disclosed in Japanese Examined Patent Publication No. Hei 5-44195. According to this technique, a thin-film transistor is made equivalently to have such a structure (also called as a multi-gate structure) that a plurality of thin-film transistors are connected in series to each other, so that an applied voltage is distributed to each of the plurality of thin-film transistors. [0006]
  • FIG. 4 is a structural view showing an active layer and a gate electrode of a thin-film transistor manufactured by using the technique disclosed in the above publication. In FIG. 4, [0007] reference numeral 401 denotes a source region, and 402 denotes a drain region. Gate electrodes 403 to 406 are formed above the active layer through a gate insulating film (not shown). At this time, the gate electrodes 403 to 406 are formed integrally so that they are connected electrically.
  • [0008] Channel forming regions 407 to 410 are formed just under the gate electrodes 403 to 406 into shapes corresponding to those of the gate electrodes 403 to 406. It is characterized in that the structure is substantially composed of a plurality of thin-film transistors commonly connected in series.
  • However, according to experiments carried out by the present inventors by using the TFTs having the structure as shown in FIG. 4, it has been found that the thin-film transistor closest to the [0009] drain region 402 deteriorates most intensely. Also, it has been found that when a high voltage is applied between the source and drain, breakdown or deterioration proceeds sequentially from a transistor at the side close to the drain region.
  • According to another experiment, it has been found that in a TFT constituted by an active layer with a wide channel width, the vicinity of a center of an active layer (vicinity of the center in the channel width direction) deteriorates most intensely. [0010]
  • SUMMARY OF THE INVENTION
  • An object of the present invention is to prevent breakdown or deterioration of a semiconductor device equivalently having such a structure that a plurality of semiconductor devices are connected in series to each other, by relieving the concentration of electric field on one of the plurality of semiconductor devices close to a drain side. [0011]
  • Another object of the present invention is to prevent deterioration from occurring at a center portion of an active layer, by suppressing an electric current flowing through the vicinity of the center of the active layer. [0012]
  • According to a structure of a first invention, a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with the active layer through the gate insulating film, and is characterized in that the gate electrode has a structure which can be regarded substantially as a plurality of gate electrodes integrally formed, and that among said plurality of gate electrodes, the one closest to the drain region has the narrowest width. [0013]
  • In the above structure, the fact that the width of the gate electrode closest to the drain region is the narrowest implies the fact that the width of the channel forming region (in other words, channel length) formed just under the gate electrode is the narrowest. [0014]
  • According to another structure of the first invention, a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with the active layer through the gate insulating film, and is characterized in that the gate electrode has a structure which can be regarded substantially as a plurality of gate electrodes integrally formed, and that the widths of the plurality of gate electrodes sequentially become narrower as it comes to close to the drain region. [0015]
  • Also in this case, the above feature implies that the widths of the channel forming regions sequentially become narrower as it comes close to the drain region. [0016]
  • These structures are intended to decrease the resistance component of the channel forming region by narrowing the width of the gate electrode close to the drain region, that is, the width of the channel forming region, so that a voltage applied to the channel forming region is lowered. [0017]
  • According to a structure of a second invention, a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with said active layer through said gate insulating film, and is characterized in that a width of the gate electrode is varied in a channel width direction of the active layer. [0018]
  • According to another structure of the second invention, a semiconductor device is comprised of: an active layer including source and drain regions and channel forming regions; a gate insulating film; and a gate electrode overlapping with said active layer through said gate insulating film, and is characterized in that a width of the gate electrode becomes wider as it comes close to a center portion of the active layer from an end of the active layer in a channel width direction. [0019]
  • The above two structures are intended to suppress the amount of flowing current by widening the width of the gate electrode at the vicinity of the center of the active layer so that the channel forming region is widened and the resistance component is increased at the vicinity of the center of the active layer. [0020]
  • As described above, the gist of the present invention is to intentionally change the width of the channel forming region in the active layer, so that the resistance component of the channel forming region is set to have a desired characteristic. That is, the present invention is a technique to distribute a voltage applied to the channel forming region and to control the amount of current flowing through a specified portion of the channel forming region. [0021]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a view for explaining the structure of an active layer and a gate electrode of [0022] Embodiment 1;
  • FIG. 2 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 2; [0023]
  • FIG. 3 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 3; [0024]
  • FIG. 4 is a view for explaining the structure of an active layer and a gate electrode of the prior art; [0025]
  • FIG. 5 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 4; [0026]
  • FIG. 6 is a view for explaining the structure of an active layer and a gate electrode of Embodiment 5; and [0027]
  • FIGS. 7A to [0028] 7F are views for explaining examples of electronic instruments of Embodiment 7.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A first invention is a technique to prevent an electric field from concentrating onto a channel forming region close to a drain region in a thin-film transistor having a multi-gate structure. In order to realize the technique, the structure as shown in FIG. 1 is adopted. [0029]
  • In an active layer, [0030] channel forming regions 106 to 108 are formed into the shapes corresponding to that of gate electrodes. Since gate widths become narrow in the sequence of the gate electrodes 103, 104 and 105, channel lengths become shorter in the sequence of the channel forming regions 106, 107 and 108 (the channel forming region 108 is the shortest).
  • With this structure, in accordance with Ohm's law, a voltage applied to the [0031] channel forming region 108 becomes the lowest, so that an electric field formed concentrically in an end portion at a drain side of the channel forming region 108 becomes low. As a result, it is possible to relieve the phenomenon that an electric field is more concentrated onto a portion as it comes close to a drain region.
  • A second invention is a technique to prevent deterioration or breakdown from proceeding first in the vicinity of a center of an active layer. In order to realize the technique, the structure as shown in FIG. 5 is adopted. [0032]
  • In FIG. 5, a [0033] gate electrode 503 is patterned into such a shape that the width of the gate electrode in the vicinity of the center of the active layer becomes the widest. As a result, a channel length of a channel forming region 504 becomes the widest in the vicinity of the center of the active layer.
  • With the above structure, the amount of current flowing through the vicinity of the active layer can be suppressed so that the amount of generated heat can be decreased. Accordingly, it is possible to prevent the deterioration phenomenon which appears to be caused by heat accumulation. [0034]
  • Embodiment 1
  • In this embodiment, a thin-film transistor will be exemplified as a semiconductor device, and the structures of an active layer and a gate electrode of a thin-film transistor using the first invention will be described. In this embodiment, although a gate electrode has a triple-gate type multi-gate electrode structure in which a gate electrode is divided into three at a region where the gate electrode overlaps with an active layer, the gate electrode is not limited to this structure. [0035]
  • In FIG. 1, [0036] reference numeral 101 denotes a source region, and 102 denotes a drain region, which are formed by adding impurity elements (phosphorus, boron, etc.) imparting one conductivity. Also, reference numeral 103 denotes a gate electrode with a width “a”, 104 denotes a gate electrode with a width “b”, and 105 denotes a gate electrode with a width “c”. As shown in FIG. 1, the gate electrodes 103 to 105 are electrically connected to each other.
  • Further, [0037] regions 106 to 108 are channel forming regions formed correspondingly to the gate electrodes 103 to 105, and are substantially intrinsic regions (undoped region) where impurity elements are not intentionally added.
  • The structure of the first invention is featured that the widths of the gate electrodes (widths of the channel forming regions) become narrower as it comes close to the [0038] drain region 102. In FIG. 1, the widths of the gate electrodes become narrower in the sequence of “a”, “b” and “c”.
  • Incidentally, the scope of the first invention is not limited to the shape of the active layer and the gate electrodes shown in FIG. 1, but a user may arbitrarily determine the shape. Also, it is necessary for a user to experimentally obtain specific values of the widths of the channel forming regions and the like. [0039]
  • Further, in this embodiment, the description is made of the structure in which the widths of the gate electrodes sequentially become narrower as it comes close to the drain region. However, the same effect as in the first invention can be obtained even if only the gate electrode closest to the drain region is made thinner than all of the other gate electrodes and all of the other gate electrodes are made to have the same width. [0040]
  • Now, the description is made of the process until the present inventors reached the first invention. Since a channel forming region is substantially intrinsic, it behaves as a region having high resistance. Thus, even if a thin-film transistor is in an on-state, it is conceivable that as a channel length becomes longer, its resistance component becomes higher. That is, in the structure shown in FIG. 1, it is conceivable that the resistance of the [0041] channel forming region 108 is the lowest.
  • Then, if the amount of current flowing between a source and a drain is constant, according to Ohm's law, the higher the resistance of a region is, the larger a voltage applied to the region is. That is, a voltage applied to the [0042] channel forming region 108 becomes the lowest.
  • Further, it is conceivable that a voltage applied to both ends of a channel forming region is concentrically applied to the end portion (channel/drain connection portion) close to the drain side of the channel forming region so that a high electric field is formed. Thus, it can be said that as the voltage applied to the channel forming region becomes lower, the electric field concentrated on the end portion at the drain side becomes lower. [0043]
  • When the above consideration is summarized, in the structure shown in FIG. 1, it is understood that the electric fields formed in the end portions at the drain side become lower in the sequence of the [0044] channel forming regions 106, 107 and 108.
  • Conventionally, a higher electric field is apt to be formed at the channel/drain connection portion closer to the drain region, so that deterioration or breakdown tends to occur. However, by effecting the first invention, the electric field applied to the channel/drain connection portion can be made low as it comes close to the drain region, so that the deterioration can be relieved. [0045]
  • Embodiment 2
  • In this embodiment, an example in which the shape of an active layer is different from that of the first embodiment, will be described with reference to FIG. 2. Portions in FIG. 2 corresponding to those in FIG. 1 will be designated by the same reference numerals. [0046]
  • In the structure shown in FIG. 2, a first difference from FIG. 1 is that the active layer has a zigzag or serpentine shape. Such a shape is effective in lowering an area occupied by the active layer. A second difference from FIG. 1 is the shape of a gate electrode. [0047]
  • By adjusting the design pattern of the gate electrode, a channel forming region with a desired width can be formed. In this embodiment, in order to form a [0048] channel forming region 106 with a channel length “a”, a gate electrode portion indicated by reference numeral 201 is formed. Also, in order to form a channel forming region 107 with a channel length “b” and a channel forming region 108 with a channel length “c”, gate electrode portions 202 and 203 are formed, respectively.
  • Of course, the shape of the active layer and the shape of the gate electrode to which the first invention can be applied, are not limited to those shown in this embodiment. It is needless to say that a user may adequately determine the shape according to the necessity. [0049]
  • By employing the gate electrode described above, it is possible to form the active layer in which the widths of the channel forming regions become narrower as it comes close to the drain region [0050] 102 (a>b>c in the drawing).
  • Embodiment 3
  • The structure shown in the first or second embodiment is effective when the positions of a source region and a drain region are fixed. For example, the source and drain regions are fixed when a driving circuit of an active matrix type electro-optical device is formed. [0051]
  • However, since pixel TFTs arranged in a pixel matrix circuit of the active matrix type electro-optical device, repeat charge and discharge of an electric charge, the source region and the drain region are counterchanged with each other every time the charge and discharge are made. In this case, the first invention can not be effected by the structures described in the first and second embodiments. [0052]
  • Therefore, in the case described above, as shown in FIG. 3, it is necessary to form a structure in which [0053] gate electrodes 303 and 305 at the sides close to a source region (or drain region) 301 and a drain region (or source region) 302, respectively, are made narrower than a gate electrode 304.
  • In this embodiment, when a channel length of a [0054] channel forming region 307 is “b”, channel lengths of channel forming regions 306 and 307 are made a channel length “a” which is shorter than the channel length “b”. If the gate electrodes are made to have a symmetrical structure between a source side and a drain side, it is desirable for keeping the symmetry of a TFT operation.
  • Embodiment 4
  • In this embodiment, a structure of an active layer and a gate electrode of a thin-film transistor using a second invention will be described with reference to FIG. 5. [0055]
  • In FIG. 5, [0056] reference numeral 501 denotes a source region, 502 denotes a drain region, and 503 denotes a gate electrode. The gate electrode 503 has a structure in which a width of electrode is locally widened. As a result, the width of a channel forming region 504 which is formed in correspondence with the shape of the gate electrode 503 becomes wider as it comes close to the center of an active layer from end portions of the active layer in a channel width direction (direction shown by arrows in the drawing).
  • Here, the description is made of the process until the present inventors found the second invention. The present inventors considered the phenomenon that deterioration started from the vicinity of a center of an active layer in a thin-film transistor using the active layer having a wide channel width, and assumed that the phenomenon was greatly affected by heat accumulation which was caused by difficulty of heat radiation from the vicinity of the center of the active layer. [0057]
  • For that reason, it is necessary to decrease the amount of current flowing through the vicinity of the center of the active layer to suppress heat generation. Therefore, the inventors considered it to be important that the channel length at the vicinity of the center of the active layer should be elongated to form a region having a large resistance component to suppress the amount of current flowing therethrough. [0058]
  • This embodiment shows a technique invented based on the above findings of the present inventors, and shows an example in which the shape of the [0059] gate electrode 503 above the active layer is locally changed (widened), so that a large current is prevented from flowing through the vicinity of the center of the active layer.
  • Incidentally, as described above, the gist of the second invention is that the channel length close to the center of the active layer is elongated so as to suppress the heat generation due to a large electric current. Therefore, if the gist is kept, the structure and shape of the gate electrode may be arbitrarily designed according to the necessity of a user. [0060]
  • Embodiment 5
  • In this embodiment, an example in which the second invention shown in the fourth embodiment is combined with a heat dissipation effect due to the shape of an active layer, will be described with reference to FIG. 6. [0061]
  • The feature of an active layer shown in FIG. 6 is that slits are locally provided. That is, parts of the active layer are hollowed out, so that three active layers with narrow channel widths are substantially electrically connected in parallel to each other. The number of the slits may be appropriately changed. [0062]
  • In FIG. 6, [0063] reference numeral 601 denotes a source region, 602 denotes a drain region, 603 denotes a gate electrode, and 604 to 606 denote channel forming regions formed just under the gate electrode 603. The channel forming regions 604 and 606 have channel lengths of the same width, and the channel forming region 605 has a channel length longer than other regions.
  • The feature of this embodiment is that since the slits are provided in the active layer, generated heat can be easily dissipated. Thus, the amount of flowing current can be decreased by the second invention so that the generation of intense heat is suppressed, and heat dissipation can be further effectively carried out by providing the slits. [0064]
  • Embodiment 6
  • By combining the first invention described in the first to third embodiments with the second invention described in the fourth and fifth embodiments, a thin-film transistor of multi-gate structure having higher reliability can be manufactured. [0065]
  • That is, deterioration of a thin-film transistor close to a drain region can be prevented by the first invention, and deterioration from the vicinity of a center of an active layer due to heat generation can be prevented by the second invention. [0066]
  • This embodiment is an especially useful technique for a thin-film transistor and the like for a driving circuit which handles a large current and brings high speed operation. [0067]
  • Embodiment 7
  • A thin-film transistor described in the first to sixth embodiments can constitute an active matrix type electro-optical device (liquid crystal display device, EL display device, EC display device, and the like). For example, in a liquid crystal display device in which a pixel matrix circuit and a driving circuit are integrally formed on the same substrate, the first invention is effective for the pixel matrix circuit to which a high voltage is applied, and the second invention is effective for the driving circuit which handles a large current. [0068]
  • U.S. Pat. No. 5,569,936, the disclosure of which is herein incorporated by reference, discloses an active matrix type liquid crystal display device, which the thin film transistor formed through the first to sixth embodiments of the present invention can be applied to. [0069]
  • A thin-film transistor using the present invention can be applied to electronic instruments and the like in which the above electro-optical device is used as a display medium. The electronic instruments will be described below with reference to drawings. [0070]
  • As semiconductor devices using the present invention, there are enumerated a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer, and the like. Brief description thereof will be presented with reference to FIGS. 7A to [0071] 7F.
  • FIG. 7A shows a mobile computer which is constituted by a [0072] main body 2001, a camera portion 2002, an image receiving portion 2003, an operation switch 2004, and a display device 2005. The present invention can be applied to the display device 2005 and an integrated circuit incorporated into the device.
  • FIG. 7B shows a head mount display which is constituted by a [0073] main body 2101, a display device 2102, and a band portion 2103. The display device 2102 is formed of two comparatively compact ones. The present invention can be applied to the display device 2102 and an integrated circuit incorporated into the device.
  • FIG. 7C shows a car navigation unit which is constituted by a [0074] main body 2201, a display device 2202, an operation switch 2203, and an antenna 2204. The present invention can be applied to the display device 2202 and an integrated circuit inside the device.
  • FIG. 7D shows a potable telephone which is constituted by a [0075] main body 2301, an audio output portion 2302, an audio input portion 2303, a display device 2304, an operation switch 2305, and an antenna 2306. The present invention can be applied to the display device 2304 and an integrated circuit inside the device.
  • FIG. 7E shows a video camera which is constituted by a [0076] main body 2401, a display device 2402, an audio input portion 2403, an operation switch 2404, a battery 2405, and an image receiving portion 2406. The present invention can be applied to the display device 2402 and an integrated circuit inside the device.
  • FIG. 7F shows a front projector which is constituted by a [0077] main body 2501, a light source 2502, a reflection type display device 2503, an optical system 2504, and a screen 2505. Since the screen 2505 is a large picture screen used for presentation, high resolution is required for the display device 2503. The present invention can be applied to the reflection type display device 2503 and an integrated circuit inside the device.
  • It should be noted that the term “semiconductor device” used in the present specification implies “a driving device using a semiconductor”. The above electro-optical devices and electronic instruments are also included in the category of the semiconductor device. [0078]
  • As described above, by effecting the present invention, the reliability of various semiconductor devices can be improved. Accordingly, the present invention is a useful technique in technology or industry. [0079]
  • If the present invention is effected, it is possible to relieve the phenomenon in which an electric field is locally concentrated in a thin-film transistor formed of a multi-gate structure. That is, it becomes possible to prevent deterioration that tends to occur at a high rate as it comes close to a drain region. [0080]
  • Further, if the amount of current flowing through the vicinity of a center of an active layer is suppressed, it becomes possible to decrease the breakdown or deterioration due to heat. [0081]
  • As described above, when the present invention is used, it is possible to prevent the breakdown or deterioration of a semiconductor device (semiconductor element) typified by a thin-film transistor, and to constitute a semiconductor device having high reliability by using such a semiconductor element. [0082]

Claims (24)

1. An EL display device comprising at least a thin film transistor including:
a semiconductor island including:
a source region,
a drain region, and
at least a first channel forming region, a second channel forming region, and a third channel forming region, each being formed between the source region and the drain region;
a gate insulating film; and
a gate electrode, adjacent to the semiconductor island and having the gate insulating film between said semiconductor island and said gate electrode,
wherein the gate electrode is divided into at least a first gate electrode portion, a second gate electrode portion and a third gate electrode portion,
wherein the first gate electrode portion is formed over the first channel forming region and the closest to the drain region, the first channel forming region being the closest to the drain region,
wherein the first gate electrode has the narrowest width so that the first channel forming region has the shortest channel length,
wherein the third gate electrode portion is formed over the third channel forming region and the closest to the source region thereby the third channel forming region being defined the closest to the source region,
wherein the third gate electrode portion has the widest width so that the third channel forming region has the longest channel length,
wherein a current flows from the source region to the drain region through each of the first, second and third channel forming regions in a channel length direction.
2. A device according to
claim 1
,
wherein the semiconductor island comprises crystalline silicon.
3. A device according to
claim 1
,
wherein the gate electrode overlaps with the semiconductor island having the gate insulating film therebetween.
4. A device according to
claim 1
,
wherein the EL display device is used in one selected from the group consisting of a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer.
5. An EL display device comprising at least a thin film transistor including:
a semiconductor island with a serpentine shape, said semiconductor island including:
a source region,
a drain region, and
at least a first channel forming region, a second channel forming region and a third channel forming region, each being formed between the source region and the drain region;
a gate insulating film; and
a gate electrode adjacent to the serpentine shaped semiconductor island the gate insulating film between said semiconductor island and said gate electrode,
wherein the gate electrode has at least a first gate electrode portion, a second gate electrode portion and a third gate electrode portion,
wherein the first gate electrode portion is formed over the first channel forming region and the closest to the drain region thereby the first channel forming region being defined the closest to the drain region,
wherein the first gate electrode has the narrowest width so that the first channel forming region has the shortest channel length,
wherein the third gate electrode portion is formed over the third channel forming region and the closest to the source region thereby the third channel forming region being defined the closest to the source region,
wherein the third gate electrode portion has the widest width so that the third channel forming region has the longest channel length,
wherein a current flows from the source region to the drain region through each of the first, second and third channel forming regions in a channel length direction.
6. A device according to
claim 5
,
wherein the semiconductor island comprises crystalline silicon.
7. A device according to
claim 5
,
wherein the gate electrode overlaps with the semiconductor island having the gate insulating film therebetween.
8. A device according to
claim 5
,
wherein the EL display device is used in one selected from the group consisting of a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer.
9. An EL display device comprising:
a driving circuit portion; and
a pixel matrix circuit portion, said pixel matrix circuit portion including at least a pixel thin film transistor,
said pixel thin film transistor comprising:
a semiconductor island including:
a source region,
a drain region, and
at least a first channel forming region, a second channel forming region and a third channel forming region, each being formed between the source region and the drain region;
a gate insulating film; and
a gate electrode adjacent to the semiconductor island having the gate insulating film therebetween,
wherein the gate electrode has a symmetrical structure and is divided into at least a first gate electrode portion, a second gate electrode portion and a third gate electrode portion,
wherein the first gate electrode portion is formed over the first channel forming region and the closest to one of the source and drain regions,
wherein the third gate electrode portion is formed over the third channel forming region and the closest to the other of the source and drain regions,
wherein the second gate electrode portion is formed over the second channel forming region and between the first and third gate electrode portion thereby the second channel forming region being defined between the first and third channel forming regions,
wherein the second gate electrode portion has the widest width so that the second channel forming region has the longest channel length,
wherein each of the first and third gate electrodes has a same width which is narrower than a width of the second gate electrode portion so that each of the first and third channel forming regions has a same length which is shorter than a width of the second channel forming region,
wherein a current flows from the source region to the drain region through each of the first, second and third channel forming regions in a channel length direction,
wherein the source region and the drain region are interchanged with each other every time of a charge and a discharge.
10. A device according to
claim 9
,
wherein the semiconductor island comprises crystalline silicon.
11. A device according to
claim 9
,
wherein the gate electrode overlaps with the semiconductor island having the gate insulating film therebetween.
12. A device according to
claim 9
,
wherein the EL display device is used in one selected from the group consisting of a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer.
13. An EL display device comprising at least a thin film transistor including:
a semiconductor island including:
a source region,
a drain region, and
a channel forming region being formed between the source and drain regions;
a gate insulating film; and
a gate electrode adjacent to the semiconductor island having the gate insulating film therebetween,
wherein the gate electrode has two end portions and a center portion formed between the two end portions, each of the end and center portions being located in a channel width direction,
wherein the center portion of the gate electrode has the widest width so that a center portion of the channel forming region has the longest channel length,
wherein a current flows from the source region to the drain region through the channel forming region in a channel length direction.
14. A device according to
claim 13
,
wherein the semiconductor island comprises crystalline silicon.
15. A device according to
claim 13
,
wherein the gate electrode overlaps with the semiconductor island having the gate insulating film therebetween.
16. A device according to
claim 13
,
wherein the EL display device is used in one selected from the group consisting of a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer.
17. An EL display device comprising at least a thin film transistor including:
a semiconductor island including:
a source region,
a drain region, and
a channel forming region being formed between the source region and the drain region;
a gate insulating film; and
a gate electrode adjacent to the semiconductor island having the gate insulating film therebetween,
wherein the gate electrode has two end portions and a middle portion formed between the two end portions, each of the end and middle portions being located in a channel width direction,
wherein the channel forming region has a plurality of slits therein so that a plurality of active regions are defined and electrically connected in parallel to each other,
wherein the middle portion of the gate electrode has the widest width so that a middle portion of the channel forming region has the longest channel length,
wherein a current flows from the source region to the drain region through the channel forming region in a channel length direction.
18. A device according to
claim 17
,
wherein the semiconductor island comprises crystalline silicon.
19. A device according to
claim 17
,
wherein the gate electrode overlaps with the semiconductor island having the gate insulating film therebetween.
20. A device according to
claim 17
,
wherein EL display device is used in one selected from the group consisting of a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer.
21. An EL display device comprising at least a thin film transistor including:
a semiconductor island including:
a source region;
a drain region;
at least a first channel forming region, a second channel forming region and a third channel forming region, each being formed between the source and drain regions;
a gate insulating film;
a gate electrode adjacent to the semiconductor island having the gate insulating film therebetween;
wherein the gate electrode is divided into at least a first gate electrode portion, a second gate electrode portion and a third gate electrode portion;
wherein the first gate electrode portion is formed over the first channel forming region and the closest to the drain region thereby the first channel forming region being defined the closest to the drain region;
wherein the first gate electrode portion has the narrowest width so that the first channel forming region has the shortest channel length;
wherein the third gate electrode portion is formed over the third channel forming region and the closest to the source region thereby the third channel forming region being defined the closest to the source region;
wherein the third gate electrode portion has the widest width so that the third channel forming region has the longest channel length;
wherein each of the first, second and third gate electrode portions has two end portions and a middle portion formed between the two end portions, each of the end and middle portions being located in a channel width direction;
wherein the middle portion of each of the first, second and third gate electrodes has the widest width so that a middle portion of each of the first, second and third channel forming regions has the longest channel length; and
wherein a current flows from the source region to the drain region through each of the first, second, and third channel forming regions in a channel length direction.
22. A device according to
claim 21
,
wherein the semiconductor island comprises crystalline silicon.
23. A device according to
claim 21
,
wherein the gate electrode overlaps with the semiconductor island having the gate insulating film therebetween.
24. A device according to
claim 21
,
wherein the EL display device is used in one selected from the group consisting of a TV camera, a head mount display, a car navigation system, a projector, a video camera, a personal computer.
US09/736,139 1996-11-21 2000-12-13 Active matrix display device having multiple gate electrode portions Expired - Lifetime US6426517B2 (en)

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US20030127651A1 (en) * 2001-12-27 2003-07-10 Satoshi Murakami Light emitting device and method of manufacturing the same
US20030181043A1 (en) * 2001-12-28 2003-09-25 Yoshifumi Tanada Semiconductor device, manufacturing method thereof, and electric device using the semiconductor device or the manufacturing method
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US20040065902A1 (en) * 1999-06-04 2004-04-08 Semiconductor Energy Laboratory., Ltd. Electro-optical device and electronic device
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US20050029519A1 (en) * 2002-03-15 2005-02-10 Semiconductor Energy Laboratory Co., Ltd. TV set and digital camera
US20050095758A1 (en) * 2001-12-19 2005-05-05 Samsung Sdi Co., Ltd. CMOS thin film transistor
US20050098784A1 (en) * 2002-01-17 2005-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US20050161742A1 (en) * 2001-12-28 2005-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US7022564B1 (en) * 2004-10-14 2006-04-04 Semiconductor Components Industries, L.L.C. Method of forming a low thermal resistance device and structure
US20060084228A1 (en) * 2004-10-14 2006-04-20 Semiconductor Components Industries, Llc. Low thermal resistance semiconductor device and method therefor
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US6274896B1 (en) * 2000-01-14 2001-08-14 Lexmark International, Inc. Drive transistor with fold gate
TW521303B (en) 2000-02-28 2003-02-21 Semiconductor Energy Lab Electronic device
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US7045444B2 (en) 2000-12-19 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device that includes selectively adding a noble gas element
US6858480B2 (en) * 2001-01-18 2005-02-22 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
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US7115453B2 (en) * 2001-01-29 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
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US7141822B2 (en) * 2001-02-09 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
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JP4993810B2 (en) 2001-02-16 2012-08-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6812081B2 (en) * 2001-03-26 2004-11-02 Semiconductor Energy Laboratory Co.,.Ltd. Method of manufacturing semiconductor device
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US20030202307A1 (en) * 2002-04-26 2003-10-30 Kei-Kang Hung Semiconductor device with ESD protection
US6861338B2 (en) * 2002-08-22 2005-03-01 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and method of manufacturing the same
AU2003264515A1 (en) 2002-09-20 2004-04-08 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US7374976B2 (en) * 2002-11-22 2008-05-20 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin film transistor
TW595005B (en) * 2003-08-04 2004-06-21 Au Optronics Corp Thin film transistor and pixel structure with the same
TWI255150B (en) 2003-12-22 2006-05-11 Lg Philips Lcd Co Ltd Organic electroluminescent device and method of fabricating the same
US7994509B2 (en) 2005-11-01 2011-08-09 Hewlett-Packard Development Company, L.P. Structure and method for thin film device with stranded conductor
US7588970B2 (en) * 2005-06-10 2009-09-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2007011061A1 (en) * 2005-07-22 2007-01-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101404582B1 (en) * 2006-01-20 2014-06-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Driving method of display device
JP4348644B2 (en) * 2006-09-26 2009-10-21 セイコーエプソン株式会社 Thin film transistor, electro-optical device and electronic apparatus
JP4548408B2 (en) * 2006-11-29 2010-09-22 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP2008135605A (en) * 2006-11-29 2008-06-12 Seiko Epson Corp Semiconductor device, and electrooptical device
US20090072313A1 (en) * 2007-09-19 2009-03-19 International Business Machines Corporation Hardened transistors in soi devices
US8890256B2 (en) * 2009-03-20 2014-11-18 International Business Machines Corporation Structure for heavy ion tolerant device, method of manufacturing the same and structure thereof
KR20120131775A (en) * 2011-05-26 2012-12-05 삼성디스플레이 주식회사 A thin film transistor, a method for manufacturing the same, and an organic light emitting display apparatus
JP2018046243A (en) 2016-09-16 2018-03-22 株式会社東芝 Semiconductor device and memory element
CN109037240B (en) * 2018-07-27 2020-11-10 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof, display panel and display device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58171860A (en) 1982-04-01 1983-10-08 Seiko Epson Corp Thin film transistor
US5331192A (en) * 1989-06-15 1994-07-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US5272369A (en) * 1990-03-28 1993-12-21 Interuniversitair Micro-Elektronica Centrum Vzw Circuit element with elimination of kink effect
DE69128876T2 (en) * 1990-11-30 1998-08-06 Sharp Kk Thin film semiconductor device
US5569936A (en) 1993-03-12 1996-10-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device employing crystallization catalyst
JP2936998B2 (en) * 1994-03-15 1999-08-23 日本電気株式会社 Frequency converter
JP3126630B2 (en) * 1994-06-20 2001-01-22 キヤノン株式会社 display
US5777360A (en) * 1994-11-02 1998-07-07 Lsi Logic Corporation Hexagonal field programmable gate array architecture
US5929464A (en) * 1995-01-20 1999-07-27 Semiconductor Energy Laboratory Co., Ltd. Active matrix electro-optical device
JPH1051007A (en) 1996-08-02 1998-02-20 Semiconductor Energy Lab Co Ltd Semiconductor device
JPH10154816A (en) * 1996-11-21 1998-06-09 Semiconductor Energy Lab Co Ltd Semiconductor device
US5821564A (en) * 1997-05-23 1998-10-13 Mosel Vitelic Inc. TFT with self-align offset gate

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6955953B2 (en) 1999-01-29 2005-10-18 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having thin film transistor and capacitor
US20040029338A1 (en) * 1999-01-29 2004-02-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US7575961B2 (en) 1999-04-07 2009-08-18 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device and a method of manufacturing the same
US7122835B1 (en) * 1999-04-07 2006-10-17 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device and a method of manufacturing the same
US20070026583A1 (en) * 1999-04-07 2007-02-01 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device and a method of manufacturing the same
US9123854B2 (en) 1999-06-04 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and electronic device
US7701134B2 (en) 1999-06-04 2010-04-20 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device with improved operating performance
US7741775B2 (en) 1999-06-04 2010-06-22 Semiconductor Energy Laboratories Co., Ltd. Electro-optical device and electronic device
US8853696B1 (en) 1999-06-04 2014-10-07 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and electronic device
US20050161672A1 (en) * 1999-06-04 2005-07-28 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and electronic device
US9368680B2 (en) 1999-06-04 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and electronic device
US20060192205A1 (en) * 1999-06-04 2006-08-31 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and electronic device
US20060097256A1 (en) * 1999-06-04 2006-05-11 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and electronic device
US20040065902A1 (en) * 1999-06-04 2004-04-08 Semiconductor Energy Laboratory., Ltd. Electro-optical device and electronic device
US7112475B2 (en) 2001-12-19 2006-09-26 Samsung Sdi Co., Ltd. Method of fabricating a thin film transistor with multiple gates using metal induced lateral crystallization
US7381990B2 (en) 2001-12-19 2008-06-03 Samsung Sdi Co., Ltd. Thin film transistor with multiple gates fabricated using super grain silicon crystallization
US20050158928A1 (en) * 2001-12-19 2005-07-21 Woo-Young So Method of fabricating thin film transistor with multiple gates using super grain silicon crystallization
US6933526B2 (en) 2001-12-19 2005-08-23 Samsung Sdi Co., Ltd. CMOS thin film transistor
US20050191799A1 (en) * 2001-12-19 2005-09-01 Samsung Sdi Co., Ltd. Thin film transistor with multiple gates using metal induced lateral crystallization and method of fabricating the same
US20050191798A1 (en) * 2001-12-19 2005-09-01 Samsung Sdi Co., Ltd. Thin film transistor with multiple gates using metal induced lateral crystallization and method of fabricating the same
US20050158920A1 (en) * 2001-12-19 2005-07-21 Woo-Young So Thin film transistor with multiple gates using super grain silicon crystallization
US7001802B2 (en) 2001-12-19 2006-02-21 Samsung Sdi Co., Ltd. Thin film transistor with multiple gates using metal induced lateral crystalization and method of fabricating the same
EP1326282A3 (en) * 2001-12-19 2004-12-15 Samsung SDI Co. Ltd. Thin film transistor with multiple gates
US20040253772A1 (en) * 2001-12-19 2004-12-16 Samsung Sdi Co., Ltd. Thin film transistor with multiple gates using metal induced lateral crystalization and method of fabricating the same
US20050095758A1 (en) * 2001-12-19 2005-05-05 Samsung Sdi Co., Ltd. CMOS thin film transistor
US7211475B2 (en) 2001-12-19 2007-05-01 Samsung Sdi Co., Ltd. CMOS thin film transistor
US20050093065A1 (en) * 2001-12-19 2005-05-05 Woo-Young So Method for fabricating thin film transistor with multiple gates using metal induced lateral crystallization
US7235435B2 (en) 2001-12-19 2007-06-26 Samsung Sdi Co., Ltd. Method for fabricating thin film transistor with multiple gates using metal induced lateral crystallization
US7235434B2 (en) 2001-12-19 2007-06-26 Samsung Sdi Co., Ltd. Thin film transistor with multiple gates using metal induced lateral crystallization and method of fabricating the same
US7294537B2 (en) * 2001-12-19 2007-11-13 Samsung Sdi Co., Ltd. Method of fabricating thin film transistor with multiple gates using super grain silicon crystallization
US7208352B2 (en) 2001-12-19 2007-04-24 Samsung Sdi Co., Ltd. Method of fabricating a thin film transistor with multiple gates using metal induced lateral crystallization
US20050095753A1 (en) * 2001-12-19 2005-05-05 Woo-Young So Thin film transistor with multiple gates using metal induced lateral crystallization and method of fabricating the same
US7492012B2 (en) 2001-12-27 2009-02-17 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US6861710B2 (en) 2001-12-27 2005-03-01 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US20060151789A1 (en) * 2001-12-27 2006-07-13 Semiconductor Energy Laboratory Co., Ltd., A Japan Corporation Light Emitting Device and Method of Manufacturing the Same
US20050156172A1 (en) * 2001-12-27 2005-07-21 Semiconductor Energy Laboratory Co., Ltd. A Japan Corporation Light emitting device and method of manufacturing the same
US7033848B2 (en) 2001-12-27 2006-04-25 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US20030127651A1 (en) * 2001-12-27 2003-07-10 Satoshi Murakami Light emitting device and method of manufacturing the same
US7115903B2 (en) 2001-12-28 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device producing system
US20050161742A1 (en) * 2001-12-28 2005-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US20070034877A1 (en) * 2001-12-28 2007-02-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device producing system
US7176490B2 (en) 2001-12-28 2007-02-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7226817B2 (en) 2001-12-28 2007-06-05 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing
US7538350B2 (en) 2001-12-28 2009-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor thin film device
US20030181043A1 (en) * 2001-12-28 2003-09-25 Yoshifumi Tanada Semiconductor device, manufacturing method thereof, and electric device using the semiconductor device or the manufacturing method
US7652286B2 (en) 2001-12-28 2010-01-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device producing system
US20030230749A1 (en) * 2001-12-28 2003-12-18 Atsuo Isobe Semiconductor device and semiconductor device producing system
US20070070346A1 (en) * 2002-01-17 2007-03-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US20050098784A1 (en) * 2002-01-17 2005-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US7148507B2 (en) 2002-01-17 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having thin film transistor with position controlled channel formation region
US7582162B2 (en) 2002-01-17 2009-09-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US7166863B2 (en) 2002-03-15 2007-01-23 Semiconductor Energy Laboratory Co. Ltd. Semiconductor element, semiconductor device, electronic device, TV set and digital camera
US20050029519A1 (en) * 2002-03-15 2005-02-10 Semiconductor Energy Laboratory Co., Ltd. TV set and digital camera
US20060084210A1 (en) * 2004-10-14 2006-04-20 Semiconductor Components Industries, Llc Method of forming a low thermal resistance device and structure
CN100479094C (en) * 2004-10-14 2009-04-15 半导体元件工业有限责任公司 Method of forming a low thermal resistance device and structure
US20060084228A1 (en) * 2004-10-14 2006-04-20 Semiconductor Components Industries, Llc. Low thermal resistance semiconductor device and method therefor
US7022564B1 (en) * 2004-10-14 2006-04-04 Semiconductor Components Industries, L.L.C. Method of forming a low thermal resistance device and structure
US7138315B2 (en) 2004-10-14 2006-11-21 Semiconductor Components Industries, L.L.C. Low thermal resistance semiconductor device and method therefor
US20130075621A1 (en) * 2011-09-22 2013-03-28 Canon Kabushiki Kaisha Radiation detection apparatus and detection system including same
US20150280008A1 (en) * 2014-03-27 2015-10-01 Boe Technology Group Co., Ltd. Multi-gate thin film transistor, array substrate and display device
US9553196B2 (en) * 2014-03-27 2017-01-24 Boe Technology Group Co., Ltd. Multi-gate thin film transistor, array substrate and display device
CN107195673A (en) * 2017-05-19 2017-09-22 北京华进创威电子有限公司 A kind of long GaNHEMT grid structures of non-homogeneous grid and device
WO2024000451A1 (en) * 2022-06-30 2024-01-04 京东方科技集团股份有限公司 Thin film transistor, shift register unit, gate driving circuit and display panel

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