US20010000646A1 - Test system with mechanical alignment for semiconductor chip scale packages and dice - Google Patents
Test system with mechanical alignment for semiconductor chip scale packages and dice Download PDFInfo
- Publication number
- US20010000646A1 US20010000646A1 US09/745,093 US74509300A US2001000646A1 US 20010000646 A1 US20010000646 A1 US 20010000646A1 US 74509300 A US74509300 A US 74509300A US 2001000646 A1 US2001000646 A1 US 2001000646A1
- Authority
- US
- United States
- Prior art keywords
- alignment
- component
- interconnect
- test system
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- This invention relates generally to testing of semiconductor components, such as chip scale packages and bare dice. More particularly, this invention relates to a test system with mechanical alignment and to a method for fabricating the test system.
- Chip scale package A recently developed semiconductor package is known as a “chip scale package” or a “chip size package”.
- the dice contained in these packages are referred to as being “minimally packaged”.
- Chip scale packages can be constructed in “cased” or “uncased” configurations. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. Uncased chip scale packages have a peripheral outline that is about the same as an unpackaged die.
- a cased chip scale package includes a substrate formed of plastic, ceramic, or other electrically insulating material bonded to the face of the die.
- the substrate can include external contacts for making outside electrical connections to the chip scale package.
- the external contacts for a chip scale package can comprise contact bumps arranged in a ball grid array (BGA), or a fine ball grid array (FBGA).
- BGA ball grid array
- FBGA fine ball grid array
- the external contacts comprise a solder material, that permits the chip scale package to be flip chip bonded to a printed circuit board, or other substrate.
- Uncased chip scale packages can include external contacts formed directly on the device bond pads in the manner of a bumped die.
- Test apparatus can be used to house one or more chip scale packages for testing, and to make temporary electrical connections with the external contacts on the chip scale packages.
- the test apparatus can include an interconnect component having contact members adapted to make the temporary electrical connections with the external contacts on the chip scale packages.
- the contact members on the interconnect must be aligned with the external contacts on the chip scale packages.
- One method of alignment is with an optical alignment system such as described in U.S. Pat. No. 5,634,267 to Wood et al.
- Another method of alignment is with a mechanical alignment system.
- the present invention is directed to a test system with an improved mechanical alignment system.
- the test system can be used to test chip scale packages or other semiconductor components such as bare semiconductor dice.
- test system for semiconductor components and a method for fabricating the test system are provided.
- the components can be chip scale packages, or bare semiconductor dice, having external contacts in the form of contact bumps.
- the test system includes a base for retaining one or more components, and multiple interconnects having contact members for making temporary electrical connections with the external contacts on the components.
- the test system also includes a mechanical alignment fixture having alignment surfaces for aligning the components to the interconnects.
- a single alignment fixture can be formed on the base, or separate alignment fixtures can be formed on each interconnect.
- the components can include alignment members configured to interact with the alignment surfaces on the alignment fixture and guide the components into alignment with the interconnects.
- Illustrative alignment members include beveled edges, alignment bumps, and alignment posts formed on the components.
- the alignment fixtures include alignment surfaces of a desired configuration.
- the alignment surfaces can include openings in the alignment fixtures sized to engage the alignment members on the components.
- the alignment surfaces can also be configured for engaging the edges of the components, or for engaging the contact bumps on the components.
- the alignment surfaces can be configured for a two stage alignment procedure including a coarse alignment stage and a fine alignment stage. In the two stage embodiment, a first layer of the alignment fixture can provide a first surface for coarse alignment, while a second layer of the alignment fixture can provide a second surface for fine alignment.
- the alignment fixture can comprise a polymeric material, such as a thick film resist, which is deposited on the interconnects, developed with alignment surfaces, and then cured.
- a polymeric material such as a thick film resist
- the thick film resist is deposited on a wafer that includes multiple interconnects, which are singulated following development and curing of the resist.
- the alignment fixture can comprise a polymer tape applied to the interconnects in a desired pattern.
- the alignment fixture can comprise a separate plate attached to the interconnects, or to the base of the system.
- FIG. 1A is a schematic side elevation view of a prior art component in the form of a bumped semiconductor die
- FIGS. 1B and 1C are schematic cross sectional views of prior art components in the form of chip scale packages
- FIG. 2A is a schematic perspective view of a test system constructed in accordance with the invention and illustrated in an unassembled configuration
- FIG. 2B is a schematic perspective view of an alternate embodiment test system illustrated in an assembled configuration
- FIG. 3 is a schematic perspective view of an interconnect component for the test system of FIG. 2A or 2 B;
- FIG. 3A is an enlarged cross sectional view taken along section line 3 A— 3 A of FIG. 3 illustrating a contact member of the interconnect;
- FIGS. 4A and 4B are enlarged cross sectional views of an alternate embodiment contact member
- FIG. 5 is a schematic side elevation view of a semiconductor component having alignment members in the form of beveled edges;
- FIG. 5A is a bottom view taken along section line 5 A— 5 A of FIG. 5;
- FIG. 6 is a schematic side elevation view of a semiconductor component having alignment members in the form of alignment bumps
- FIG. 6A is a bottom view taken along section line 6 A— 6 A of FIG. 6;
- FIG. 7 is a schematic side elevation view of a semiconductor component having alignment members in the form of alignment posts;
- FIG. 8A is a schematic cross sectional view taken along section line 8 A— 8 A of FIG. 2A illustrating an alignment fixture of the system during alignment of a component of FIG. 5;
- FIG. 8B is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 6;
- FIG. 8C is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 7;
- FIG. 8D is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 1A;
- FIG. 8E is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 1A.
- a bumped semiconductor die 10 includes a pattern of contact bumps 12 .
- the contact bumps 12 are arranged in a dense array.
- the contact bumps 12 can be arranged in a ball grid array (BGA), or a fine ball grid array (FBGA).
- BGA ball grid array
- FBGA fine ball grid array
- the contact bumps 12 are in electrical communication with various semiconductor devices and integrated circuits formed on the die 10 .
- the contact bumps 12 can be formed by processes that are known in the art, such as electro-deposition, and ball limiting metallurgy (BLM). Typically, the contact bumps 12 comprise a solder alloy. Representative solder alloys for the contact bumps 12 include 95%Pb/5%Sn, 60%Pb/40%Sn, 63%In/37%Sn, 100%Sn, and 62%Pb/36%Sn/2%Ag. Each contact bump 12 can be generally hemispherical, convex, or dome-shaped, with an outside diameter “D” and a height of “H”. Representative size ranges for the diameter “D” and height “H” can be from about 2.5 mils to 30 mils.
- a die 10 A can also be contained within a chip scale package 14 A.
- the chip scale package 14 A comprises a BGA substrate 16 bonded to the face of the die 10 A with an adhesive layer 18 .
- the BGA substrate 16 includes contact bumps 12 in electrical communication with the contact bumps 12 on the die 10 A.
- the contact bumps 12 on the BGA substrate 16 are substantially equivalent to the contact bumps 12 (FIG. 1A) previously described.
- a chip scale package 14 B comprises a semiconductor die 10 B, and protective members 20 bonded to either side of the die 10 B.
- the chip scale package 14 B includes contact bumps 12 in electrical communication with the die bond pads via leads 22 .
- An encapsulant 24 and an elastomeric pad 26 electrically isolate the leads 22 and the contact bumps 12 .
- these configurations are merely exemplary and other chip scale package configurations are known in the art.
- test system 28 constructed in accordance with the invention is illustrated.
- the test system 28 is configured to test multiple semiconductor components 30 A.
- the test system 28 includes a base 32 configured to retain the components 30 A.
- the base 32 includes external contacts 34 configured for mating electrical engagement with a test apparatus 52 , such as a burn-in board.
- the test apparatus 52 is in electrical communication with test circuitry 54 .
- the test circuitry 54 is configured to apply test signals to the integrated circuits contained on the components 30 A and to analyze the resultant signals.
- the test system 28 also includes multiple interconnects 36 mounted to the base 32 .
- the interconnects 36 include patterns of contact members 38 configured to form non-bonded, temporary electrical connections, with the contact bumps 12 on the components 30 A.
- the test system 28 includes a force applying mechanism 40 configured to bias the components 30 A against the interconnects 36 .
- the force applying mechanism comprises a bridge clamp 42 having clip portions 44 attachable to the base 32 , and leaf springs 46 attached to the bridge clamp 42 .
- the test system 28 also includes a mechanical alignment fixture 48 configured to align the components 30 A to the interconnects 36 .
- the alignment fixture 48 comprises a polymer fence formed on the base 32 and interconnects 36 .
- the alignment fixture 48 includes alignment surfaces in the form of alignment openings 50 .
- Each alignment opening 50 can be sized and shaped to contact alignment members 72 A on the components 30 A to be hereinafter described.
- the alignment openings 50 can be configured to contact outside edges of the components 30 A, or to contact the contact bumps 12 on the components 30 A.
- an alternate embodiment test system 28 A includes a force applying mechanism 40 A with elastomeric spring members 46 A.
- the elastomeric spring members 46 A can be formed of a material such as silicone, butyl rubber, or fluorosilicone. Suitable elastomeric materials include “PORON” available from Rogers.
- the elastomeric spring members 46 A can be secured to the bridge clamp 42 using an adhesive such as silicone.
- One suitable adhesive is “ZYMET” silicone elastomer manufactured by Zymet, Inc., East Hanover, N.J. Rather than being formed of elastomeric materials, the spring members 46 A can be formed as compressible gas filled bladders. This type of bladder is available from Paratech of Frankfort, Ill. under the trademark “MAXI FORCE AIR BAG”.
- the interconnect 36 includes the contact members 38 in patterns matching the patterns of the contact bumps 12 on the components 30 A.
- the interconnect 36 includes patterns of conductors 56 , and bonding pads 58 , in electrical communication with the contact members 38 .
- the bonding pads 58 can be formed on recessed surfaces 37 located along opposite edges of the interconnect 36 .
- the base 32 also includes patterns of conductors 60 in electrical communication with the external contacts 34 on the base 32 .
- Bond wires 62 can be bonded to the bonding pads 58 on the interconnect 36 , and to the conductors 60 on the base 32 to establish electrical communication therebetween.
- the recessed surfaces 37 of the interconnect 36 allow the bond wires 62 to be attached with a minimum of interference with other system components. Electrical paths between the interconnect 36 and base 32 can also be formed by flex circuit (not shown) or mechanical electrical connectors such as clips or pins (not shown).
- each contact member 38 comprises an indentation 64 formed in a substrate 68 of the interconnect 36 .
- Each indentation 64 is covered with a conductive layer 66 in electrical communication with a corresponding conductor 56 formed on a surface of the substrate 68 .
- Each indentation 64 is sized to retain and electrically contact an individual contact bump 12 .
- each indentation 64 can include sloped sidewalls for guiding and aligning the contact bumps 12 .
- the substrate 68 of the interconnect 36 can comprise ceramic, plastic, polyimide, FR-4, photo-machineable glass, or a semiconducting material, such as silicon.
- the indentations 64 for the contact members 38 can be formed by etching or machining the substrate 68 .
- the conductive layer 66 and conductors 56 can be formed within the indentations 64 , and on the surface of the substrate 68 out of highly conductive metals, such as aluminum, copper and tungsten, using a suitable metallization process (deposition, patterning, etching).
- an alternate embodiment contact member 38 S includes a stepped indentation 64 S.
- the stepped indentation 64 S can have a stepped-pyramidal, or inverted (“ziggurat” ) shape, comprising an upper cavity with sloped walls, and a smaller lower cavity with sloped walls.
- the indentation 64 S is covered by a conductive layer 66 S in electrical communication with a corresponding conductor 56 S.
- the conductive layer 66 S includes edges 70 .
- the indentation 64 S can be sized such that the edges 70 penetrate any oxide layers and electrically engage the contact bumps 12 . As shown in FIG.
- some contact bumps 12 may press into the lower cavity of the indentation 64 S to form a deformed contact bump 12 D.
- the upper cavity of the indentation 64 S limits further deformation of the contact bump 12 .
- the semiconductor component 30 A configured for use with the test system 28 (FIG. 2A) is illustrated.
- the semiconductor component 30 A comprises a semiconductor die (e.g., 10 -FIG. 1A) or a chip scale package (e.g., 14 A-FIG. 1B, 14 B-FIG. 1C) with contact bumps 12 formed substantially as previously described.
- the component 30 A includes an alignment member comprising a beveled edge 72 A formed on the outer periphery of the component 30 A along the face (circuit side) and edges thereof.
- the beveled edge 72 A can be configured to contact alignment surfaces on the alignment opening 50 (FIG. 2A) of the alignment fixture 48 (FIG. 2A), to guide and align the component 30 A with respect to the interconnect 36 (FIG. 2A).
- An angle of the beveled edge 72 A can be selected as required (e.g., 30°, 45°, 60°).
- the beveled edge 72 can be formed through a portion of a thickness of the component 30 A as shown, or through a full thickness of the component 30 A.
- One method for forming the beveled edge 72 A comprises fabricating the component 30 A on a wafer (not shown), and then sawing the wafer using a beveled saw blade.
- the beveled edge 72 A can be formed during a first saw cut with a beveled saw blade.
- a straight edged saw blade can be used to singulate the component 30 A from the wafer. Suitable saw blades with beveled edges are available from “DISCO” of Disco Hi-Tec America, Inc. Santa Clara, Calif.
- the component 30 B comprises a semiconductor die (e.g., die 10 -FIG. 1A) or a chip scale package (e.g., 14 A-FIG. 1B, 14 B-FIG. 1C) with contact bumps 12 .
- the component 30 B includes alignment members in the form of alignment bumps 72 B.
- the alignment bumps 72 B comprise polymer or metal bumps similar in size and shape to the contact bumps 12 .
- the alignment bumps 72 B are formed in a pattern along the peripheral edges of the component 30 B.
- alignment bumps 72 B located midway along the lateral and longitudinal edges of the component 30 B.
- the alignment bumps 72 B are configured to contact alignment surfaces of the alignment opening 50 (FIG. 2A) of the alignment fixture 48 (FIG. 2A), to guide and align the component 30 B with respect to the interconnect 36 (FIG. 2A).
- the alignment bumps 72 B can be formed using a suitable deposition process.
- screen printing or dispensing a viscous material through a nozzle can be employed. Suitable polymer materials include glob top or dam materials.
- metal alignment bumps screen printing, electroplating, or electroless deposition can be employed.
- metal pads can be formed on the component 30 B as nucleation and barrier layers for the alignment bumps 72 B.
- the alignment bumps 72 B can be formed of a same solder as the contact bumps 12 , or can be formed of a relatively hard metal such as nickel, copper, beryllium copper and alloys of these metals.
- the alignment bumps 72 B can have a height that is less than a height H (FIG. 1A) of the contact bumps 12 to permit the contact bumps 12 to engage the contact members 38 (FIG. 2 A) without interference.
- the alignment bumps 72 B can have a height selected to provide a force stop to prevent excessive deformation of the contact bumps 12 during engagement with the contact bumps 12 .
- the height of the alignment bumps 72 B can be about equal to an average height of the contact bumps 12 .
- FIGS. 7 and 7A another semiconductor component 30 C configured for use with the test system 28 (FIG. 2A) is shown.
- the component 30 C comprises a semiconductor die (e.g., 10 -FIG. 1A) or a chip scale package (e.g., 14 A-FIG. 1B, 14 B-FIG. 1C) with contact bumps 12 .
- the component 30 C includes alignment members in the form of alignment posts 72 C.
- the alignment posts 72 C comprise pillars of a desired shape having a height greater than the height H (FIG. 1A) of the contact bumps 12 .
- the alignment posts 72 C are configured for mating engagement with indentations 74 (FIG. 8C) in an interconnect 36 A (FIG.
- the alignment posts 72 C can be formed of polymers or metals, using suitable deposition processes substantially as previously described for the alignment bumps 72 B (FIG. 6). As shown in FIG. 7A, the alignment posts 72 C can be located in a desired pattern such as along the corner portions of the face of the component 30 C. In the illustrative embodiment, the alignment posts 72 C have a generally rectangular shaped cross section with a convex tip portion. Alternately, the alignment posts 72 C can be continuously formed along a periphery of the component 30 C.
- the alignment fixture 48 comprises a polymer layer deposited on the interconnect 36 .
- One suitable polymer for forming the alignment fixture 48 comprises a negative tone resist, which can be blanket deposited to a desired thickness, exposed with a pattern for the alignment openings 50 , developed to form the alignment openings 50 and then cured.
- deposition, exposing, developing and curing the polymer is using a wafer level fabrication process.
- multiple interconnects 36 can be formed on a single wafer and then singulated following the fabrication process.
- a suitable negative tone resist formulation is sold by Shell Chemical under the trademark “EPON RESIN SU-8”. Such a resist can be deposited to a thickness of from about 5-50 mils. In addition, the resist can be developed with high aspect ratio features including openings having almost vertical sidewalls.
- a conventional resist coating apparatus such as a spin coater, or a meniscus coater, can be used to deposit the resist onto a wafer containing multiple interconnects 36 . The deposited resist can then be “prebaked” at about 95° C. for about 15 minutes and exposed in a desired pattern using a conventional UV aligner with a dose of about 165 mJ/cm 2 . Developing can be accomplished with a solution of PGMEA (propyleneglycol-monomethylether-acetate). This can be followed by a “full cure” comprising a hard bake at about 200° C. for about 30 minutes.
- PGMEA propyleneglycol-monomethylether-acetate
- the above identified “EPON RESIN SU-8” resist formulation can be developed to form the alignment openings 50 with vertical alignment surfaces substantially as shown.
- the beveled edges 72 A of the components 30 A can contact the surfaces of the alignment openings 50 to align the component 30 A to the interconnect 36 .
- the alignment fixture 48 can also include an encapsulant 49 deposited on portions of the interconnect 36 and base 32 to encapsulate and protect the bond wires 62 .
- the encapsulant 49 can comprise a conventional glob top material such as an epoxy, silicone or polyimide.
- the encapsulant 49 can be formed by dispensing a required volume of viscous material over the bond wires 62 .
- a fence can also be formed on the substrate, as a mold for defining a perimeter of the encapsulant 49 .
- the encapsulant 49 can be cured at an elevated temperature (e.g. 165° C.) for a suitable period of time (e.g. 60 minutes).
- the encapsulant 49 can be deposited using a conventional process such as dispensing through a syringe.
- an alternate embodiment alignment fixture 48 A can be formed on the interconnects 36 for aligning components 30 B having alignment bumps 72 B.
- an alignment opening 50 A of the alignment fixture 48 A includes sloped alignment surfaces.
- the sloped alignment surfaces of the alignment opening 50 A are adapted to contact and guide the alignment bumps 72 B.
- the alignment fixture 48 A can comprise a conventional resist formulation deposited and developed as previously described, but with sloped surfaces for the alignment openings 50 A.
- the alignment fixture 48 A can comprise one or more layers of an adhesive tape, such as “KAPTON” tape by DuPont, or similar tape adapted for bonding lead-on-chip dice to leadframes.
- the tape With adhesive tape, the tape can be cut and applied in a desired pattern to form alignment openings 50 A of a desired size.
- the adhesive tape can be etched with beveled edges to form the sloped surfaces of the alignment openings 50 A.
- the alignment fixture 48 A can also be a separate piece of molded or machined plastic or other material attached to the interconnect 36 using an adhesive such as silicone.
- an alternate embodiment alignment fixture 48 B can be formed as a cured resist, as one or more layers of tape, or as a separate member, substantially as previously described.
- the alignment fixture 48 B includes an alignment opening 50 B having surfaces configured to contact and guide the alignment posts 72 C on component 30 C.
- an interconnect 36 A includes indentations 74 for receiving the alignment posts 72 C.
- an alternate embodiment alignment fixture 48 C comprises two separate layers of cured resist.
- the separate layers are configured to provide staged alignment for the bumped die 10 , or other semiconductor component.
- a first resist layer 76 comprises a conventional resist formulation that can be developed with a first opening 50 C 1 having sloped surfaces.
- a second resist layer 78 comprises the above “EPON RESIN SU-8” resist formulation that can be developed with a second opening 50 C 2 having vertical surfaces.
- the first opening 50 C 1 can be sized to guide the edges of the die 10 to provide a gross alignment stage.
- the second opening 50 C 2 can be sized to guide the edges of the die 10 to provide a fine alignment stage.
- This embodiment can also include an encapsulant 49 A formed over the bond wires 62 , substantially as previously described.
- an alternate embodiment alignment fixture 48 D has an alignment opening 50 D with sloped surfaces configured to engage the pattern of contact bumps 12 on the bumped die 10 .
- a thickness of the alignment fixture 48 D is preferably less than a height “H” of the contact bumps 12 .
- the alignment fixture 48 D can be a cured material, one or more layer of adhesive tape, or a separate member formed substantially as previously described. The cured material can also be formed on the surface of the interconnect 36 between the contact members 38 .
- the test system includes a test apparatus having an interconnect for electrically contacting the components, and an alignment fixture with alignment surfaces for aligning the components to the interconnect.
- the components can include alignment members configured to engage and interact with the alignment surfaces.
Abstract
A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.
Description
- This invention relates generally to testing of semiconductor components, such as chip scale packages and bare dice. More particularly, this invention relates to a test system with mechanical alignment and to a method for fabricating the test system.
- A recently developed semiconductor package is known as a “chip scale package” or a “chip size package”. The dice contained in these packages are referred to as being “minimally packaged”. Chip scale packages can be constructed in “cased” or “uncased” configurations. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. Uncased chip scale packages have a peripheral outline that is about the same as an unpackaged die.
- Typically, a cased chip scale package includes a substrate formed of plastic, ceramic, or other electrically insulating material bonded to the face of the die. The substrate can include external contacts for making outside electrical connections to the chip scale package. For example, the external contacts for a chip scale package can comprise contact bumps arranged in a ball grid array (BGA), or a fine ball grid array (FBGA). Typically, the external contacts comprise a solder material, that permits the chip scale package to be flip chip bonded to a printed circuit board, or other substrate. Uncased chip scale packages can include external contacts formed directly on the device bond pads in the manner of a bumped die.
- Following the manufacturing process, chip scale packages must be tested and burned-in. Test apparatus can be used to house one or more chip scale packages for testing, and to make temporary electrical connections with the external contacts on the chip scale packages. The test apparatus can include an interconnect component having contact members adapted to make the temporary electrical connections with the external contacts on the chip scale packages.
- For making the electrical connections the contact members on the interconnect must be aligned with the external contacts on the chip scale packages. One method of alignment is with an optical alignment system such as described in U.S. Pat. No. 5,634,267 to Wood et al. Another method of alignment is with a mechanical alignment system.
- The present invention is directed to a test system with an improved mechanical alignment system. The test system can be used to test chip scale packages or other semiconductor components such as bare semiconductor dice.
- In accordance with the present invention, a test system for semiconductor components, and a method for fabricating the test system are provided. The components can be chip scale packages, or bare semiconductor dice, having external contacts in the form of contact bumps.
- The test system includes a base for retaining one or more components, and multiple interconnects having contact members for making temporary electrical connections with the external contacts on the components. The test system also includes a mechanical alignment fixture having alignment surfaces for aligning the components to the interconnects. A single alignment fixture can be formed on the base, or separate alignment fixtures can be formed on each interconnect. In addition to the alignment fixture, the components can include alignment members configured to interact with the alignment surfaces on the alignment fixture and guide the components into alignment with the interconnects. Illustrative alignment members include beveled edges, alignment bumps, and alignment posts formed on the components.
- Several different embodiments of alignment fixtures are disclosed. In each embodiment the alignment fixtures include alignment surfaces of a desired configuration. For example, the alignment surfaces can include openings in the alignment fixtures sized to engage the alignment members on the components. The alignment surfaces can also be configured for engaging the edges of the components, or for engaging the contact bumps on the components. Still further, the alignment surfaces can be configured for a two stage alignment procedure including a coarse alignment stage and a fine alignment stage. In the two stage embodiment, a first layer of the alignment fixture can provide a first surface for coarse alignment, while a second layer of the alignment fixture can provide a second surface for fine alignment.
- The alignment fixture can comprise a polymeric material, such as a thick film resist, which is deposited on the interconnects, developed with alignment surfaces, and then cured. Preferably, the thick film resist is deposited on a wafer that includes multiple interconnects, which are singulated following development and curing of the resist. Alternately, the alignment fixture can comprise a polymer tape applied to the interconnects in a desired pattern. As another alternative, the alignment fixture can comprise a separate plate attached to the interconnects, or to the base of the system.
- FIG. 1A is a schematic side elevation view of a prior art component in the form of a bumped semiconductor die;
- FIGS. 1B and 1C are schematic cross sectional views of prior art components in the form of chip scale packages;
- FIG. 2A is a schematic perspective view of a test system constructed in accordance with the invention and illustrated in an unassembled configuration;
- FIG. 2B is a schematic perspective view of an alternate embodiment test system illustrated in an assembled configuration;
- FIG. 3 is a schematic perspective view of an interconnect component for the test system of FIG. 2A or2B;
- FIG. 3A is an enlarged cross sectional view taken along
section line 3A—3A of FIG. 3 illustrating a contact member of the interconnect; - FIGS. 4A and 4B are enlarged cross sectional views of an alternate embodiment contact member;
- FIG. 5 is a schematic side elevation view of a semiconductor component having alignment members in the form of beveled edges;
- FIG. 5A is a bottom view taken along
section line 5A—5A of FIG. 5; - FIG. 6 is a schematic side elevation view of a semiconductor component having alignment members in the form of alignment bumps;
- FIG. 6A is a bottom view taken along
section line 6A—6A of FIG. 6; - FIG. 7 is a schematic side elevation view of a semiconductor component having alignment members in the form of alignment posts;
- FIG. 8A is a schematic cross sectional view taken along
section line 8A—8A of FIG. 2A illustrating an alignment fixture of the system during alignment of a component of FIG. 5; - FIG. 8B is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 6;
- FIG. 8C is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 7;
- FIG. 8D is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 1A; and
- FIG. 8E is a schematic cross sectional view equivalent to FIG. 8A illustrating an alternate embodiment alignment fixture during alignment of the component of FIG. 1A.
- Referring to FIGS. 1A-1C, prior art semiconductor components are illustrated. In FIG. 1A, a bumped semiconductor die10 includes a pattern of contact bumps 12. Typically the contact bumps 12 are arranged in a dense array. By way of example, the contact bumps 12 can be arranged in a ball grid array (BGA), or a fine ball grid array (FBGA). The contact bumps 12 are in electrical communication with various semiconductor devices and integrated circuits formed on the
die 10. - The contact bumps12 can be formed by processes that are known in the art, such as electro-deposition, and ball limiting metallurgy (BLM). Typically, the contact bumps 12 comprise a solder alloy. Representative solder alloys for the contact bumps 12 include 95%Pb/5%Sn, 60%Pb/40%Sn, 63%In/37%Sn, 100%Sn, and 62%Pb/36%Sn/2%Ag. Each
contact bump 12 can be generally hemispherical, convex, or dome-shaped, with an outside diameter “D” and a height of “H”. Representative size ranges for the diameter “D” and height “H” can be from about 2.5 mils to 30 mils. - Referring to FIG. 1B, a
die 10A can also be contained within achip scale package 14A. Thechip scale package 14A comprises aBGA substrate 16 bonded to the face of thedie 10A with anadhesive layer 18. TheBGA substrate 16 includes contact bumps 12 in electrical communication with the contact bumps 12 on thedie 10A. The contact bumps 12 on theBGA substrate 16 are substantially equivalent to the contact bumps 12 (FIG. 1A) previously described. - Referring to FIG. 1C, a
chip scale package 14B comprises a semiconductor die 10B, andprotective members 20 bonded to either side of the die 10B. In addition, thechip scale package 14B includes contact bumps 12 in electrical communication with the die bond pads via leads 22. Anencapsulant 24 and anelastomeric pad 26 electrically isolate theleads 22 and the contact bumps 12. As is apparent, these configurations are merely exemplary and other chip scale package configurations are known in the art. - Referring to FIG. 2A, a
test system 28 constructed in accordance with the invention is illustrated. Thetest system 28 is configured to testmultiple semiconductor components 30A. Thetest system 28 includes a base 32 configured to retain thecomponents 30A. Thebase 32 includesexternal contacts 34 configured for mating electrical engagement with atest apparatus 52, such as a burn-in board. Thetest apparatus 52 is in electrical communication withtest circuitry 54. Thetest circuitry 54 is configured to apply test signals to the integrated circuits contained on thecomponents 30A and to analyze the resultant signals. - The
test system 28 also includesmultiple interconnects 36 mounted to thebase 32. Theinterconnects 36 include patterns ofcontact members 38 configured to form non-bonded, temporary electrical connections, with the contact bumps 12 on thecomponents 30A. In addition, thetest system 28 includes aforce applying mechanism 40 configured to bias thecomponents 30A against theinterconnects 36. In the illustrative embodiment, the force applying mechanism comprises abridge clamp 42 havingclip portions 44 attachable to thebase 32, andleaf springs 46 attached to thebridge clamp 42. - The
test system 28 also includes amechanical alignment fixture 48 configured to align thecomponents 30A to theinterconnects 36. In the illustrative embodiment, thealignment fixture 48 comprises a polymer fence formed on thebase 32 and interconnects 36. Thealignment fixture 48 includes alignment surfaces in the form ofalignment openings 50. Eachalignment opening 50 can be sized and shaped to contactalignment members 72A on thecomponents 30A to be hereinafter described. Alternately, thealignment openings 50 can be configured to contact outside edges of thecomponents 30A, or to contact the contact bumps 12 on thecomponents 30A. - Referring to FIG. 2B, an alternate
embodiment test system 28A includes aforce applying mechanism 40A withelastomeric spring members 46A. Theelastomeric spring members 46A can be formed of a material such as silicone, butyl rubber, or fluorosilicone. Suitable elastomeric materials include “PORON” available from Rogers. Theelastomeric spring members 46A can be secured to thebridge clamp 42 using an adhesive such as silicone. One suitable adhesive is “ZYMET” silicone elastomer manufactured by Zymet, Inc., East Hanover, N.J. Rather than being formed of elastomeric materials, thespring members 46A can be formed as compressible gas filled bladders. This type of bladder is available from Paratech of Frankfort, Ill. under the trademark “MAXI FORCE AIR BAG”. - Referring to FIG. 3, the mounting of an
individual interconnect 36 to thebase 32 is illustrated. In FIG. 3, thealignment fixture 48 is not shown for illustrative purposes. Theinterconnect 36 includes thecontact members 38 in patterns matching the patterns of the contact bumps 12 on thecomponents 30A. In addition, theinterconnect 36 includes patterns ofconductors 56, andbonding pads 58, in electrical communication with thecontact members 38. Thebonding pads 58 can be formed on recessedsurfaces 37 located along opposite edges of theinterconnect 36. The base 32 also includes patterns ofconductors 60 in electrical communication with theexternal contacts 34 on thebase 32.Bond wires 62 can be bonded to thebonding pads 58 on theinterconnect 36, and to theconductors 60 on the base 32 to establish electrical communication therebetween. The recessed surfaces 37 of theinterconnect 36 allow thebond wires 62 to be attached with a minimum of interference with other system components. Electrical paths between theinterconnect 36 andbase 32 can also be formed by flex circuit (not shown) or mechanical electrical connectors such as clips or pins (not shown). - Referring to FIG. 3A, an
individual contact member 38 is illustrated in greater detail. In the illustrative embodiment, eachcontact member 38 comprises anindentation 64 formed in asubstrate 68 of theinterconnect 36. Eachindentation 64 is covered with aconductive layer 66 in electrical communication with a correspondingconductor 56 formed on a surface of thesubstrate 68. Eachindentation 64 is sized to retain and electrically contact anindividual contact bump 12. In addition, eachindentation 64 can include sloped sidewalls for guiding and aligning the contact bumps 12. - The
substrate 68 of theinterconnect 36 can comprise ceramic, plastic, polyimide, FR-4, photo-machineable glass, or a semiconducting material, such as silicon. Theindentations 64 for thecontact members 38 can be formed by etching or machining thesubstrate 68. Theconductive layer 66 andconductors 56 can be formed within theindentations 64, and on the surface of thesubstrate 68 out of highly conductive metals, such as aluminum, copper and tungsten, using a suitable metallization process (deposition, patterning, etching). - Referring to FIG. 4A, an alternate
embodiment contact member 38S includes a steppedindentation 64S. The steppedindentation 64S can have a stepped-pyramidal, or inverted (“ziggurat” ) shape, comprising an upper cavity with sloped walls, and a smaller lower cavity with sloped walls. Again theindentation 64S is covered by aconductive layer 66S in electrical communication with a correspondingconductor 56S. In this embodiment, theconductive layer 66S includes edges 70. Theindentation 64S can be sized such that theedges 70 penetrate any oxide layers and electrically engage the contact bumps 12. As shown in FIG. 4B, because of size variations in the contact bumps 12 and large biasing forces, some contact bumps 12 may press into the lower cavity of theindentation 64S to form a deformed contact bump 12D. In this case the upper cavity of theindentation 64S limits further deformation of thecontact bump 12. - Other types of contact members configured to make non-bonded, temporary electrical connections with contact bumps12 are described in the following U.S. patent applications, which are incorporated herein by reference:
- U.S. patent application Ser. No. 08/829,193, entitled “Interconnect Having Recessed Contact Members With Penetrating Blades For Testing Semiconductor Dice And Packages With Contact Bumps”;
- U.S. patent application Ser. No. 08/823,490, entitled “Method, Apparatus And System For Testing Bumped Semiconductor Components”; and
- U.S. patent application Ser. No. 08/867,551, entitled “Interconnect For Making Temporary Electrical Connections With Bumped Semiconductor Components.
- Referring to FIGS. 5 and 5A, a
semiconductor component 30A configured for use with the test system 28 (FIG. 2A) is illustrated. Thesemiconductor component 30A comprises a semiconductor die (e.g., 10-FIG. 1A) or a chip scale package (e.g., 14A-FIG. 1B, 14B-FIG. 1C) with contact bumps 12 formed substantially as previously described. In addition, thecomponent 30A includes an alignment member comprising abeveled edge 72A formed on the outer periphery of thecomponent 30A along the face (circuit side) and edges thereof. As will be further explained, thebeveled edge 72A can be configured to contact alignment surfaces on the alignment opening 50 (FIG. 2A) of the alignment fixture 48 (FIG. 2A), to guide and align thecomponent 30A with respect to the interconnect 36 (FIG. 2A). - An angle of the
beveled edge 72A can be selected as required (e.g., 30°, 45°, 60°). In addition, the beveled edge 72 can be formed through a portion of a thickness of thecomponent 30A as shown, or through a full thickness of thecomponent 30A. One method for forming thebeveled edge 72A comprises fabricating thecomponent 30A on a wafer (not shown), and then sawing the wafer using a beveled saw blade. For example, thebeveled edge 72A can be formed during a first saw cut with a beveled saw blade. During a second saw cut, a straight edged saw blade can be used to singulate thecomponent 30A from the wafer. Suitable saw blades with beveled edges are available from “DISCO” of Disco Hi-Tec America, Inc. Santa Clara, Calif. - Referring to FIGS. 6 and 6A, another
semiconductor component 30B configured for use with thetest system 28 is shown. Thecomponent 30B comprises a semiconductor die (e.g., die 10-FIG. 1A) or a chip scale package (e.g., 14A-FIG. 1B, 14B-FIG. 1C) with contact bumps 12. In addition, thecomponent 30B includes alignment members in the form of alignment bumps 72B. The alignment bumps 72B comprise polymer or metal bumps similar in size and shape to the contact bumps 12. The alignment bumps 72B are formed in a pattern along the peripheral edges of thecomponent 30B. In the illustrative embodiment there are fouralignment bumps 72B, located midway along the lateral and longitudinal edges of thecomponent 30B. As will be further explained, the alignment bumps 72B are configured to contact alignment surfaces of the alignment opening 50 (FIG. 2A) of the alignment fixture 48 (FIG. 2A), to guide and align thecomponent 30B with respect to the interconnect 36 (FIG. 2A). - Depending on the material, the alignment bumps72B can be formed using a suitable deposition process. For polymer alignment bumps 72B, screen printing or dispensing a viscous material through a nozzle can be employed. Suitable polymer materials include glob top or dam materials. For metal alignment bumps, screen printing, electroplating, or electroless deposition can be employed. In addition, depending on the deposition process, metal pads can be formed on the
component 30B as nucleation and barrier layers for the alignment bumps 72B. The alignment bumps 72B can be formed of a same solder as the contact bumps 12, or can be formed of a relatively hard metal such as nickel, copper, beryllium copper and alloys of these metals. - The alignment bumps72B can have a height that is less than a height H (FIG. 1A) of the contact bumps 12 to permit the contact bumps 12 to engage the contact members 38 (FIG. 2A) without interference. Alternately, the alignment bumps 72B can have a height selected to provide a force stop to prevent excessive deformation of the contact bumps 12 during engagement with the contact bumps 12. In this case, the height of the alignment bumps 72B can be about equal to an average height of the contact bumps 12.
- Referring to FIGS. 7 and 7A, another
semiconductor component 30C configured for use with the test system 28 (FIG. 2A) is shown. Thecomponent 30C comprises a semiconductor die (e.g., 10-FIG. 1A) or a chip scale package (e.g., 14A-FIG. 1B, 14B-FIG. 1C) with contact bumps 12. In addition, thecomponent 30C includes alignment members in the form ofalignment posts 72C. The alignment posts 72C comprise pillars of a desired shape having a height greater than the height H (FIG. 1A) of the contact bumps 12. The alignment posts 72C are configured for mating engagement with indentations 74 (FIG. 8C) in aninterconnect 36A (FIG. 8C). The alignment posts 72C can be formed of polymers or metals, using suitable deposition processes substantially as previously described for the alignment bumps 72B (FIG. 6). As shown in FIG. 7A, the alignment posts 72C can be located in a desired pattern such as along the corner portions of the face of thecomponent 30C. In the illustrative embodiment, the alignment posts 72C have a generally rectangular shaped cross section with a convex tip portion. Alternately, the alignment posts 72C can be continuously formed along a periphery of thecomponent 30C. - Referring to FIG. 8A, the construction of the
alignment fixture 48 and interaction with thesemiconductor component 30A is illustrated. In this embodiment, thealignment fixture 48 comprises a polymer layer deposited on theinterconnect 36. One suitable polymer for forming thealignment fixture 48 comprises a negative tone resist, which can be blanket deposited to a desired thickness, exposed with a pattern for thealignment openings 50, developed to form thealignment openings 50 and then cured. Preferably deposition, exposing, developing and curing the polymer is using a wafer level fabrication process. In particular,multiple interconnects 36 can be formed on a single wafer and then singulated following the fabrication process. - A suitable negative tone resist formulation is sold by Shell Chemical under the trademark “EPON RESIN SU-8”. Such a resist can be deposited to a thickness of from about 5-50 mils. In addition, the resist can be developed with high aspect ratio features including openings having almost vertical sidewalls. A conventional resist coating apparatus, such as a spin coater, or a meniscus coater, can be used to deposit the resist onto a wafer containing
multiple interconnects 36. The deposited resist can then be “prebaked” at about 95° C. for about 15 minutes and exposed in a desired pattern using a conventional UV aligner with a dose of about 165 mJ/cm2. Developing can be accomplished with a solution of PGMEA (propyleneglycol-monomethylether-acetate). This can be followed by a “full cure” comprising a hard bake at about 200° C. for about 30 minutes. - The above identified “EPON RESIN SU-8” resist formulation can be developed to form the
alignment openings 50 with vertical alignment surfaces substantially as shown. In this embodiment thebeveled edges 72A of thecomponents 30A can contact the surfaces of thealignment openings 50 to align thecomponent 30A to theinterconnect 36. - Still referring to FIG. 8A, the
alignment fixture 48 can also include anencapsulant 49 deposited on portions of theinterconnect 36 andbase 32 to encapsulate and protect thebond wires 62. Theencapsulant 49 can comprise a conventional glob top material such as an epoxy, silicone or polyimide. Theencapsulant 49 can be formed by dispensing a required volume of viscous material over thebond wires 62. A fence can also be formed on the substrate, as a mold for defining a perimeter of theencapsulant 49. Following dispensing, theencapsulant 49 can be cured at an elevated temperature (e.g. 165° C.) for a suitable period of time (e.g. 60 minutes). Theencapsulant 49 can be deposited using a conventional process such as dispensing through a syringe. - Referring to FIG. 8B, an alternate
embodiment alignment fixture 48A can be formed on theinterconnects 36 for aligningcomponents 30B having alignment bumps 72B. In this embodiment, analignment opening 50A of thealignment fixture 48A includes sloped alignment surfaces. The sloped alignment surfaces of thealignment opening 50A are adapted to contact and guide the alignment bumps 72B. Thealignment fixture 48A can comprise a conventional resist formulation deposited and developed as previously described, but with sloped surfaces for thealignment openings 50A. Alternately, thealignment fixture 48A can comprise one or more layers of an adhesive tape, such as “KAPTON” tape by DuPont, or similar tape adapted for bonding lead-on-chip dice to leadframes. With adhesive tape, the tape can be cut and applied in a desired pattern to formalignment openings 50A of a desired size. In addition, the adhesive tape can be etched with beveled edges to form the sloped surfaces of thealignment openings 50A. Thealignment fixture 48A can also be a separate piece of molded or machined plastic or other material attached to theinterconnect 36 using an adhesive such as silicone. - Referring to FIG. 8C, an alternate
embodiment alignment fixture 48B can be formed as a cured resist, as one or more layers of tape, or as a separate member, substantially as previously described. Thealignment fixture 48B includes analignment opening 50B having surfaces configured to contact and guide the alignment posts 72C oncomponent 30C. In this embodiment aninterconnect 36A includesindentations 74 for receiving the alignment posts 72C. - Referring to FIG. 8D, an alternate
embodiment alignment fixture 48C comprises two separate layers of cured resist. The separate layers are configured to provide staged alignment for the bumped die 10, or other semiconductor component. A first resistlayer 76 comprises a conventional resist formulation that can be developed with a first opening 50C1 having sloped surfaces. A second resistlayer 78 comprises the above “EPON RESIN SU-8” resist formulation that can be developed with a second opening 50C2 having vertical surfaces. The first opening 50C1 can be sized to guide the edges of the die 10 to provide a gross alignment stage. The second opening 50C2 can be sized to guide the edges of the die 10 to provide a fine alignment stage. This embodiment can also include an encapsulant 49A formed over thebond wires 62, substantially as previously described. - Referring to FIG. 8E, an alternate
embodiment alignment fixture 48D has analignment opening 50D with sloped surfaces configured to engage the pattern of contact bumps 12 on the bumped die 10. In this embodiment a thickness of thealignment fixture 48D is preferably less than a height “H” of the contact bumps 12. Thealignment fixture 48D can be a cured material, one or more layer of adhesive tape, or a separate member formed substantially as previously described. The cured material can also be formed on the surface of theinterconnect 36 between thecontact members 38. - Thus the invention provides an improved test system for semiconductor components including dice and chip scale packages. The test system includes a test apparatus having an interconnect for electrically contacting the components, and an alignment fixture with alignment surfaces for aligning the components to the interconnect. In addition the components can include alignment members configured to engage and interact with the alignment surfaces.
- While the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
Claims (43)
1. A test system for semiconductor components comprising:
a semiconductor component comprising external contacts and an alignment member formed thereon;
an interconnect comprising a plurality of contact members configured to make non-bonded electrical connections with the external contacts; and
an alignment fixture proximate to the interconnect, said alignment fixture including a surface configured to engage the alignment member to guide the component into alignment with the interconnect.
2. The test system as claimed in wherein the alignment fixture comprises a polymer layer on the interconnect and the surface comprises an opening in the layer.
claim 1
3. The test system as claimed in wherein the alignment member comprises a beveled edge on the component.
claim 1
4. The test system as claimed in wherein the alignment member comprises a pattern of bumps or posts on the component.
claim 1
5. The test system as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 1
6. A test system for semiconductor components comprising:
a semiconductor component comprising a plurality of contact bumps and an alignment member;
an interconnect comprising a plurality of indentations covered with conductive layers, said indentations configured to retain and electrically contact the contact bumps; and
an alignment fixture comprising a polymer layer deposited on the interconnect and formed with an opening having a surface for engaging the alignment member to align the contact bumps with the indentations.
7. The test system as claimed in wherein the alignment member comprises a beveled edge formed along a periphery of the component.
claim 6
8. The test system as claimed in wherein the alignment member comprises a pattern of bumps on the component sized to provide a force stop for the contact bumps.
claim 6
9. The test system as claimed in wherein the alignment member comprises a pattern of posts on the component engageable with a second plurality of indentations in the interconnect.
claim 6
10. The test system as claimed in wherein the opening includes a first surface configured for gross alignment of the component and a second surface configured for fine alignment of the component.
claim 6
11. The test system as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 6
12. A test system for semiconductor components comprising:
a semiconductor component comprising a plurality of external contacts;
an interconnect comprising a pattern of contact members configured to electrically contact the external contacts on the component; and
a alignment fixture comprising a first layer and a second layer deposited on the interconnect, said first layer comprising a first alignment opening having a first surface configured to align the component in a first stage, said second layer comprising a second alignment opening having a second surface configured to align the component in a second stage.
13. The test system as claimed in wherein the first layer comprises a first type of resist and the second layer comprises a second type resist.
claim 12
14. The test system as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 12
15. A test system for semiconductor components comprising:
a semiconductor component comprising a plurality of external contacts and a plurality of alignment members;
an interconnect comprising a plurality of contact members configured to electrically engage the external contacts and a plurality of indentations configured to receive the alignment members; and
an alignment fixture proximate to the interconnect, said alignment fixture comprising an opening with a surface configured to guide the alignment members into the indentations.
16. The test system as claimed in wherein the alignment members comprise a polymeric material.
claim 15
17. The test system as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 15
18. A test system for semiconductor components comprising:
a semiconductor component comprising a plurality of contact bumps having a first height;
an interconnect comprising a plurality of contact members comprising indentations covered with conductive layers, said indentations configured to retain and electrically contact the contact bumps; and
an alignment fixture on the interconnect, said alignment fixture comprising a surface configured to contact at least some of the contact bumps to align the contact bumps to the indentations, said alignment fixture having a second height less than the first height.
19. The system as claimed in wherein the alignment fixture comprises at least one layer of adhesive tape attached to the interconnect.
claim 18
20. The system as claimed in wherein the alignment fixture comprises a resist deposited on the interconnect, developed with an opening including the surface, and then cured.
claim 18
21. The test system as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 18
22. A test system for semiconductor components comprising:
a component comprising a pattern of contact bumps in a dense array and at least one alignment member;
a base configured to retain the component, said base comprising a plurality of external contacts connectable to test circuitry;
an interconnect mounted to the base, said interconnect comprising a plurality of contact members in electrical communication with the external contacts on the base; and
an alignment member attached to the base or to the interconnect, said alignment member including a surface configured to engage the alignment member on the component to align the contact bumps to the contact members.
23. The test system as claimed in wherein the alignment member comprises a beveled edge on the component.
claim 22
24. The test system as claimed in wherein the alignment member comprises a plurality of bumps on the component.
claim 22
25. The test system as claimed in wherein the alignment member comprises a plurality of posts on the component.
claim 22
26. The test system as claimed in wherein the alignment member comprises a polymer layer deposited on the interconnect, said polymer layer including an opening with the surface.
claim 22
27. The test system as claimed in wherein the alignment member comprises first and second polymer layers on the interconnect, said first polymer layer including a first opening, said second polymer layer including a second opening, said first and second openings forming the surface.
claim 22
28. An apparatus for testing a semiconductor component having contact bumps comprising:
an interconnect comprising a plurality of contact members configured to make temporary electrical connections with the contact bumps, said contact members comprising indentations sized to retain the contact bumps, said indentations covered with conductive layers; and
an alignment fixture comprising a polymer layer on the interconnect, said layer comprising an opening with a surface for guiding the component onto the interconnect with the contact bumps electrically engaging the contact members.
29. The apparatus as claimed in wherein the polymer layer comprises patterned and developed resist.
claim 28
30. An apparatus for testing a chip scale semiconductor package having contact bumps comprising:
a base configured to retain the package;
an interconnect on the base, said interconnect comprising a plurality of contact members configured to make temporary electrical connections with the contact bumps, said contact members comprising indentations sized to retain the contact bumps, said indentations covered with conductive layers;
a force applying mechanism for biasing the package against the interconnect; and
an alignment fixture comprising a first layer and a second layer deposited on the interconnect, said first layer comprising a first alignment opening having a first surface configured to align the component in a first stage, said second layer comprising a second alignment opening having a second surface configured to align the component in a second stage.
31. The apparatus as claimed in wherein the first layer comprises a first type of resist and the second layer comprises a second type of resist.
claim 30
32. A method for fabricating a test system for semiconductor components comprising:
providing a component having external contacts and an alignment member formed thereon;
providing an interconnect comprising a plurality of contact members configured to make temporary electrical connections with the external contacts; and
forming an alignment fixture on the interconnect, said alignment fixture comprising a polymer layer having a surface configured to engage the alignment member to align the external contacts to the contact members.
33. The method as claimed in wherein the polymer layer comprises a layer of resist and the forming step comprises depositing and developing the resist with an opening comprising the surface.
claim 32
34. The method as claimed in wherein the polymer layer comprises a first layer of resist and a second layer of resist, said first and second layers comprising first and second openings comprising the surface.
claim 32
35. The method as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 32
36. A method for fabricating a test system for semiconductor components comprising:
providing a component having external contacts and an alignment member;
providing an interconnect comprising a plurality of contact members configured to make temporary electrical connection with the external contacts;
forming a resist layer on the interconnect;
forming a surface on the resist layer, said surface configured to contact the alignment member to align the component with the interconnect; and
curing the resist layer.
37. The method as claimed in wherein the resist layer comprises a first type of resist and a second type of resist.
claim 36
38. The method as claimed in wherein the surface comprises an opening in the layer of resist.
claim 36
39. The method as claimed in wherein the alignment member comprises an element selected from the group consisting of beveled edges, bumps, and posts.
claim 36
40. The method as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 36
41. A method for fabricating a test system for semiconductor components comprising:
providing a component having external contacts;
providing an interconnect comprising a plurality of contact members configured to make temporary electrical connection with the external contacts;
depositing a first resist layer on the interconnect;
depositing a second resist layer on the first resist layer;
developing the first resist layer to form a first guide surface for aligning the component to the interconnect in a first stage; and
developing the second resist layer to form a second guide surface for aligning the component to the interconnect in a second stage.
42. The method as claimed in further comprising providing the component with an alignment member configured to contact the first and second guide surface.
claim 41
43. The method as claimed in wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
claim 41
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/745,093 US6353328B2 (en) | 1997-12-11 | 2000-12-20 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/988,433 US6018249A (en) | 1997-12-11 | 1997-12-11 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
US09/365,461 US6229324B1 (en) | 1997-12-11 | 1999-08-02 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
US09/745,093 US6353328B2 (en) | 1997-12-11 | 2000-12-20 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/365,461 Division US6229324B1 (en) | 1997-12-11 | 1999-08-02 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010000646A1 true US20010000646A1 (en) | 2001-05-03 |
US6353328B2 US6353328B2 (en) | 2002-03-05 |
Family
ID=25534115
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/988,433 Expired - Lifetime US6018249A (en) | 1997-12-11 | 1997-12-11 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
US09/365,461 Expired - Lifetime US6229324B1 (en) | 1997-12-11 | 1999-08-02 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
US09/745,093 Expired - Fee Related US6353328B2 (en) | 1997-12-11 | 2000-12-20 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/988,433 Expired - Lifetime US6018249A (en) | 1997-12-11 | 1997-12-11 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
US09/365,461 Expired - Lifetime US6229324B1 (en) | 1997-12-11 | 1999-08-02 | Test system with mechanical alignment for semiconductor chip scale packages and dice |
Country Status (6)
Country | Link |
---|---|
US (3) | US6018249A (en) |
JP (1) | JP2001526395A (en) |
KR (2) | KR100396723B1 (en) |
AU (1) | AU1711299A (en) |
DE (1) | DE19882885T1 (en) |
WO (1) | WO1999030174A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040112142A1 (en) * | 2002-12-05 | 2004-06-17 | Min Byoung-Jun | Test kit for semiconductor package and method for testing semiconductor package using the same |
US20120032321A1 (en) * | 2010-08-04 | 2012-02-09 | International Business Machines Corporation | Electrical Contact Alignment Posts |
Families Citing this family (104)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6741085B1 (en) * | 1993-11-16 | 2004-05-25 | Formfactor, Inc. | Contact carriers (tiles) for populating larger substrates with spring contacts |
US20020004320A1 (en) * | 1995-05-26 | 2002-01-10 | David V. Pedersen | Attaratus for socketably receiving interconnection elements of an electronic component |
US6310484B1 (en) * | 1996-04-01 | 2001-10-30 | Micron Technology, Inc. | Semiconductor test interconnect with variable flexure contacts |
US6690185B1 (en) * | 1997-01-15 | 2004-02-10 | Formfactor, Inc. | Large contactor with multiple, aligned contactor units |
US6040702A (en) | 1997-07-03 | 2000-03-21 | Micron Technology, Inc. | Carrier and system for testing bumped semiconductor components |
US6329829B1 (en) | 1997-08-22 | 2001-12-11 | Micron Technology, Inc. | Interconnect and system for making temporary electrical connections to semiconductor components |
US6072326A (en) | 1997-08-22 | 2000-06-06 | Micron Technology, Inc. | System for testing semiconductor components |
US6048744A (en) | 1997-09-15 | 2000-04-11 | Micron Technology, Inc. | Integrated circuit package alignment feature |
US6018249A (en) | 1997-12-11 | 2000-01-25 | Micron Technolgoy, Inc. | Test system with mechanical alignment for semiconductor chip scale packages and dice |
US6130148A (en) * | 1997-12-12 | 2000-10-10 | Farnworth; Warren M. | Interconnect for semiconductor components and method of fabrication |
US6833613B1 (en) * | 1997-12-18 | 2004-12-21 | Micron Technology, Inc. | Stacked semiconductor package having laser machined contacts |
US6620731B1 (en) | 1997-12-18 | 2003-09-16 | Micron Technology, Inc. | Method for fabricating semiconductor components and interconnects with contacts on opposing sides |
US6140827A (en) * | 1997-12-18 | 2000-10-31 | Micron Technology, Inc. | Method and apparatus for testing bumped die |
US6429528B1 (en) * | 1998-02-27 | 2002-08-06 | Micron Technology, Inc. | Multichip semiconductor package |
JP3497722B2 (en) * | 1998-02-27 | 2004-02-16 | 富士通株式会社 | Semiconductor device, method of manufacturing the same, and transfer tray thereof |
US6103613A (en) * | 1998-03-02 | 2000-08-15 | Micron Technology, Inc. | Method for fabricating semiconductor components with high aspect ratio features |
US6112795A (en) * | 1998-03-12 | 2000-09-05 | International Business Machines Corporation | Fixture for multi-layered ceramic package assembly |
US6177727B1 (en) * | 1998-05-01 | 2001-01-23 | Motorola, Inc. | Saddle bracket for solid state pressure gauge |
US6677776B2 (en) | 1998-05-11 | 2004-01-13 | Micron Technology, Inc. | Method and system having switching network for testing semiconductor components on a substrate |
US6337577B1 (en) | 1998-05-11 | 2002-01-08 | Micron Technology, Inc. | Interconnect and system for testing bumped semiconductor components with on-board multiplex circuitry for expanding tester resources |
US6292003B1 (en) * | 1998-07-01 | 2001-09-18 | Xilinx, Inc. | Apparatus and method for testing chip scale package integrated circuits |
US6369600B2 (en) * | 1998-07-06 | 2002-04-09 | Micron Technology, Inc. | Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure |
US6353326B2 (en) | 1998-08-28 | 2002-03-05 | Micron Technology, Inc. | Test carrier with molded interconnect for testing semiconductor components |
US6100175A (en) | 1998-08-28 | 2000-08-08 | Micron Technology, Inc. | Method and apparatus for aligning and attaching balls to a substrate |
US6208156B1 (en) * | 1998-09-03 | 2001-03-27 | Micron Technology, Inc. | Test carrier for packaging semiconductor components having contact balls and calibration carrier for calibrating semiconductor test systems |
US6887723B1 (en) * | 1998-12-04 | 2005-05-03 | Formfactor, Inc. | Method for processing an integrated circuit including placing dice into a carrier and testing |
US6337575B1 (en) * | 1998-12-23 | 2002-01-08 | Micron Technology, Inc. | Methods of testing integrated circuitry, methods of forming tester substrates, and circuitry testing substrates |
US6307394B1 (en) | 1999-01-13 | 2001-10-23 | Micron Technology, Inc. | Test carrier with variable force applying mechanism for testing semiconductor components |
US6369595B1 (en) | 1999-01-21 | 2002-04-09 | Micron Technology, Inc. | CSP BGA test socket with insert and method |
US6175241B1 (en) | 1999-02-19 | 2001-01-16 | Micron Technology, Inc. | Test carrier with decoupling capacitors for testing semiconductor components |
US6285202B1 (en) | 1999-02-19 | 2001-09-04 | Micron Technology, Inc. | Test carrier with force applying mechanism guide and terminal contact protector |
US6819127B1 (en) * | 1999-02-19 | 2004-11-16 | Micron Technology, Inc. | Method for testing semiconductor components using interposer |
US6242932B1 (en) * | 1999-02-19 | 2001-06-05 | Micron Technology, Inc. | Interposer for semiconductor components having contact balls |
US6524346B1 (en) * | 1999-02-26 | 2003-02-25 | Micron Technology, Inc. | Stereolithographic method for applying materials to electronic component substrates and resulting structures |
US6222280B1 (en) | 1999-03-22 | 2001-04-24 | Micron Technology, Inc. | Test interconnect for semiconductor components having bumped and planar contacts |
US6396291B1 (en) | 1999-04-23 | 2002-05-28 | Micron Technology, Inc. | Method for testing semiconductor components |
US6204676B1 (en) * | 1999-05-10 | 2001-03-20 | Silicon Integrated Systems Corp. | Testing apparatus for testing a ball grid array device |
US7215131B1 (en) | 1999-06-07 | 2007-05-08 | Formfactor, Inc. | Segmented contactor |
US6285203B1 (en) | 1999-06-14 | 2001-09-04 | Micron Technology, Inc. | Test system having alignment member for aligning semiconductor components |
US6170329B1 (en) * | 1999-06-14 | 2001-01-09 | Agilent Technologies, Inc. | Test fixture customization adapter enclosure |
US6297653B1 (en) | 1999-06-28 | 2001-10-02 | Micron Technology, Inc. | Interconnect and carrier with resistivity measuring contacts for testing semiconductor components |
US7066708B1 (en) | 1999-10-19 | 2006-06-27 | Micron Technology, Inc. | Methods and apparatus for retaining a tray stack having a plurality of trays for carrying microelectric devices |
US7033920B1 (en) * | 2000-01-10 | 2006-04-25 | Micron Technology, Inc. | Method for fabricating a silicon carbide interconnect for semiconductor components |
US6975030B1 (en) | 2000-01-10 | 2005-12-13 | Micron Technology, Inc. | Silicon carbide contact for semiconductor components |
US6563215B1 (en) | 2000-01-10 | 2003-05-13 | Micron Technology, Inc. | Silicon carbide interconnect for semiconductor components and method of fabrication |
JP2001228192A (en) * | 2000-02-18 | 2001-08-24 | Oht Inc | Inspecting device and holder for it |
US6529027B1 (en) * | 2000-03-23 | 2003-03-04 | Micron Technology, Inc. | Interposer and methods for fabricating same |
US6522018B1 (en) | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
DE10024875B4 (en) | 2000-05-16 | 2004-07-01 | Infineon Technologies Ag | Component holder system for use with test devices for testing electronic components |
US7138653B1 (en) * | 2000-06-08 | 2006-11-21 | Micron Technology, Inc. | Structures for stabilizing semiconductor devices relative to test substrates and methods for fabricating the stabilizers |
US6365434B1 (en) | 2000-06-28 | 2002-04-02 | Micron Technology, Inc. | Method and apparatus for reduced flash encapsulation of microelectronic devices |
US6638831B1 (en) | 2000-08-31 | 2003-10-28 | Micron Technology, Inc. | Use of a reference fiducial on a semiconductor package to monitor and control a singulation method |
US6910812B2 (en) | 2001-05-15 | 2005-06-28 | Peregrine Semiconductor Corporation | Small-scale optoelectronic package |
US6564979B2 (en) | 2001-07-18 | 2003-05-20 | Micron Technology, Inc. | Method and apparatus for dispensing adhesive on microelectronic substrate supports |
DE10136152A1 (en) * | 2001-07-25 | 2002-10-02 | Infineon Technologies Ag | Semiconductor component with numerous discrete raised points on component main side |
US6548376B2 (en) | 2001-08-30 | 2003-04-15 | Micron Technology, Inc. | Methods of thinning microelectronic workpieces |
US6991960B2 (en) * | 2001-08-30 | 2006-01-31 | Micron Technology, Inc. | Method of semiconductor device package alignment and method of testing |
US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
US6870276B1 (en) * | 2001-12-26 | 2005-03-22 | Micron Technology, Inc. | Apparatus for supporting microelectronic substrates |
US7212599B2 (en) * | 2002-01-25 | 2007-05-01 | Applied Micro Circuits Corporation | Jitter and wander reduction apparatus |
TW531821B (en) * | 2002-02-08 | 2003-05-11 | Ultratera Corp | Fixture for use in test of semiconductor package and process with use of the same |
US6622380B1 (en) | 2002-02-12 | 2003-09-23 | Micron Technology, Inc. | Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards |
US6903001B2 (en) * | 2002-07-18 | 2005-06-07 | Micron Technology Inc. | Techniques to create low K ILD for BEOL |
US6913476B2 (en) * | 2002-08-06 | 2005-07-05 | Micron Technology, Inc. | Temporary, conformable contacts for microelectronic components |
US6845901B2 (en) * | 2002-08-22 | 2005-01-25 | Micron Technology, Inc. | Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece |
US6924653B2 (en) * | 2002-08-26 | 2005-08-02 | Micron Technology, Inc. | Selectively configurable microelectronic probes |
US7705349B2 (en) * | 2002-08-29 | 2010-04-27 | Micron Technology, Inc. | Test inserts and interconnects with electrostatic discharge structures |
US6773938B2 (en) * | 2002-08-29 | 2004-08-10 | Micron Technology, Inc. | Probe card, e.g., for testing microelectronic components, and methods for making same |
DE10260765A1 (en) * | 2002-12-23 | 2004-02-26 | Infineon Technologies Ag | Integrated circuit with a wafer level package and test card for contacting the package has contact elements of differing heights |
US6879050B2 (en) * | 2003-02-11 | 2005-04-12 | Micron Technology, Inc. | Packaged microelectronic devices and methods for packaging microelectronic devices |
SG143931A1 (en) * | 2003-03-04 | 2008-07-29 | Micron Technology Inc | Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths |
SG137651A1 (en) * | 2003-03-14 | 2007-12-28 | Micron Technology Inc | Microelectronic devices and methods for packaging microelectronic devices |
US20050012212A1 (en) * | 2003-07-17 | 2005-01-20 | Cookson Electronics, Inc. | Reconnectable chip interface and chip package |
US6924655B2 (en) * | 2003-09-03 | 2005-08-02 | Micron Technology, Inc. | Probe card for use with microelectronic components, and methods for making same |
US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US20050104171A1 (en) * | 2003-11-13 | 2005-05-19 | Benson Peter A. | Microelectronic devices having conductive complementary structures and methods of manufacturing microelectronic devices having conductive complementary structures |
US7091124B2 (en) * | 2003-11-13 | 2006-08-15 | Micron Technology, Inc. | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices |
US7043388B2 (en) * | 2003-12-22 | 2006-05-09 | Micron Technology, Inc. | System and apparatus for testing packaged devices and related methods |
JP2005241275A (en) * | 2004-02-24 | 2005-09-08 | Japan Electronic Materials Corp | Probe card |
US7256595B2 (en) * | 2004-03-22 | 2007-08-14 | Micron Technology, Inc. | Test sockets, test systems, and methods for testing microfeature devices |
KR100585142B1 (en) * | 2004-05-04 | 2006-05-30 | 삼성전자주식회사 | Structure of flip chip semiconductor package for testing a bump and method of fabricating the same |
US7253089B2 (en) * | 2004-06-14 | 2007-08-07 | Micron Technology, Inc. | Microfeature devices and methods for manufacturing microfeature devices |
SG145547A1 (en) * | 2004-07-23 | 2008-09-29 | Micron Technology Inc | Microelectronic component assemblies with recessed wire bonds and methods of making same |
US7632747B2 (en) * | 2004-08-19 | 2009-12-15 | Micron Technology, Inc. | Conductive structures for microfeature devices and methods for fabricating microfeature devices |
US20060043534A1 (en) * | 2004-08-26 | 2006-03-02 | Kirby Kyle K | Microfeature dies with porous regions, and associated methods and systems |
US7095122B2 (en) * | 2004-09-01 | 2006-08-22 | Micron Technology, Inc. | Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same |
US7204699B2 (en) * | 2004-12-27 | 2007-04-17 | Fci Americas Technology, Inc. | Electrical connector with provisions to reduce thermally-induced stresses |
US7218128B2 (en) * | 2005-02-14 | 2007-05-15 | International Business Machines Corporation | Method and apparatus for locating and testing a chip |
US20070020964A1 (en) * | 2005-07-22 | 2007-01-25 | Domintech Co., Ltd. | Memory module with chip hold-down fixture |
SG130061A1 (en) | 2005-08-24 | 2007-03-20 | Micron Technology Inc | Microelectronic devices and microelectronic support devices, and associated assemblies and methods |
US7807505B2 (en) * | 2005-08-30 | 2010-10-05 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US7622377B2 (en) * | 2005-09-01 | 2009-11-24 | Micron Technology, Inc. | Microfeature workpiece substrates having through-substrate vias, and associated methods of formation |
US20070126445A1 (en) * | 2005-11-30 | 2007-06-07 | Micron Technology, Inc. | Integrated circuit package testing devices and methods of making and using same |
US20070148820A1 (en) * | 2005-12-22 | 2007-06-28 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
SG133445A1 (en) | 2005-12-29 | 2007-07-30 | Micron Technology Inc | Methods for packaging microelectronic devices and microelectronic devices formed using such methods |
US7910385B2 (en) * | 2006-05-12 | 2011-03-22 | Micron Technology, Inc. | Method of fabricating microelectronic devices |
SG138501A1 (en) * | 2006-07-05 | 2008-01-28 | Micron Technology Inc | Lead frames, microelectronic devices with lead frames, and methods for manufacturing lead frames and microelectronic devices with lead frames |
SG139573A1 (en) * | 2006-07-17 | 2008-02-29 | Micron Technology Inc | Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods |
SG149726A1 (en) | 2007-07-24 | 2009-02-27 | Micron Technology Inc | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
SG150396A1 (en) * | 2007-08-16 | 2009-03-30 | Micron Technology Inc | Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods |
KR101388790B1 (en) * | 2007-08-30 | 2014-04-24 | 삼성전자주식회사 | Chip array of optical device, chip on platform and apparatus for arranging of chip on platform using the same |
US7857646B2 (en) * | 2008-05-02 | 2010-12-28 | Micron Technology, Inc. | Electrical testing apparatus having masked sockets and associated systems and methods |
CN102216791B (en) * | 2008-11-26 | 2014-01-15 | 日本发条株式会社 | Base member for probe unit, and probe unit |
US9754983B1 (en) * | 2016-07-14 | 2017-09-05 | Semiconductor Components Industries, Llc | Chip scale package and related methods |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5634267A (en) * | 1991-06-04 | 1997-06-03 | Micron Technology, Inc. | Method and apparatus for manufacturing known good semiconductor die |
US5006792A (en) * | 1989-03-30 | 1991-04-09 | Texas Instruments Incorporated | Flip-chip test socket adaptor and method |
AU637874B2 (en) * | 1990-01-23 | 1993-06-10 | Sumitomo Electric Industries, Ltd. | Substrate for packaging a semiconductor device |
US5046239A (en) * | 1990-07-10 | 1991-09-10 | The United States Of America As Represented By The Secretary Of The Army | Method of making a flexible membrane circuit tester |
US5088190A (en) * | 1990-08-30 | 1992-02-18 | Texas Instruments Incorporated | Method of forming an apparatus for burn in testing of integrated circuit chip |
US5172050A (en) * | 1991-02-15 | 1992-12-15 | Motorola, Inc. | Micromachined semiconductor probe card |
US5559444A (en) * | 1991-06-04 | 1996-09-24 | Micron Technology, Inc. | Method and apparatus for testing unpackaged semiconductor dice |
US5519332A (en) * | 1991-06-04 | 1996-05-21 | Micron Technology, Inc. | Carrier for testing an unpackaged semiconductor die |
US5541525A (en) * | 1991-06-04 | 1996-07-30 | Micron Technology, Inc. | Carrier for testing an unpackaged semiconductor die |
US5495179A (en) * | 1991-06-04 | 1996-02-27 | Micron Technology, Inc. | Carrier having interchangeable substrate used for testing of semiconductor dies |
US5578934A (en) * | 1991-06-04 | 1996-11-26 | Micron Technology, Inc. | Method and apparatus for testing unpackaged semiconductor dice |
US5691649A (en) * | 1991-06-04 | 1997-11-25 | Micron Technology, Inc. | Carrier having slide connectors for testing unpackaged semiconductor dice |
WO1993019487A1 (en) * | 1992-03-24 | 1993-09-30 | Unisys Corporation | Integrated circuit module having microscopic self-alignment features |
US5483174A (en) * | 1992-06-10 | 1996-01-09 | Micron Technology, Inc. | Temporary connection of semiconductor die using optical alignment techniques |
US5329423A (en) * | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
US5633122A (en) * | 1993-08-16 | 1997-05-27 | Micron Technology, Inc. | Test fixture and method for producing a test fixture for testing unpackaged semiconductor die |
US5572140A (en) * | 1993-08-25 | 1996-11-05 | Sunright Limited | Reusable carrier for burn-in/testing on non packaged die |
US5543725A (en) * | 1993-08-25 | 1996-08-06 | Sunright Limited | Reusable carrier for burn-in/testing on non packaged die |
US5530376A (en) * | 1993-08-25 | 1996-06-25 | Sunright Limited | Reusable carrier for burn-in/testing of non packaged die |
US5592736A (en) * | 1993-09-03 | 1997-01-14 | Micron Technology, Inc. | Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads |
US5500605A (en) * | 1993-09-17 | 1996-03-19 | At&T Corp. | Electrical test apparatus and method |
JP2710544B2 (en) * | 1993-09-30 | 1998-02-10 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Probe structure, method of forming probe structure |
KR950033507A (en) * | 1994-02-08 | 1995-12-26 | 오가 노리오 | IC measurement test apparatus and IC measurement test method using the same |
US5703493A (en) * | 1995-10-25 | 1997-12-30 | Motorola, Inc. | Wafer holder for semiconductor applications |
JPH09274066A (en) * | 1996-02-07 | 1997-10-21 | Fujitsu Ltd | Semiconductor tester, testing method utilizing tester thereof and semiconductor device |
US5756370A (en) * | 1996-02-08 | 1998-05-26 | Micron Technology, Inc. | Compliant contact system with alignment structure for testing unpackaged semiconductor dice |
US5801452A (en) | 1996-10-25 | 1998-09-01 | Micron Technology, Inc. | Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member |
US5834945A (en) * | 1996-12-31 | 1998-11-10 | Micron Technology, Inc. | High speed temporary package and interconnect for testing semiconductor dice and method of fabrication |
US6016060A (en) | 1997-03-25 | 2000-01-18 | Micron Technology, Inc. | Method, apparatus and system for testing bumped semiconductor components |
US5962921A (en) | 1997-03-31 | 1999-10-05 | Micron Technology, Inc. | Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps |
US5931685A (en) | 1997-06-02 | 1999-08-03 | Micron Technology, Inc. | Interconnect for making temporary electrical connections with bumped semiconductor components |
US6040702A (en) | 1997-07-03 | 2000-03-21 | Micron Technology, Inc. | Carrier and system for testing bumped semiconductor components |
US6072326A (en) | 1997-08-22 | 2000-06-06 | Micron Technology, Inc. | System for testing semiconductor components |
US6018249A (en) * | 1997-12-11 | 2000-01-25 | Micron Technolgoy, Inc. | Test system with mechanical alignment for semiconductor chip scale packages and dice |
-
1997
- 1997-12-11 US US08/988,433 patent/US6018249A/en not_active Expired - Lifetime
-
1998
- 1998-12-04 KR KR10-2000-7006323A patent/KR100396723B1/en not_active IP Right Cessation
- 1998-12-04 JP JP2000524680A patent/JP2001526395A/en active Pending
- 1998-12-04 AU AU17112/99A patent/AU1711299A/en not_active Abandoned
- 1998-12-04 KR KR10-2002-7015599A patent/KR100423250B1/en not_active IP Right Cessation
- 1998-12-04 WO PCT/US1998/025804 patent/WO1999030174A1/en not_active Application Discontinuation
- 1998-12-04 DE DE19882885T patent/DE19882885T1/en not_active Ceased
-
1999
- 1999-08-02 US US09/365,461 patent/US6229324B1/en not_active Expired - Lifetime
-
2000
- 2000-12-20 US US09/745,093 patent/US6353328B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040112142A1 (en) * | 2002-12-05 | 2004-06-17 | Min Byoung-Jun | Test kit for semiconductor package and method for testing semiconductor package using the same |
US7017428B2 (en) * | 2002-12-05 | 2006-03-28 | Samsung Electronics Co., Ltd. | Test kit for semiconductor package and method for testing semiconductor package using the same |
US20120032321A1 (en) * | 2010-08-04 | 2012-02-09 | International Business Machines Corporation | Electrical Contact Alignment Posts |
US8415792B2 (en) * | 2010-08-04 | 2013-04-09 | International Business Machines Corporation | Electrical contact alignment posts |
US8530345B2 (en) | 2010-08-04 | 2013-09-10 | International Business Machines Corporation | Electrical contact alignment posts |
Also Published As
Publication number | Publication date |
---|---|
US6229324B1 (en) | 2001-05-08 |
KR100396723B1 (en) | 2003-09-02 |
US6018249A (en) | 2000-01-25 |
WO1999030174A1 (en) | 1999-06-17 |
KR20010032974A (en) | 2001-04-25 |
KR20030014232A (en) | 2003-02-15 |
DE19882885T1 (en) | 2000-11-30 |
US6353328B2 (en) | 2002-03-05 |
JP2001526395A (en) | 2001-12-18 |
AU1711299A (en) | 1999-06-28 |
KR100423250B1 (en) | 2004-03-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6229324B1 (en) | Test system with mechanical alignment for semiconductor chip scale packages and dice | |
US6417685B1 (en) | Test system having alignment member for aligning semiconductor components | |
US6222280B1 (en) | Test interconnect for semiconductor components having bumped and planar contacts | |
US6208157B1 (en) | Method for testing semiconductor components | |
US6313651B1 (en) | Carrier and system for testing bumped semiconductor components | |
US6995577B2 (en) | Contact for semiconductor components | |
US6333555B1 (en) | Interconnect for semiconductor components and method of fabrication | |
US6400172B1 (en) | Semiconductor components having lasered machined conductive vias | |
US6242932B1 (en) | Interposer for semiconductor components having contact balls | |
US6091252A (en) | Method, apparatus and system for testing bumped semiconductor components | |
US5801452A (en) | Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member | |
US6329829B1 (en) | Interconnect and system for making temporary electrical connections to semiconductor components | |
US6314641B1 (en) | Interconnect for testing semiconductor components and method of fabrication | |
KR101387719B1 (en) | Microelectronic assemblies having compliancy and methods therefor | |
US6620633B2 (en) | Method for testing bumped semiconductor components | |
US6396291B1 (en) | Method for testing semiconductor components | |
US6369600B2 (en) | Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure | |
US6819127B1 (en) | Method for testing semiconductor components using interposer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140305 |