US20010001724A1 - Edge stress reduction by noncoincident layers - Google Patents
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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Abstract
The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).
Description
- The present invention relates to edge stress reduction in integrated circuit structures and fabrication methods.
- Background: Stress-Induced Defects
- Nearly all films are found to be in a state of internal stress, regardless of the means by which they have been produced. The stress may be compressive or tensile. Compressively stressed films are characterized by the fact that they would like to expand parallel to the substrate surface, and in the extreme, a compressively stressed film will buckle up on the substrate (the stress in the substrate is opposite in sign). Films in tensile stress, on the other hand, would like to contract parallel to the substrate, and may crack if their elastic limits are exceeded. Films in tensile stress tend to cause concave bending of the substrate (bending toward the film), while films in compressive stress tend to cause convex bending (bending away from the film).
- For example, during the formation of suicides, there is a net volume shrinkage which could possibly result in a large tensile stress in the film. This stress can result in delamination and other problems during subsequent processing.
- Highly stressed films are undesirable as they are more likely to exhibit poor adhesion, they are more susceptible to corrosion, they may undergo cracking in tensile stress (especially for brittle films, such as inorganic dielectrics), and they tend to exhibit higher resistivities. In addition, the stress increases with increasing thickness.
- One conventional approach of reducing the stress in metal films (e.g. tungsten), which is discussed in U.S. Pat. No. 5,480,529 to Kola et al., includes employing a continuously operating capacitance-based measurement technique to allow adjustment of the deposition conditions in rapid response to changes in the stress of the film being deposited. However, this approach requires frequent and rapid measurements and constant adjustment of process parameters, both of which are cumbersome and increase the cost of the devices. Not all processes can be optimized in this way and not all films can be made stress-free (especially refractory metals and silicides).
- A stressed film will tend to cause a corresponding stress in the layer(s) to which it is bonded. For example, a transistor gate layer which is in strong compressive stress will tend to induce a tensile stress in a substrate to which it is bonded.
- Particularly large stresses and gradients occur at the edges of layered device structures such as gate edges, nitride moat (e.g. active device area) mask edges, and LOCOS edges. The stress level often reaches hundreds of Mega-Pascals at tens of nanometers within the vicinity of the edge. This stress level can cause structural reliability problems, such as peeling, or induce crystal defects in silicon during device processing. Furthermore, stress-induced defects can undesirably increase the leakage current in transistors.
- Background: DRAM Gate Structures
- One of the driving forces in shrinking integrated circuit geometries is the distributed resistance and parasitic capacitance of the signal lines, which reduce the propagation speed of signals. The additional delays thus introduced reduce the potential speed of the chip.
- This is a particular problem for DRAMs, since the wordlines are densely packed together, and the capacitive coupling between adjacent lines becomes very significant. Moreover, the sheet resistance of the lines cannot usefully be improved by increasing the height of the lines, since this also increases the capacitive coupling between adjacent lines. There has therefore been great pressure to find materials with a lower resistivity to replace the traditional polysilicon/silicide lines. This has impelled efforts to design metal into the gate line structure. One example of this is a gate stack structure which includes tungsten (or other refractory metal) over polysilicon with a diffusion barrier layer therebetween (e.g. 5 nm of TiN), but many other gate stack structures have been proposed.
- Stress in the refractory metal and barrier layers is typically tensile and very high (e.g. between 1000 and 3000 MPa), while the stress in the polysilicon and gate oxide is compressive and much lower (e.g. 100 to 300 MPa). (Thus, the tensile stress of the metal layer dominates over the compressive stress of the polysilicon layer.) The stress distribution in the silicon substrate near the gate structure is tensile at external edges, and rapidly changes to compressive toward the center of the gate. This polar reversal of layer stresses occurs within tens of nanometers. The interaction of stress and point defects in the silicon substrate (due to ion implantation or grown in micro-defects) during annealing can undesirably cause crystal dislocations.
- Background: Inverse-T-Gates
- Inverse-T-gate structures are usually formed by forming sidewall spacers on an upper polysilicon layer portion prior to etching the lower polysilicon layer portion (and possibly an intervening barrier layer). Thus in a single patterning step this produces a conductor line in which the upper portion is narrower than the lower portion. (However, inverse-T-gate structures do not normally contain a thick, highly-stressed metal layer, and are usually designed to control profiling of the implanted diffusions.) Inverse-T-gate structures are discussed in, for example, the following articles: Wen et al., “A Self-Aligned Inverse-T Gate Fully Overlapped LDD Device for Sub-Half Micron CMOS,” 1989 IEDM paper 32.1; Goranova et al., “A Pragmatic View of Inverse-T-Gate Lightly-Doped-Drain Transistors,” 34 SOLID-STATE ELECTRONICS 1169 (1991); and Chen et al., “Self-Aligned Silicided Inverse-T Gate LDD Devices for Sub-Half Micron CMOS Technology,” 1990 IEDM, 829; all of which are hereby incorporated by reference.
- Edge Stress Reduction Structures and Methods
- The present application discloses structures and methods which enable the reduction of the edge stress to avoid device reliability and performance problems. In cases where the choice of materials is limited, reduction of edge stress can be achieved by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).
- Advantages of the disclosed methods and structures include: optimization of the stress at the edge to reduce or eliminate device
- reliability and/or performance problems; and can be implemented in any integrated circuit device to reduce stress at the edges.
- The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:
- FIG. 1 shows a process flow for fabricating a DRAM gate structure using embodiments of the present invention;
- FIGS.2A-2E schematically illustrate the formation of DRAM gate structures in accordance with embodiments of the present invention; and
- FIG. 3 is a chart showing the change in stress in various structures.
- The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
- Overview of Methods and Structures
- As shown in FIGS.2A-2D, a typical stack structure typically consists of the following layers: dielectric 240,
metal 230,diffusion barrier 220, conductive layer (e.g., polysilicon) 210, and gate dielectric 200. - To reduce stress at the edge, and thus of the total structure, a noncoincident structure is fabricated in accordance with the process flow of FIG. 1. First, the gate stack layers are blanket deposited (step100):
conductive layer 210,barrier layer 220,metal 230, and adielectric layer 240, as shown in FIG. 2A. Thereafter, the stack is formed by patterning, using a photoresist, and etching (step 110) thestack layers - In order to reduce the edge stress, the
metal layer 230 is then made noncoincident, by performing a lateral etch (step 120) of themetal 230, which results in the structure shown in FIG. 2C. - Subsequently, a
dielectric layer 250 is deposited (step 130) overall to fill the space on either side of themetal layer 230, and then etched (step 140) to form the structure shown in FIG. 2D. - First Noncoincident Layered Embodiment: Gate Structure
- In this presently preferred embodiment, a complicated DRAM transistor gate stacks is shown, consisting of the following layers:
silicon nitride 240,tungsten 230,titanium nitride 220,polysilicon 210, andgate oxide 200. This gate stack has potential application in 256 Megabit and higher DRAM products which require low resistance wordlines. The thickness of the materials for a typical 256 Megabit gate stack are: silicon nitride 150 nm, tungsten 60 nm, titanium nitride 20 nm, polysilicon 50 nm, and gate silicon dioxide 5 nm. - After blanket deposition of each of the above layers, the gate stack is patterned and etched. The
nitride layer 240 is typically etched using a CHF3 and CF4 chemistry, while the tungsten layer can be etched selective to TiN using a SF6 chemistry. The TiN is then anisotropically etched using a BC13 and C12 chemistry, followed by the etching of the polysilicon layer with HBr and C12. -
Tungsten layer 230 is then made noncoincident, by performing a subsequent lateral etch using, for example, SF6. The amount of lateral etch of thetungsten layer 230 is typically at least 0.8 of the height of thepolysilicon layer 210, while the width of thetungsten layer 230 is 0.4 to 0.8 (preferably 0.45 to 0.6) of the width of thepolysilicon layer 210. -
Silicon oxide layer 250 is deposited overall, filling the space on either side of thetungsten layer 230, and then etched to form the gate structure. Processing then continues with conventional steps to complete fabrication, e.g. smiling oxidation, deposition and planarization of further interlevel dielectric, via patterning, second metal deposition and etch, protective overcoat deposition, etching contact pad apertures, etc. - The nitride/tungsten/barrier layer stresses are highly tensile (1000-3000 MPa) as compared with the compressively stressed polysilicon and gate oxide layers (100-300 MPa). Therefore, the stress of the tensile layers dominates the compressively stressed layers. By using a noncoincident metal layered structure, destructive interference between the high-stress tensile tungsten and titanium nitride layers can be achieved to reduce the stress or stress gradient at the edge.
- A first-order estimate of the stress distribution for three different structures containing layers of tungsten and TiN using measurements taken in the substrate from 40 nm outside the gate stack to 40 nm underneath the gate stack is illustrated in the chart in FIG. 3. Both the tungsten and the TiN have a similar tensile stress magnitude of 1000 MPa. The first structure (series 1) had a layer of tungsten overlying a layer of TiN, in which both layers were of equal width. The thickness of both the tungsten and the TiN layers was 0.1 microns each. The second structure (series 2) had a noncoincident structure similar to the structure described herein, in which the tungsten layer had a width smaller than the TiN layer. The third structure (series 3) had both tungsten and TiN of the same width, but the total thickness was reduced to 0.147 microns, so that the cross-sectional area was equal to the second structure. As can be seen from FIG. 3, the change in stress per unit length at the edge of the gate structure is predicted to decrease for the noncoincident structure (series 2).
- The following table shows the absolute value of the change in stress (Delta Stress) in Pascals between measurements taken in the substrate 40 nm outside the gate stack and 40 nm underneath the gate stack for the three different structures.
Stress 40 nm outside 40 nm underneath Distribution film film Delta Stress Series 1 1.53E9 −2.32E9 3.85E9 Series 2 1.00E9 −0.54E9 1.54E9 Series 3 1.12E9 −1.70E9 2.82E9 - Series 2 has the minimum delta stress at +−40 nm from the film edge. Therefore, by using noncoincident structures, the gate stack stress at the edge can be significantly reduced.
- Alternative Noncoincident Structure Formation Embodiment:
- Overetch Tungsten
- Alternatively, the
noncoincident tungsten layer 230 can be formed by overetching the tungsten layer 230 (using SF6, which is selective to TiN) during the gate stack formation. Advantageously, a subsequent etch of thetungsten layer 230 does not need to be performed. - Alternative Dielectric Layer Embodiment: Silicon Dioxide
- Alternatively, a layer of silicon dioxide can be deposited over the tungsten layer prior to the gate stack etch and the formation of the noncoincident tungsten.
- Alternative Dielectric Layer Embodiment: Silicon Oxynitride
- Alternatively, a layer of silicon oxynitride can be deposited over the tungsten layer prior to the gate stack etch and the formation of the noncoincident tungsten.
- Alternative Barrier Layer Embodiment: TiAIN
- Alternatively, a layer of TiAIN can be deposited over the polysilicon layer prior to the deposition of the metal layer to serve as a barrier layer.
- Alternative Barrier Layer Embodiment: TiSiN
- Alternatively, a layer of TiSiN can be deposited over the polysilicon layer prior to the deposition of the metal layer to serve as a barrier layer.
- Alternative Barrier Layer Embodiment: Tungsten Nitride
- Alternatively, a layer of tungsten nitride can be deposited over the polysilicon layer prior to the deposition of the metal layer to serve as a barrier layer.
- Alternative Barrier Layer Embodiment: Titanium Boride
- Alternatively, a layer of titanium boride can be deposited over the polysilicon layer prior to the deposition of the metal layer to serve as a barrier layer. Advantageously, titanium boride has a resistivity close to the resistivity of tungsten, and therefore the titanium boride layer can be made nearly as thick as the tungsten layer in order to increase the destructive interference between the tungsten and titanium boride layers, and thus reduce the edge stress. Further information on titanium boride can be found in: Murarka, SILICIDES FOR VLSI APPLICATIONS, p.35 (1983), which is hereby incorporated by reference.
- Alternative Barrier Layer Embodiment: Hafnium Boride
- Alternatively, a layer of hafnium boride can be deposited over the polysilicon layer prior to the deposition of the metal layer to serve as a barrier layer. Advantageously, hafnium boride has a resistivity close to the resistivity of tungsten, and therefore the boride layer can be made nearly as thick as the tungsten layer in order to increase the destructive interference between the tungsten and boride layers, and thus reduce the edge stress.
- Alternative Barrier Layer Embodiment: Zirconium Boride
- Alternatively, a layer of zirconium boride can be deposited over the polysilicon layer prior to the deposition of the metal layer to serve as a barrier layer. Advantageously, zirconium boride has a resistivity close to the resistivity of tungsten, and therefore the boride layer can be made nearly as thick as the tungsten layer in order to increase the destructive interference between the tungsten and boride layers, and thus reduce the edge stress.
- Alternative Metal Layer Embodiment: Molybdenum
- The present invention is not limited to tungsten, but can be applied to other refractory metals. In an alternative contemplated class of embodiments, the metal layer can be molybdenum or a molybdenum alloy, and the process described above can be used to reduce the stress at the gate edges.
- Alternative Metal Layer Embodiment: Platinum
- In another alternative contemplated class of embodiments, the metal layer can be platinum or an alloy thereof, and the process described above can be used to reduce the stress at the gate edges.
- Alternative Metal Layer Embodiment: Tantalum
- In another alternative contemplated class of embodiments, the metal layer can be tantalum or an alloy thereof, and the process described above can be used to reduce the stress at the gate edges.
- Alternative Metal Layer Embodiment: Niobium
- In another alternative contemplated class of embodiments, the metal layer can be niobium or an alloy thereof, and the process described above can be used to reduce the stress at the gate edges.
- Alternative Gate Stack Embodiment: Metal Silicide
- In an alternative embodiment, a metal silicide layer (e.g. titanium silicide), which has a thickness of around 80 nm, can be deposited over the polysilicon layer instead of the metal layer. Titanium silicide (TiSi2) is typically used because it has a significantly lower sheet resistance than other commonly used metal silicides, such as tungsten silicide. Titanium silicide films typically have large tensile stress, and therefore a noncoincident TiSi2 layer can be formed using embodiments of the present invention in order to reduce the edge stress.
- Alternative Metal Silicide Layer Embodiment: Molybdenum Silicide
- In alternative embodiments, the metal silicide layer can consist of molybdenum silicide. Otherwise, processing conditions are similar to those for titanium silicide.
- Alternative Metal Silicide Layer Embodiment: Cobalt Silicide
- In alternative embodiments, the metal silicide layer can consist of cobalt silicide. Otherwise, processing conditions are similar to those for titanium silicide.
- Second Noncoincident Layered Embodiment: Bitlines
- In DRAMs, the bitline metallization typically includes a barrier/adhesion layer (e.g. titanium) underlying a highly-stressed metal layer, such as tungsten, and an overlying dielectric (e.g. TEOS, or silicon nitride, which has tensile stress). The stress at the edge of bitline structures can be reduced by forming a noncoincident metal layer in accordance with embodiments of the present invention.
- Third Embodiment: Multiple Noncoincident Layers
- As shown in FIG. 2E, multiple noncoincident layers can be formed to further reduce edge stress, such as
metal layer 235, shown deposited overtungsten layer 230. Where both metal layers are the same (e.g., tungsten), an etch stop layer (not shown) is interposed betweenlayers layer 235 is etched, but beforelayer 230 is exposed, a lateral etch oflayer 235 is performed. This is followed by etching of the remaining stack layers and a second lateral etch to undercutlayer 230. Alternatively, wheremetal layer 235 is different fromlayer 230, a single etch step can be used, with an etchant having selective etch rates for the two metals. - According to another disclosed class of innovative embodiments, there is provided: An integrated circuit structure, comprising: a highly-stressed metal overlying a second conductive material, which has a thickness greater than half of the thickness of said metal; wherein the width of said metal is less than the width of said second conductive material; wherein destructive interference between said second conductive layer and said metal lowers the stress in underlying structures near edges of said structure.
- According to another disclosed class of innovative embodiments, there is provided: A method of fabricating an interconnect structure, comprising the steps of: (a.) patterning and etching an interconnect structure having at least a highly-stressed metal layer and a layer of a second conductive material; (b.) selectively laterally etching said metal layer to form edges of said metal layer which are not coincident with edges of said second conductive material; (c.) depositing a blanket dielectric layer; and (d.) etching said dielectric layer to leave said dielectric layer only in areas within said interconnect structure adjacent to said metal layer; wherein destructive interference between said second conductive layer and said metal lowers the stress in underlying structures near edges of said interconnect structure.
- Modifications and Variations
- As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given, but is only defined by the issued claims.
- While the inventions have been described with primary reference to a single-poly process, it will be readily recognized that these inventions can also be applied to process with two, three, or more layers of polysilicon or polycide. Furthermore, it should be noted that the inventions described herein can be applied to gate stacks having only a metal layer and no polysilicon layer, in which the edges of the top portion of the metal layer are noncoincident to the edges of the bottom portion of the metal layer.
- It should also be noted that the number of layers of metallization described above does not implicitly limit any of the claims, which can be applied to processes and structures with more or fewer layers.
- Of course a variety of structures can be used to implement the polysilicon or polycide gate. Similarly, a wide variety of materials, and of combinations of materials, can be used to implement the metal layer.
- Of course, the specific etch chemistries, layer compositions, and layer thicknesses given are merely illustrative, and do not by any means delimit the scope of the claimed inventions.
- The invention can also be adapted to other combinations of dielectric materials in the interlevel dielectric. For example, phosphosilicates, germanosilicate, borophosphosilicate, arsenosilicates or combinations thereof, in addition to low-k dielectrics and spin-on-glass can be used instead of the SiO2 of the presently preferred embodiment.
Claims (21)
1. An integrated circuit structure, comprising:
a strip of a first, metallic, conductive material, having a stress greater than 500 MPa, overlying a strip of a second conductive material having a stress less than 500 MPa;
wherein the width of said strip of first conductive material is less than the width of said strip of second conductive material;
whereby destructive interference between said first conductive layer and said second conductive layer lowers the stress in underlying structures near edges of said structure.
2. The integrated circuit of , wherein the stress in said first conductive material is of the opposite sign as the stress in said second conductive material.
claim 1
3. The integrated circuit of , wherein said first conductive material consists essentially of tungsten.
claim 1
4. The integrated circuit of , wherein said second conductive material has a thickness greater than half of the thickness of said first conductive material.
claim 1
5. The integrated circuit of , further comprising a barrier layer between said first conductive layer and said second conductive layer.
claim 1
6. The integrated circuit of , wherein said barrier layer consists of titanium nitride.
claim 5
7. The integrated circuit of , wherein said barrier layer consists of titanium boride.
claim 5
8. The integrated circuit of , further comprising a dielectric layer overlying said first conductive material.
claim 1
9. The integrated circuit of , further comprising a third conductive material comprising at least fifty percent atomic of silicon underlying said second conductive material; wherein the stress of said third conductive material is compressive.
claim 1
10. The integrated circuit of , wherein the stress of said first conductive material is tensile.
claim 1
11. A method of fabricating an integrated circuit structure, comprising the steps of:
(a.) patterning and etching a stack having at least a first layer of a metallic, conductive material having a stress greater than 500 MPa and a layer of a second conductive material having a stress less than 500 MPa;
(b.) selectively laterally etching said first conductive layer to form edges of said first conductive layer which are not coincident with edges of said second conductive material;
(c.) depositing a blanket dielectric layer; and
(d.) etching said dielectric layer to leave said dielectric layer only in areas within said integrated circuit structure adjacent to said first conductive layer;
whereby destructive interference between said first conductive layer and said second conductive layer lowers the stress in underlying structures near edges of said integrated circuit structure.
12. The integrated circuit of , wherein the stress in said first conductive material is of the opposite sign as the stress in said second conductive material.
claim 11
13. The method of , wherein said first conductive material consists essentially of tungsten.
claim 11
14. The method of , wherein said stack has a barrier layer between said first conductive layer and said second conductive layer.
claim 11
15. The method of , wherein said barrier layer consists of titanium nitride.
claim 14
16. The method of , wherein said barrier layer consists of titanium boride.
claim 11
17. The method of , wherein the stress of said first conductive material is tensile.
claim 11
18. The method of , wherein said step (b.) is performed during said step (a.).
claim 11
19. The method of , wherein said integrated circuit structure further comprises a dielectric layer overlying said first conductive material.
claim 11
20. The method of , wherein said integrated circuit structure further comprises a third conductive material comprising at least fifty percent atomic of silicon underlying said second conductive material, wherein the stress of said third conductive material is compressive.
claim 11
21. A product produced by the method of .
claim 11
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US09/738,001 US6380008B2 (en) | 1997-06-16 | 2000-12-14 | Edge stress reduction by noncoincident layers |
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US4976597P | 1997-06-16 | 1997-06-16 | |
US09/096,012 US6373088B2 (en) | 1997-06-16 | 1998-06-10 | Edge stress reduction by noncoincident layers |
US09/738,001 US6380008B2 (en) | 1997-06-16 | 2000-12-14 | Edge stress reduction by noncoincident layers |
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US09/096,012 Division US6373088B2 (en) | 1997-06-16 | 1998-06-10 | Edge stress reduction by noncoincident layers |
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US20010001724A1 true US20010001724A1 (en) | 2001-05-24 |
US6380008B2 US6380008B2 (en) | 2002-04-30 |
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US09/738,001 Expired - Lifetime US6380008B2 (en) | 1997-06-16 | 2000-12-14 | Edge stress reduction by noncoincident layers |
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Also Published As
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US20010026004A1 (en) | 2001-10-04 |
US6380008B2 (en) | 2002-04-30 |
US6373088B2 (en) | 2002-04-16 |
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