US20010005034A1 - Inductor with magnetic material layers - Google Patents
Inductor with magnetic material layers Download PDFInfo
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- US20010005034A1 US20010005034A1 US09/789,146 US78914601A US2001005034A1 US 20010005034 A1 US20010005034 A1 US 20010005034A1 US 78914601 A US78914601 A US 78914601A US 2001005034 A1 US2001005034 A1 US 2001005034A1
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- inductor
- magnetic material
- insulating layer
- layer
- inductor pattern
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- 239000000696 magnetic material Substances 0.000 title claims abstract description 154
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 21
- 230000005291 magnetic effect Effects 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 230000003014 reinforcing effect Effects 0.000 claims description 13
- 230000005294 ferromagnetic effect Effects 0.000 claims 20
- 230000004888 barrier function Effects 0.000 abstract description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000013459 approach Methods 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- UCNNJGDEJXIUCC-UHFFFAOYSA-L hydroxy(oxo)iron;iron Chemical compound [Fe].O[Fe]=O.O[Fe]=O UCNNJGDEJXIUCC-UHFFFAOYSA-L 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49021—Magnetic recording reproducing transducer [e.g., tape head, core, etc.]
- Y10T29/49032—Fabricating head structure or component thereof
- Y10T29/4906—Providing winding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49021—Magnetic recording reproducing transducer [e.g., tape head, core, etc.]
- Y10T29/49032—Fabricating head structure or component thereof
- Y10T29/4906—Providing winding
- Y10T29/49064—Providing winding by coating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49069—Data storage inductor or core
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Abstract
Description
- The present invention relates to inductors, and particularly to inductors used in integrated circuits.
- The telecommunications and computer industries are driving the demand for miniaturized analog and mixed signal circuits. Inductors are a critical component in the traditional discrete element circuits, such as impedence matching circuits, resonant tank circuits, linear filters, and power circuits, used in these industries. Since traditional inductors are bulky components, successful integration of the traditional discrete element circuits requires the development of miniaturized inductors.
- One approach to miniaturizing an inductor is to use standard integrated circuit building blocks, such as resistors, capacitors, and active circuitry, such as operational amplifiers, to design an active inductor that simulates the electrical properties of a discrete inductor. Active inductors can be designed to have a high inductance and a high Q factor, but inductors fabricated using these designs consume a great deal of power and generate noise.
- A second approach to miniaturizing an inductor is to fabricate a solenoid type inductor with a core using conventional integrated circuit manufacturing process technology. Unfortunately, conventional integrated circuit process steps do not lend themselves to precisely and inexpensively fabricating a helical structure with a core. So, integrated circuit process technology is only marginally compatible with manufacturing a solenoid type inductor.
- A third approach, sometimes used in the fabrication of miniature inductors in gallium arsenide circuits, is to fabricate a spiral type inductor using conventional integrated circuit processes. Unfortunately, this approach has a high cost factor associated with it when applied to fabricating inductors for use in silicon integrated circuits. Silicon integrated circuits operate at lower frequencies than gallium arsenide circuits, and generally require inductors having a higher inductance than inductors used in gallium arsenide circuits. The higher inductance is realized in a spiral inductor occupying a large surface area on the silicon substrate.
- For these and other reasons there is a need for the present invention.
- In one embodiment of the invention, an inductor comprises layers of material deposited on a silicon substrate. First, a layer of magnetic material is deposited on the silicon substrate. Next, an insulating layer is deposited on the magnetic material layer. An inductor pattern is deposited on the insulating layer and above the magnetic material layer. Finally, a second insulating layer is deposited on the inductor pattern, and a second magnetic material layer is deposited on the second insulating layer. The second magnetic material layer is deposited above the inductor pattern.
- In an alternate embodiment, the inductor described above is coupled to another electronic device in an integrated circuit.
- In still another embodiment, a plurality of sandwich structures are vertically stacked on an insulating layer that is deposited on a layer of magnetic material. The layer of magnetic material is deposited on a silicon substrate. The sandwich structures include an inductor pattern, an insulating layer deposited on the inductor pattern, a layer of magnetic material deposited on the insulating layer and above the inductor pattern, and an insulating layer deposited on the magnetic material layer. The structures also include a conducting path through the structures, such that each inductor pattern is serially connected to the inductor pattern above by the conducting path. The current flowing in the serially connected inductor patterns creates a reinforcing magnetic field in the magnetic material between adjacent inductor patterns.
- In still another embodiment, a method of fabricating an inductor comprises a series of steps. First, a silicon substrate is selected, a layer of magnetic material is deposited on the substrate, and an insulating layer is deposited on the magnetic material layer. Next, a plurality of sandwich structures are stacked on the insulating layer. The method of fabricating the structures comprises the steps of depositing an inductor pattern on the insulating layer and above the magnetic material layer, depositing an insulating layer on the inductor pattern, depositing a layer of magnetic material on the insulating layer and above the inductor pattern, and depositing an insulating layer on the magnetic material layer. Finally, a conducting path is fabricated through the structures to connect each inductor pattern serially to the inductor pattern above, such that a current flowing in the serially connected inductor patterns creates a reinforcing magnetic field in the magnetic material between adjacent inductor patterns.
- FIG. 1A is a cross-sectional view of one embodiment of a square spiral inductor embedded in a solid state structure.
- FIG. 1B is a top view of one embodiment of a square spiral inductor pattern.
- FIG. 2 is a cross-sectional view one embodiment of an inductor coupled to another electronic device in an integrated circuit.
- FIG. 3A is a cross-sectional view of one embodiment of two vertically stacked inductors.
- FIG. 3B is a cross-sectional view of one embodiment of two stacked and serially connected inductors showing the current in the inductors and the resulting magnetic field lines.
- In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
- Inductors intended for use in circuits fabricated on a silicon substrate usually operate at lower frequencies and require larger inductances than inductors intended for use in circuits fabricated on a gallium arsenide substrate. As mentioned above, a larger inductance is usually realized in silicon by having the inductor occupy a larger surface area. According to one embodiment of the present invention, rather than increasing the inductance by increasing the surface area occupied by the inductor, a larger inductance is achieved by adding a layer of magnetic material to the inductor.
- Referring to FIG. 1A, a cross-sectional view of one embodiment of a square spiral inductor of the present invention is shown.
Inductor 100 is formed onsubstrate 110 and comprisesmagnetic material layer 120,insulating layer 130,inductor pattern 140, secondinsulating layer 150, and secondmagnetic material layer 160.Magnetic material layer 120 is deposited onsubstrate 110,insulating layer 130 is deposited onmagnetic material layer 120,inductor pattern 140 is deposited oninsulating layer 130, secondinsulating layer 150 is deposited oninductor pattern 140, and secondmagnetic material layer 160 is deposited on secondinsulating layer 150. -
Substrate 110, in one embodiment, is a semiconductor, and even though the invention is not limited to a particular type of semiconductor, silicon is the preferred semiconductor substrate material. -
Magnetic material layer 120, in one embodiment, is deposited on the surface ofsubstrate 110. The particular magnetic material selected for use in a particular inductor design depends on the inductance requirement. In one embodiment, in which a large inductance in a small volume is desired, a high permeability ferromagnetic material, such as pure iron or a NiFe alloy is selected. An example of a high permeability NiFe alloy is an alloy of 81% Ni and 19% Fe. Electrically conducting films, such as an insulating magnetic oxide film, may also be suitable for use in the present invention. -
Insulating layer 130 is deposited onmagnetic material layer 120. In one embodiment,insulating layer 130 is an inorganic silicon oxide film. In an alternate embodiment,insulating layer 130 is silicon dioxide. In still another embodiment, which is perhaps preferable in a low temperature processing environment,insulating layer 130 is an organic insulator, such as parylene and polyimide. -
Inductor pattern 140 is deposited on insulatinglayer 130. In one embodiment,inductor pattern 140 is a spiral. In an alternate embodiment,inductor pattern 140 is a circular spiral. In a second alternate embodiment,inductor pattern 140 is a polygonal spiral, where the polygonal spiral may be in the shape of a triangle, square, rectangle, octagon, or hexagon. A square spiral inductor pattern, which is shown asinductor pattern 140 in FIG. 1B, is preferred, since it is easy to manufacture.Inductor pattern 140 is fabricated from a high-conductivity material. In one embodiment the high-conductivity material is gold. In an alternate embodiment, the high-conductivity material is copper. - Referring to FIG. 1A, second insulating
layer 150 is deposited oninductor pattern 140, and is fabricated from the same materials as insulatinglayer 130. - Second
magnetic material layer 160 is deposited on second insulatinglayer 150, and is fabricated from the same materials asmagnetic material layer 120. Secondmagnetic material layer 160 is preferably located aboveinductor pattern 140, and secondmagnetic material layer 160 does not intersect the plane ofmagnetic material layer 160. - Locating
magnetic material layer 160 aboveinductor pattern 140 allows the contribution of the magnetic material to the inductance of the inductor to be precisely controlled during the manufacturing process. The thickness of the layer of magnetic material along with the magnetic properties of the material define the contribution of the layer to the inductance of the inductor. Once the properties of the material are established during the preparation of the material, the thickness of the layer, which can be precisely controlled in an integrated circuit manufacturing process, defines the contribution of the layer of magnetic material to the inductance. - In one embodiment, the inductor of the present invention is connected to other electronic devices in an integrated circuit. The inductor of the present invention is compatible with conventional silicon manufacturing processes. Structures for coupling passive devices, such as inductors, to other integrated circuit devices are known in the art.
- Referring to FIG. 2,
inductor 200 is coupled todevice 210. The coupling is accomplished by providing conductingpath 220 frominductor pattern 230, throughvias 240, todevice 210. - Referring to FIG. 3A, one embodiment of
inductor structure 300, which combines two inductors, is shown.Inductor structure 300 comprisesbase structure 305,sandwich structure 310,second sandwich structure 315, and conductingpath 320.Base structure 305 includessubstrate 325,magnetic material layer 330, and insulatinglayer 335.Sandwich structure 310 includesinductor pattern 340, insulatinglayer 345,magnetic material layer 350, and insulatinglayer 355.Second sandwich structure 315 is stacked onsandwich structure 310.Second sandwich structure 315 includesinductor pattern 360, insulatinglayer 365,magnetic material layer 370, and insulatinglayer 375. - Conducting
path 320 couplessandwich structure 310 tosecond sandwich structure 315, and serially connectsinductor pattern 340 toinductor pattern 360. A current flowing in the serially connected inductor patterns creates a reinforcing magnetic field inmagnetic material layer 350. Magnetic material layers 330 and 370 are located belowinductor pattern 340 and aboveinductor pattern 360, respectively. Magnetic material layers 330 and 370 confine the magnetic flux and noise radiated by a current flowing ininductor pattern 340 andinductor pattern 360 to the area bounded by the outer surfaces of magnetic material layers 330 and 370. By stacking sandwich structures, in one embodiment, a large inductance can be created without increasing the surface area on a substrate occupied by the inductor. - Referring to FIG. 3B, a diagram showing the currents and the resulting reinforcing magnetic fields of the two inductor sandwich of FIG. 3A is shown. Current375 flows in inductor pattern 380, in conducting
path 385, and ininductor pattern 390. The resultingmagnetic field lines 395 are shown as reinforcing each other inmagnetic material 398, which corresponds tomagnetic material layer 350 in FIG. 3A.Magnetic field lines 395 are confined by magnetic material barrier layers 399. - It is to be recognized that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (120)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US09/789,146 US6287932B2 (en) | 1999-02-03 | 2001-02-20 | Inductor with magnetic material layers |
US09/946,054 US7497005B2 (en) | 1999-02-03 | 2001-09-04 | Method for forming an inductor |
US12/362,621 US20090137067A1 (en) | 1999-02-03 | 2009-01-30 | Method for forming an inductor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/243,584 US6191468B1 (en) | 1999-02-03 | 1999-02-03 | Inductor with magnetic material layers |
US09/789,146 US6287932B2 (en) | 1999-02-03 | 2001-02-20 | Inductor with magnetic material layers |
Related Parent Applications (1)
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US09/243,584 Division US6191468B1 (en) | 1999-02-03 | 1999-02-03 | Inductor with magnetic material layers |
Related Child Applications (1)
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US09/946,054 Continuation US7497005B2 (en) | 1999-02-03 | 2001-09-04 | Method for forming an inductor |
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US20010005034A1 true US20010005034A1 (en) | 2001-06-28 |
US6287932B2 US6287932B2 (en) | 2001-09-11 |
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US09/789,146 Expired - Lifetime US6287932B2 (en) | 1999-02-03 | 2001-02-20 | Inductor with magnetic material layers |
US09/946,054 Expired - Fee Related US7497005B2 (en) | 1999-02-03 | 2001-09-04 | Method for forming an inductor |
US12/362,621 Abandoned US20090137067A1 (en) | 1999-02-03 | 2009-01-30 | Method for forming an inductor |
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US09/243,584 Expired - Lifetime US6191468B1 (en) | 1999-02-03 | 1999-02-03 | Inductor with magnetic material layers |
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US09/946,054 Expired - Fee Related US7497005B2 (en) | 1999-02-03 | 2001-09-04 | Method for forming an inductor |
US12/362,621 Abandoned US20090137067A1 (en) | 1999-02-03 | 2009-01-30 | Method for forming an inductor |
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JP2013135220A (en) * | 2011-12-22 | 2013-07-08 | Samsung Electro-Mechanics Co Ltd | Chip inductor and method for manufacturing the same |
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Also Published As
Publication number | Publication date |
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US20020005565A1 (en) | 2002-01-17 |
US7497005B2 (en) | 2009-03-03 |
US20090137067A1 (en) | 2009-05-28 |
US6191468B1 (en) | 2001-02-20 |
US6287932B2 (en) | 2001-09-11 |
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