US20010005045A1 - Integrated circuit chip and method for fabricating the same - Google Patents

Integrated circuit chip and method for fabricating the same Download PDF

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Publication number
US20010005045A1
US20010005045A1 US09/791,137 US79113701A US2001005045A1 US 20010005045 A1 US20010005045 A1 US 20010005045A1 US 79113701 A US79113701 A US 79113701A US 2001005045 A1 US2001005045 A1 US 2001005045A1
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Prior art keywords
circuit board
board unit
die
lead frame
pads
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US09/791,137
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US6429535B2 (en
Inventor
Ming-Tung Shen
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SUZHOU INDUSTRIAL PARK TONY LIGHTING TECHNOLOGY Co Ltd
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Ming-Tung Shen
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Assigned to COMPUTECH INTERNATIONAL VENTURES LIMITED reassignment COMPUTECH INTERNATIONAL VENTURES LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHEN, MING-TUNG
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Publication of US6429535B2 publication Critical patent/US6429535B2/en
Assigned to SUZHOU INDUSTRIAL PARK TONY LIGHTING TECHNOLOGY CO. LTD. reassignment SUZHOU INDUSTRIAL PARK TONY LIGHTING TECHNOLOGY CO. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: COMPUTECH INTERNATIONAL VENTURES LTD.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the invention relates to an integrated circuit chip and a method for fabricating the same, more particularly to an integrated circuit chip and a method for fabricating the same that can reduce production costs and that can increase production capacity.
  • FIGS. 1A to 1 C a conventional method for fabricating an integrated circuit chip is shown.
  • a die 10 having an upper surface provided with a plurality of solder pads 100 is attached to a tie bar 130 on a lead frame 13 by means of a double-side adhesive tape 12 to fix the die 10 on the lead frame 13 .
  • the solder pads 100 are exposed via a bore 1300 formed in the tie bar 130 , as shown in FIG. 1D.
  • each of the solder pads 100 is connected electrically to a respective lead 131 of the lead frame 13 via known wire bonding techniques by means of a conductive wire 14 that extends through the bore 1300 .
  • a plastic protective layer 15 is used to encapsulate the die 10 and a portion of the lead frame 13 to form an integrated circuit chip.
  • the aforesaid method needs different kinds of lead frames for different kinds of packaging, such as TSOP, SOJ, QFP, SOP and so on.
  • TSOP TSOP
  • SOJ SOJ
  • QFP QFP
  • SOP SOP
  • at least one mold is prepared for each customer, thereby increasing costs.
  • the main object of the present invention is to provide an integrated circuit chip and a method for fabricating the same which can overcome the drawbacks associated with the aforesaid prior art.
  • a method for fabricating an integrated circuit chip comprises:
  • FIGS. 1A to 1 C are fragmentary schematic, partly sectional views showing a conventional method for fabricating an integrated circuit chip.
  • FIG. 1D is a fragmentary top view showing a lead frame used in the conventional method for fabricating an integrated circuit chip.
  • FIGS. 2A to 2 D are fragmentary schematic, partly sectional views showing the first preferred embodiment of a method for fabricating an integrated circuit chip of this invention.
  • FIG. 2E is a fragmentary top view showing a lead frame used in the first preferred embodiment of this invention.
  • FIG. 3 is a fragmentary schematic, partly sectional view showing the second preferred embodiment of this invention.
  • FIG. 4 is a fragmentary schematic, partly sectional view showing the third preferred embodiment of this invention.
  • FIG. 5 is a fragmentary schematic, partly sectional view showing the fourth preferred embodiment of this invention.
  • FIG. 6 is a fragmentary schematic, partly sectional view showing the fifth preferred embodiment of this invention.
  • FIG. 7 is a fragmentary schematic, partly sectional view showing the sixth preferred embodiment of this invention.
  • FIG. 8 is a fragmentary schematic, partly sectional view showing the seventh preferred embodiment of this invention.
  • FIG. 9 is a fragmentary top view showing the seventh preferred embodiment of this invention.
  • FIG. 10 is a fragmentary schematic, partly sectional view showing the eighth preferred embodiment of this invention.
  • FIG. 11 is a fragmentary schematic, partly sectional view showing the ninth preferred embodiment of this invention.
  • FIG. 12 is a fragmentary schematic, partly sectional view showing the tenth preferred embodiment of this invention.
  • FIG. 13 is a fragmentary schematic, partly sectional view showing the eleventh preferred embodiment of this invention.
  • FIG. 14 is a fragmentary schematic, partly sectional view showing the twelfth preferred embodiment of this invention.
  • FIG. 15 is a fragmentary schematic, partly sectional view showing the thirteenth preferred embodiment of this invention.
  • FIG. 16 is a fragmentary schematic, partly sectional view showing the fourteenth preferred embodiment of this invention.
  • FIG. 17 is a fragmentary schematic, partly sectional view showing the fifteenth preferred embodiment of this invention.
  • FIG. 18 is a fragmentary schematic, partly sectional view showing the sixteenth preferred embodiment of this invention.
  • FIG. 19 is a fragmentary schematic, partly sectional view showing the seventeenth preferred embodiment of this invention.
  • FIG. 20 is a fragmentary schematic, partly sectional view showing the eighteenth preferred embodiment of this invention.
  • FIG. 21 is a fragmentary schematic, partly sectional view showing the nineteenth preferred embodiment of this invention.
  • FIG. 22 is a fragmentary schematic, partly sectional view showing the twentieth preferred embodiment of this invention.
  • FIG. 23 is a fragmentary schematic, partly sectional view showing the twenty-first preferred embodiment of this invention.
  • FIG. 24 is a fragmentary schematic, partly sectional view showing the twenty-second preferred embodiment of this invention.
  • FIG. 25 is a fragmentary schematic, partly sectional view showing the twenty-third preferred embodiment of this invention.
  • FIG. 26 is a fragmentary schematic, partly sectional view showing the twenty-fourth preferred embodiment of this invention.
  • an integrated circuit chip includes a circuit board unit 2 , a die 3 , a plurality of conductive wires 4 , a lead frame 5 , a conductive contact layer 51 , and a plastic protective layer 6 .
  • the circuit board unit 2 has a bottom surface 200 formed with a die-receiving cavity 20 , a top surface 210 formed with a bore 21 to access the die-receiving cavity 20 , and a plurality of contact pads 22 on the top surface 210 of the circuit board unit 2 .
  • the die 3 has an upper surface 300 provided with a plurality of solder pads 30 .
  • the die 3 is placed inside the die-receiving cavity 20 such that the solder pads 30 are exposed via the bore 21 in the circuit board unit 2 .
  • the conductive wires 4 extend through the bore 21 and wire-bond the solder pads 30 to the contact pads 22 .
  • the lead frame 5 is placed on top of the circuit board unit 2 .
  • the lead frame 5 has a plurality of leads 50 .
  • the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 .
  • the conductive contact layer 51 is formed from a silver epoxy, such as one that contains both tin and lead, or solder paste that contains tin.
  • the plastic protective layer 6 is used to encapsulate the circuit board unit 2 and at least a portion of the lead frame 5 , as shown in FIG. 2E.
  • FIG. 3 illustrates the second preferred embodiment of this invention, which is based on the first preferred embodiment.
  • the circuit board unit 2 A is further formed with a plurality of electroplated holes 23 registered respectively with the contact pads 22 A and extending through a bottom surface of the circuit board unit 2 A.
  • the lead frame 5 is placed below the circuit board unit 2 A.
  • the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 A to bond leads 50 on the lead frame 5 onto the electroplated holes 23 to establish electrical connection with corresponding ones of the contact pads 22 A.
  • FIG. 4 illustrates the third preferred embodiment of this invention, which is based on the first preferred embodiment.
  • the circuit board unit 2 B includes a lower circuit board 25 formed with the die-receiving cavity 20 B, and an upper circuit board 24 superimposed on the lower circuit board 25 and formed with the bore 21 B.
  • the upper circuit board 24 has the contact pads 22 B formed on the top surface thereof, and is further formed with first electroplated holes 240 registered respectively with the contact pads 22 B.
  • the lower circuit board 25 is formed with second electroplated holes 250 registered respectively with the first electroplated holes 240 .
  • circuit traces (not shown) on the bottom side of the lower circuit board 25 can be connected to the leads 50 of the lead frame 5 via the holes 250 , 240 and the contact pads 22 B.
  • FIG. 5 illustrates the fourth preferred embodiment of this invention, which is based on the first preferred embodiment.
  • the circuit board unit 2 C has a top surface 21 C formed with the die-receiving cavity 20 C.
  • the die 3 is placed in the die-receiving cavity 20 C.
  • the upper surface 300 of the die 3 is flush with the top surface 21 C of the circuit board unit 2 C.
  • FIG. 6 illustrates the fifth preferred embodiment of this invention, which is based on the fourth preferred embodiment.
  • the circuit board unit 2 D is further formed with a plurality of electroplated holes 23 D registered respectively with the contact pads 22 D and extending through a bottom surface of the circuit board unit 2 D.
  • the lead frame 5 is placed below the circuit board unit 2 D.
  • the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 D to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 D to, establish electrical connection with corresponding ones of the contact pads 22 D.
  • FIG. 7 illustrates the sixth preferred embodiment of this invention, which is based on the fourth preferred embodiment.
  • the circuit board unit 2 E includes a lower circuit board 25 E and an upper circuit board 24 E superimposed on the lower circuit board 25 E and formed with the die-receiving cavity 20 E.
  • the upper circuit board 24 E has the contact pads 22 E formed on a top surface 21 E thereof, and is further formed with first electroplated holes 240 E registered respectively with the contact pads 22 E.
  • the lower circuit board 25 E is formed with second electroplated holes 250 E registered respectively with the first electroplated holes 240 E. Circuit traces (not shown) on the bottom side of the lower circuit board 25 E can be connected to the contact pads 22 E via the holes 250 E, 240 E.
  • FIGS. 8 and 9 illustrate the seventh preferred embodiment of this invention, which is based on the first preferred embodiment.
  • the circuit board unit 2 F further has opposite side portions formed with a plurality of positioning notches 26 that correspond respectively to the contact pads 22 F.
  • Each of leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 .
  • the conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 F. The height of the resulting integrated circuit chip can thus be reduced.
  • FIG. 10 illustrates the eighth preferred embodiment of this invention, which is based on the seventh preferred embodiment.
  • the circuit board unit 2 G includes a lower circuit board 25 G formed with the die-receiving cavity, and an upper circuit board 24 G superimposed on the lower circuit board 25 G and formed with the bore to access the die-receiving cavity.
  • the upper circuit board 24 G has the contact pads 22 G on a top surface thereof, and is further formed with first electroplated holes 240 G registered respectively with the contact pads 22 G.
  • the lower circuit board 25 G is formed with second electroplated holes 250 G registered respectively with the first electroplated holes 240 G. Circuit traces (not shown) on the bottom side of the lower circuit board 25 G can be connected to the contact pads 22 G via the holes 250 G, 240 G.
  • FIG. 11 illustrates the ninth preferred embodiment of this invention, which is based on the seventh preferred embodiment.
  • the circuit board unit 2 H has a top surface 21 H formed with the die-receiving cavity 20 H.
  • the die 3 is placed in the die-receiving cavity 20 H.
  • An upper surface 300 of the die 3 is flush with the top surface 21 H of the circuit board unit 2 H.
  • FIG. 12 illustrates the tenth preferred embodiment of this invention, which is based on the ninth preferred embodiment.
  • the circuit board unit 2 I includes a lower circuit board 25 I and an upper circuit board 24 I superimposed on the lower circuit board 25 I and formed with the die-receiving cavity 20 I.
  • the upper circuit board 24 I has the contact pads 22 I formed on a top surface 21 I thereof, and is further formed with first electroplated holes 240 I registered respectively with the contact pads 22 I.
  • the lower circuit board 25 I is formed with second electroplated holes 250 I registered respectively with the first electroplated holes 240 I. Circuit traces (not shown) on the bottom side of the lower circuit board 25 I can be connected to the contact pads 22 I via the holes 250 I, 240 I.
  • FIG. 13 illustrates the eleventh preferred embodiment of this invention.
  • a circuit board unit 2 J has a bottom surface formed with a plurality of die-receiving cavities 20 J, and a top surface formed with a plurality of bores 21 J to access a respective one of the die-receiving cavities 20 J and further formed with a plurality of contact pads 22 J.
  • Each of a number of dies 3 has an upper surface provided with a plurality of solder pads 30 .
  • Each of the dies 3 is placed in a respective one of the die-receiving cavities 20 J such that the solder pads 30 on each of the dies 3 are exposed via a respective one of the bores 21 J in the circuit board unit 2 J.
  • a plurality of conductive wires 4 extend through the bore 21 J and wire-bond the solder pads 30 J to the contact pads 22 J.
  • a lead frame 5 is placed on top of the circuit board unit 2 J, and has a plurality of leads 50 .
  • a conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 J to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 J.
  • a plastic protective layer 6 is used to encapsulate the circuit board unit 2 J and at least a portion of the lead frame 5 .
  • FIG. 14 illustrates the twelfth preferred embodiment of this invention, which is based on the eleventh preferred embodiment.
  • the circuit board unit 2 L further has opposite side portions formed with a plurality of positioning notches 26 L that correspond respectively to the contact pads 22 L.
  • Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 L.
  • the conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 L.
  • FIG. 15 illustrates the thirteenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment.
  • the circuit board unit 2 M has a top surface 21 M formed with a plurality of die-receiving cavities 20 M.
  • Each of the dies 3 is placed in a respective one of the die-receiving cavities 20 M.
  • An upper surface 300 of each die 3 is flush with the top surface 21 M of the circuit board unit 2 M.
  • FIG. 16 illustrates the fourteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment.
  • the circuit board unit 2 N further has opposite side portions formed with a plurality of positioning notches 26 N that correspond respectively to the contact pads 22 N.
  • Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 N.
  • a conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 N.
  • FIG. 17 is illustrates the fifteenth preferred embodiment of this invention, which is based on the second preferred embodiment.
  • first and second circuit board units 2 P that are identical in construction.
  • Each of the first and second circuit board units 2 P has a bottom surface formed with a die-receiving cavity 20 P, a top surface formed with a bore 21 P to access the die-receiving cavity 20 P, and a plurality of contact pads 22 P on the top surface.
  • Each of the first and second circuit board units 2 P is further formed with a plurality of electroplated holes 23 P registered respectively with the contact pads 22 P and extending through the bottom surface thereof.
  • the lead frame 5 is placed between the first and second circuit board units 2 P.
  • Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 P to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 P to establish electrical connection with corresponding ones of the contact pads 22 P.
  • FIG. 18 is illustrates the sixteenth preferred embodiment of this invention, which is based on the fifth preferred embodiment.
  • first and second circuit board units 2 Q that are identical in construction.
  • Each of the first and second circuit board units 2 Q has a top surface formed with a die-receiving cavity 20 Q and a plurality of contact pads 22 Q, and a plurality of electroplated holes 23 Q that are registered respectively with the contact pads 22 Q and that extend through a bottom surface thereof.
  • the lead frame 5 is placed between the first and second circuit board units 2 P.
  • Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 P to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 P to establish electrical connection with corresponding ones of the contact pads 22 P.
  • FIG. 19 is illustrates the seventeenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment.
  • the circuit board unit 2 R is further formed with a plurality of electroplated holes 23 R registered respectively with the contact pads 22 R and extending through a bottom surface of the circuit board unit 2 R.
  • the lead frame 5 is placed below the circuit board unit 2 R.
  • the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 R to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 R to establish electrical connection with corresponding ones of the contact pads 22 R.
  • FIG. 20 is illustrates the eighteenth preferred embodiment of this invention, which is based on the seventeenth preferred embodiment.
  • first and second circuit board units 2 S that are identical in construction.
  • Each of the first and second circuit board units 2 S is formed with a plurality of electroplated holes 23 S registered respectively with the contact pads 22 S and extending through a bottom surface thereof.
  • the lead frame 5 is placed between the first and second circuit board units 2 S.
  • Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 S to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 S to establish electrical connection with corresponding ones of the contact pads 22 S.
  • FIG. 21 illustrates the nineteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment.
  • the circuit board unit 2 T is further formed with a plurality of electroplated holes 23 T registered respectively with the contact pads 22 T and extending through a bottom surface of the circuit board unit 2 T.
  • the lead frame 5 is placed below the circuit board unit 2 T.
  • the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 T to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 T to establish electrical connection with corresponding ones of the contact pads 22 T.
  • FIG. 22 is illustrates the twentieth preferred embodiment of this invention, which is based on the nineteenth preferred embodiment.
  • first and second circuit board units 2 U that are identical in construction.
  • Each of the first and second circuit board units 2 U is formed with a plurality of electroplated holes 23 U registered respectively with the contact pads 22 U and extending through a bottom surface thereof.
  • the lead frame 5 is placed between the first and second circuit board units 2 U.
  • Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 U to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 U to establish electrical connection with corresponding ones of the contact pads 22 U.
  • FIG. 23 illustrates the twenty-first preferred embodiment of this invention.
  • a circuit board unit 2 V has a top surface formed with a bore 21 V and a plurality of contact pads 22 V.
  • a die 3 has an upper surface provided with a plurality ot solder pads 30 .
  • the die 3 is attached to a bottom surface of the circuit board unit 2 V by an adhesive layer 27 such that the solder pads 30 on the die 3 are exposed via the bore 21 V in the circuit board unit 2 V.
  • a plurality of conductive wires 4 extend through the bore 21 V and wire-bond the solder pads 30 to the contact pads 22 V.
  • a lead frame 5 is placed on top of the circuit board unit 2 V and has a plurality of leads 50 .
  • a conductive contact layer 51 bonds the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 V.
  • a plastic protective layer 6 is used to encapsulate the circuit board unit 2 V and at least a portion of the lead frame 5 .
  • FIG. 24 illustrates the twenty-second preferred embodiment of this invention, which is based on the twenty-first preferred embodiment.
  • the circuit board unit 2 W further has opposite side portions formed with a plurality of positioning notches 26 W that correspond respectively to the contact pads 22 W.
  • Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26 W.
  • a conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22 W.
  • FIG. 25 illustrates the twenty-third preferred embodiment of this invention, which is based on the twenty-first preferred embodiment.
  • the circuit board unit 2 X is further formed with a plurality of electroplated holes 23 X registered respectively with the contact pads 22 X and extending through a bottom surface of the circuit board unit 2 X.
  • the lead frame 5 is placed below the circuit board unit 2 X.
  • the conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 X to bond the leads 50 on the lead frame 5 onto the electroplated holes 23 X to establish electrical connection with corresponding ones of the contact pads 22 X.
  • FIG. 26 illustrates the twenty-fourth preferred embodiment of this invention, which is based on the twenty-third preferred embodiment.
  • first and second circuit board units 2 Y that are identical in construction.
  • Each of the first and second circuit board units 2 Y is formed with a plurality of electroplated holes 23 Y registered respectively with the contact pads 22 Y and extending through a bottom surface thereof.
  • the lead frame 5 is placed between the first and second circuit board units 2 Y.
  • Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2 Y to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23 Y to establish electrical connection with corresponding ones of the contact pads 22 Y.

Abstract

A method for fabricating an integrated circuit chip includes the steps of:
(a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed;
(d) wire-bonding the solder pads to the contact pads via conductive wires;
(e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates to an integrated circuit chip and a method for fabricating the same, more particularly to an integrated circuit chip and a method for fabricating the same that can reduce production costs and that can increase production capacity. [0002]
  • 2. Description of the Related Art [0003]
  • Referring to FIGS. 1A to [0004] 1C, a conventional method for fabricating an integrated circuit chip is shown. As shown in FIG. 1A, a die 10 having an upper surface provided with a plurality of solder pads 100 is attached to a tie bar 130 on a lead frame 13 by means of a double-side adhesive tape 12 to fix the die 10 on the lead frame 13. The solder pads 100 are exposed via a bore 1300 formed in the tie bar 130, as shown in FIG. 1D. Referring to FIG. 1B, each of the solder pads 100 is connected electrically to a respective lead 131 of the lead frame 13 via known wire bonding techniques by means of a conductive wire 14 that extends through the bore 1300. Referring to FIG. 1C, a plastic protective layer 15 is used to encapsulate the die 10 and a portion of the lead frame 13 to form an integrated circuit chip.
  • The following are some of the drawbacks of the conventional method for fabricating an integrated circuit chip: [0005]
  • 1. The aforesaid method needs different kinds of lead frames for different kinds of packaging, such as TSOP, SOJ, QFP, SOP and so on. Thus, at least one mold is prepared for each customer, thereby increasing costs. [0006]
  • 2. In the aforesaid method, double-side adhesive tape is needed to secure the die on the tie bar, thereby increasing the fabricating costs. [0007]
  • 3. In the aforesaid method, it will take a long time to form the molds for the lead frames, thereby affecting the ability of manufacturers to compete. [0008]
    • SUMMARY OF THE INVENTION
  • Therefore, the main object of the present invention is to provide an integrated circuit chip and a method for fabricating the same which can overcome the drawbacks associated with the aforesaid prior art. [0009]
  • According to this invention, a method for fabricating an integrated circuit chip comprises: [0010]
  • (a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit; [0011]
  • (b) forming a die having an upper surface provided with a plurality of solder pads; [0012]
  • (c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed; [0013]
  • (d) wire-bonding the solder pads to the contact pads via conductive wires; [0014]
  • (e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and [0015]
  • (f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame. [0016]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which: [0017]
  • FIGS. 1A to [0018] 1C are fragmentary schematic, partly sectional views showing a conventional method for fabricating an integrated circuit chip.
  • FIG. 1D is a fragmentary top view showing a lead frame used in the conventional method for fabricating an integrated circuit chip. [0019]
  • FIGS. 2A to [0020] 2D are fragmentary schematic, partly sectional views showing the first preferred embodiment of a method for fabricating an integrated circuit chip of this invention.
  • FIG. 2E is a fragmentary top view showing a lead frame used in the first preferred embodiment of this invention. [0021]
  • FIG. 3 is a fragmentary schematic, partly sectional view showing the second preferred embodiment of this invention. [0022]
  • FIG. 4 is a fragmentary schematic, partly sectional view showing the third preferred embodiment of this invention. [0023]
  • FIG. 5 is a fragmentary schematic, partly sectional view showing the fourth preferred embodiment of this invention. [0024]
  • FIG. 6 is a fragmentary schematic, partly sectional view showing the fifth preferred embodiment of this invention. [0025]
  • FIG. 7 is a fragmentary schematic, partly sectional view showing the sixth preferred embodiment of this invention. [0026]
  • FIG. 8 is a fragmentary schematic, partly sectional view showing the seventh preferred embodiment of this invention. [0027]
  • FIG. 9 is a fragmentary top view showing the seventh preferred embodiment of this invention. [0028]
  • FIG. 10 is a fragmentary schematic, partly sectional view showing the eighth preferred embodiment of this invention. [0029]
  • FIG. 11 is a fragmentary schematic, partly sectional view showing the ninth preferred embodiment of this invention. [0030]
  • FIG. 12 is a fragmentary schematic, partly sectional view showing the tenth preferred embodiment of this invention. [0031]
  • FIG. 13 is a fragmentary schematic, partly sectional view showing the eleventh preferred embodiment of this invention. [0032]
  • FIG. 14 is a fragmentary schematic, partly sectional view showing the twelfth preferred embodiment of this invention. [0033]
  • FIG. 15 is a fragmentary schematic, partly sectional view showing the thirteenth preferred embodiment of this invention. [0034]
  • FIG. 16 is a fragmentary schematic, partly sectional view showing the fourteenth preferred embodiment of this invention. [0035]
  • FIG. 17 is a fragmentary schematic, partly sectional view showing the fifteenth preferred embodiment of this invention. [0036]
  • FIG. 18 is a fragmentary schematic, partly sectional view showing the sixteenth preferred embodiment of this invention. [0037]
  • FIG. 19 is a fragmentary schematic, partly sectional view showing the seventeenth preferred embodiment of this invention. [0038]
  • FIG. 20 is a fragmentary schematic, partly sectional view showing the eighteenth preferred embodiment of this invention. [0039]
  • FIG. 21 is a fragmentary schematic, partly sectional view showing the nineteenth preferred embodiment of this invention. [0040]
  • FIG. 22 is a fragmentary schematic, partly sectional view showing the twentieth preferred embodiment of this invention. [0041]
  • FIG. 23 is a fragmentary schematic, partly sectional view showing the twenty-first preferred embodiment of this invention. [0042]
  • FIG. 24 is a fragmentary schematic, partly sectional view showing the twenty-second preferred embodiment of this invention. [0043]
  • FIG. 25 is a fragmentary schematic, partly sectional view showing the twenty-third preferred embodiment of this invention. [0044]
  • FIG. 26 is a fragmentary schematic, partly sectional view showing the twenty-fourth preferred embodiment of this invention. [0045]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure. [0046]
  • Referring to FIGS. 2A to [0047] 2E, according to the first preferred embodiment of this invention, an integrated circuit chip includes a circuit board unit 2, a die 3, a plurality of conductive wires 4, a lead frame 5, a conductive contact layer 51, and a plastic protective layer 6. Referring to FIGS. 2A and 2B, the circuit board unit 2 has a bottom surface 200 formed with a die-receiving cavity 20, a top surface 210 formed with a bore 21 to access the die-receiving cavity 20, and a plurality of contact pads 22 on the top surface 210 of the circuit board unit 2. The die 3 has an upper surface 300 provided with a plurality of solder pads 30. The die 3 is placed inside the die-receiving cavity 20 such that the solder pads 30 are exposed via the bore 21 in the circuit board unit 2. Referring to FIG. 2C, the conductive wires 4 extend through the bore 21 and wire-bond the solder pads 30 to the contact pads 22. Referring to FIGS. 2C and 2D, the lead frame 5 is placed on top of the circuit board unit 2. The lead frame 5 has a plurality of leads 50. The conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2 to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22. The conductive contact layer 51 is formed from a silver epoxy, such as one that contains both tin and lead, or solder paste that contains tin. The plastic protective layer 6 is used to encapsulate the circuit board unit 2 and at least a portion of the lead frame 5, as shown in FIG. 2E.
  • FIG. 3 illustrates the second preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 3, unlike the first preferred embodiment shown in of FIG. 2D, the [0048] circuit board unit 2A is further formed with a plurality of electroplated holes 23 registered respectively with the contact pads 22A and extending through a bottom surface of the circuit board unit 2A. The lead frame 5 is placed below the circuit board unit 2A. The conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2A to bond leads 50 on the lead frame 5 onto the electroplated holes 23 to establish electrical connection with corresponding ones of the contact pads 22A.
  • FIG. 4 illustrates the third preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 4, unlike the first preferred embodiment shown in FIG. 2D, the [0049] circuit board unit 2B includes a lower circuit board 25 formed with the die-receiving cavity 20B, and an upper circuit board 24 superimposed on the lower circuit board 25 and formed with the bore 21B. The upper circuit board 24 has the contact pads 22B formed on the top surface thereof, and is further formed with first electroplated holes 240 registered respectively with the contact pads 22B. The lower circuit board 25 is formed with second electroplated holes 250 registered respectively with the first electroplated holes 240. Thus, circuit traces (not shown) on the bottom side of the lower circuit board 25 can be connected to the leads 50 of the lead frame 5 via the holes 250, 240 and the contact pads 22B.
  • FIG. 5 illustrates the fourth preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 5, unlike the first preferred embodiment shown in FIG. 2D, the [0050] circuit board unit 2C has a top surface 21C formed with the die-receiving cavity 20C. The die 3 is placed in the die-receiving cavity 20C. The upper surface 300 of the die 3 is flush with the top surface 21C of the circuit board unit 2C.
  • FIG. 6 illustrates the fifth preferred embodiment of this invention, which is based on the fourth preferred embodiment. In FIG. 6, unlike the fourth preferred embodiment shown in FIG. 5, the [0051] circuit board unit 2D is further formed with a plurality of electroplated holes 23D registered respectively with the contact pads 22D and extending through a bottom surface of the circuit board unit 2D. The lead frame 5 is placed below the circuit board unit 2D. The conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2D to bond the leads 50 on the lead frame 5 onto the electroplated holes 23D to, establish electrical connection with corresponding ones of the contact pads 22D.
  • FIG. 7 illustrates the sixth preferred embodiment of this invention, which is based on the fourth preferred embodiment. In FIG. 7, unlike the fourth preferred embodiment shown in FIG. 5, the [0052] circuit board unit 2E includes a lower circuit board 25E and an upper circuit board 24E superimposed on the lower circuit board 25E and formed with the die-receiving cavity 20E. The upper circuit board 24E has the contact pads 22E formed on a top surface 21E thereof, and is further formed with first electroplated holes 240E registered respectively with the contact pads 22E. The lower circuit board 25E is formed with second electroplated holes 250E registered respectively with the first electroplated holes 240E. Circuit traces (not shown) on the bottom side of the lower circuit board 25E can be connected to the contact pads 22E via the holes 250E, 240E.
  • FIGS. 8 and 9 illustrate the seventh preferred embodiment of this invention, which is based on the first preferred embodiment. In FIG. 8, unlike the first preferred embodiment shown in FIG. 2D, the [0053] circuit board unit 2F further has opposite side portions formed with a plurality of positioning notches 26 that correspond respectively to the contact pads 22F. Each of leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26. The conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22F. The height of the resulting integrated circuit chip can thus be reduced.
  • FIG. 10 illustrates the eighth preferred embodiment of this invention, which is based on the seventh preferred embodiment. In FIG. 10, unlike the seventh preferred embodiment shown in FIG. 8, the [0054] circuit board unit 2G includes a lower circuit board 25G formed with the die-receiving cavity, and an upper circuit board 24G superimposed on the lower circuit board 25G and formed with the bore to access the die-receiving cavity. The upper circuit board 24G has the contact pads 22G on a top surface thereof, and is further formed with first electroplated holes 240G registered respectively with the contact pads 22G. The lower circuit board 25G is formed with second electroplated holes 250G registered respectively with the first electroplated holes 240G. Circuit traces (not shown) on the bottom side of the lower circuit board 25G can be connected to the contact pads 22G via the holes 250G, 240G.
  • FIG. 11 illustrates the ninth preferred embodiment of this invention, which is based on the seventh preferred embodiment. In FIG. 11, unlike the seventh preferred embodiment shown in FIG. 8, the [0055] circuit board unit 2H has a top surface 21H formed with the die-receiving cavity 20H. The die 3 is placed in the die-receiving cavity 20H. An upper surface 300 of the die 3 is flush with the top surface 21H of the circuit board unit 2H.
  • FIG. 12 illustrates the tenth preferred embodiment of this invention, which is based on the ninth preferred embodiment. In FIG. 12, unlike the ninth preferred embodiment shown in FIG. 11, the circuit board unit [0056] 2I includes a lower circuit board 25I and an upper circuit board 24I superimposed on the lower circuit board 25I and formed with the die-receiving cavity 20I. The upper circuit board 24I has the contact pads 22I formed on a top surface 21I thereof, and is further formed with first electroplated holes 240I registered respectively with the contact pads 22I. The lower circuit board 25I is formed with second electroplated holes 250I registered respectively with the first electroplated holes 240I. Circuit traces (not shown) on the bottom side of the lower circuit board 25I can be connected to the contact pads 22I via the holes 250I, 240I.
  • FIG. 13 illustrates the eleventh preferred embodiment of this invention. In this embodiment, a circuit board unit [0057] 2J has a bottom surface formed with a plurality of die-receiving cavities 20J, and a top surface formed with a plurality of bores 21J to access a respective one of the die-receiving cavities 20J and further formed with a plurality of contact pads 22J. Each of a number of dies 3 has an upper surface provided with a plurality of solder pads 30. Each of the dies 3 is placed in a respective one of the die-receiving cavities 20J such that the solder pads 30 on each of the dies 3 are exposed via a respective one of the bores 21J in the circuit board unit 2J. A plurality of conductive wires 4 extend through the bore 21J and wire-bond the solder pads 30J to the contact pads 22J. A lead frame 5 is placed on top of the circuit board unit 2J, and has a plurality of leads 50. A conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2J to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22J. Finally, a plastic protective layer 6 is used to encapsulate the circuit board unit 2J and at least a portion of the lead frame 5. Thus, surface mounting steps are reduced to enhance the production capacity.
  • FIG. 14 illustrates the twelfth preferred embodiment of this invention, which is based on the eleventh preferred embodiment. In FIG. 14, unlike the eleventh preferred embodiment shown in FIG. 13, the [0058] circuit board unit 2L further has opposite side portions formed with a plurality of positioning notches 26L that correspond respectively to the contact pads 22L. Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26L. The conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22L.
  • FIG. 15 illustrates the thirteenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment. In FIG. 15, unlike the eleventh preferred embodiment shown in FIG. 13, the circuit board unit [0059] 2M has a top surface 21M formed with a plurality of die-receiving cavities 20M. Each of the dies 3 is placed in a respective one of the die-receiving cavities 20M. An upper surface 300 of each die 3 is flush with the top surface 21M of the circuit board unit 2M.
  • FIG. 16 illustrates the fourteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment. In FIG. 16, unlike the thirteenth preferred embodiment shown in FIG. 15, the [0060] circuit board unit 2N further has opposite side portions formed with a plurality of positioning notches 26N that correspond respectively to the contact pads 22N. Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26N. A conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22N.
  • FIG. 17 is illustrates the fifteenth preferred embodiment of this invention, which is based on the second preferred embodiment. In FIG. 17, unlike the second preferred embodiment shown in FIG. 3, there are first and second [0061] circuit board units 2P that are identical in construction. Each of the first and second circuit board units 2P has a bottom surface formed with a die-receiving cavity 20P, a top surface formed with a bore 21P to access the die-receiving cavity 20P, and a plurality of contact pads 22P on the top surface. Each of the first and second circuit board units 2P is further formed with a plurality of electroplated holes 23P registered respectively with the contact pads 22P and extending through the bottom surface thereof. The lead frame 5 is placed between the first and second circuit board units 2P. Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2P to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23P to establish electrical connection with corresponding ones of the contact pads 22P.
  • FIG. 18 is illustrates the sixteenth preferred embodiment of this invention, which is based on the fifth preferred embodiment. In FIG. 18, unlike the fifth preferred embodiment shown in FIG. 6, there are first and second [0062] circuit board units 2Q that are identical in construction. Each of the first and second circuit board units 2Q has a top surface formed with a die-receiving cavity 20Q and a plurality of contact pads 22Q, and a plurality of electroplated holes 23Q that are registered respectively with the contact pads 22Q and that extend through a bottom surface thereof. The lead frame 5 is placed between the first and second circuit board units 2P. Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2P to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23P to establish electrical connection with corresponding ones of the contact pads 22P.
  • FIG. 19 is illustrates the seventeenth preferred embodiment of this invention, which is based on the eleventh preferred embodiment. In FIG. 19, unlike the eleventh preferred embodiment shown in FIG. 13, the [0063] circuit board unit 2R is further formed with a plurality of electroplated holes 23R registered respectively with the contact pads 22R and extending through a bottom surface of the circuit board unit 2R. The lead frame 5 is placed below the circuit board unit 2R. The conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2R to bond the leads 50 on the lead frame 5 onto the electroplated holes 23R to establish electrical connection with corresponding ones of the contact pads 22R.
  • FIG. 20 is illustrates the eighteenth preferred embodiment of this invention, which is based on the seventeenth preferred embodiment. In FIG. 20, unlike the seventeenth preferred embodiment shown in FIG. 19, there are first and second circuit board units [0064] 2S that are identical in construction. Each of the first and second circuit board units 2S is formed with a plurality of electroplated holes 23S registered respectively with the contact pads 22S and extending through a bottom surface thereof. The lead frame 5 is placed between the first and second circuit board units 2S. Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2S to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23S to establish electrical connection with corresponding ones of the contact pads 22S.
  • FIG. 21 illustrates the nineteenth preferred embodiment of this invention, which is based on the thirteenth preferred embodiment. In FIG. 21, unlike the thirteenth preferred embodiment shown in FIG. 15, the [0065] circuit board unit 2T is further formed with a plurality of electroplated holes 23T registered respectively with the contact pads 22T and extending through a bottom surface of the circuit board unit 2T. The lead frame 5 is placed below the circuit board unit 2T. The conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2T to bond the leads 50 on the lead frame 5 onto the electroplated holes 23T to establish electrical connection with corresponding ones of the contact pads 22T.
  • FIG. 22 is illustrates the twentieth preferred embodiment of this invention, which is based on the nineteenth preferred embodiment. In FIG. 22, unlike the nineteenth preferred embodiment shown in FIG. 19, there are first and second [0066] circuit board units 2U that are identical in construction. Each of the first and second circuit board units 2U is formed with a plurality of electroplated holes 23U registered respectively with the contact pads 22U and extending through a bottom surface thereof. The lead frame 5 is placed between the first and second circuit board units 2U. Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2U to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23U to establish electrical connection with corresponding ones of the contact pads 22U.
  • FIG. 23 illustrates the twenty-first preferred embodiment of this invention. In this embodiment, a [0067] circuit board unit 2V has a top surface formed with a bore 21V and a plurality of contact pads 22V. A die 3 has an upper surface provided with a plurality ot solder pads 30. The die 3 is attached to a bottom surface of the circuit board unit 2V by an adhesive layer 27 such that the solder pads 30 on the die 3 are exposed via the bore 21V in the circuit board unit 2V. A plurality of conductive wires 4 extend through the bore 21V and wire-bond the solder pads 30 to the contact pads 22V. A lead frame 5 is placed on top of the circuit board unit 2V and has a plurality of leads 50. A conductive contact layer 51 bonds the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22V. Finally, a plastic protective layer 6 is used to encapsulate the circuit board unit 2V and at least a portion of the lead frame 5.
  • FIG. 24 illustrates the twenty-second preferred embodiment of this invention, which is based on the twenty-first preferred embodiment. In FIG. 24, unlike the twenty-first preferred embodiment shown in FIG. 23, the [0068] circuit board unit 2W further has opposite side portions formed with a plurality of positioning notches 26W that correspond respectively to the contact pads 22W. Each of the leads 50 on the lead frame 5 has one end inserted into a respective one of the positioning notches 26W. A conductive contact layer 51 is used to bond the leads 50 on the lead frame 5 onto corresponding ones of the contact pads 22W.
  • FIG. 25 illustrates the twenty-third preferred embodiment of this invention, which is based on the twenty-first preferred embodiment. In FIG. 25, unlike the twenty-first preferred embodiment shown in FIG. 23, the [0069] circuit board unit 2X is further formed with a plurality of electroplated holes 23X registered respectively with the contact pads 22X and extending through a bottom surface of the circuit board unit 2X. The lead frame 5 is placed below the circuit board unit 2X. The conductive contact layer 51 is disposed between the lead frame 5 and the circuit board unit 2X to bond the leads 50 on the lead frame 5 onto the electroplated holes 23X to establish electrical connection with corresponding ones of the contact pads 22X.
  • FIG. 26 illustrates the twenty-fourth preferred embodiment of this invention, which is based on the twenty-third preferred embodiment. In FIG. 26, unlike the twenty-third preferred embodiment shown in FIG. 25, there are first and second [0070] circuit board units 2Y that are identical in construction. Each of the first and second circuit board units 2Y is formed with a plurality of electroplated holes 23Y registered respectively with the contact pads 22Y and extending through a bottom surface thereof. The lead frame 5 is placed between the first and second circuit board units 2Y. Each of two conductive contact layers 51 is disposed between the lead frame 5 and a respective one of the first and second circuit board units 2Y to bond the leads 50 on the lead frame 5 onto respective ones of the electroplated holes 23Y to establish electrical connection with corresponding ones of the contact pads 22Y.
  • While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements. [0071]

Claims (90)

I claim:
1. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with a die-receiving cavity at a bottom surface of the circuit board unit, a bore to access the die-receiving cavity at a top surface of the circuit board unit, and a plurality of contact pads on the top surface of the circuit board unit;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed via the bore in the circuit board unit;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires that extend through the bore;
(e) placing a lead frame on top of the circuit board unit, and bonding leads on the lead frame onto corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
2. The method of
claim 1
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
3. The method of claim l, wherein the conductive contact layer used in step (e) is formed from solder paste.
4. The method of
claim 1
, wherein, in step (a), the circuit board unit includes a lower circuit board formed with the die-receiving cavity; and an upper circuit board superimposed on the lower circuit board and formed with the bore, the upper circuit board being formed with first electroplated holes registered respectively with the contact pads, the lower circuit board being formed with second electroplated holes registered respectively with the first electroplated holes.
5. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with a die-receiving cavity and a plurality of contact pads on a top surface of the circuit board unit;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed from the die-receiving cavity;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires;
(e) placing a lead frame on top of the circuit board unit, and bonding leads on the lead frame onto corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
6. The method of
claim 5
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
7. The method of
claim 5
, wherein the conductive contact layer used in step (e) is formed from solder paste.
8. The method of
claim 5
, wherein, in step (a), the circuit board unit includes a lower circuit board and an upper circuit board superimposed on the lower circuit board and formed with the die-receiving cavity, the upper circuit board being formed with first electroplated holes registered respectively with the contact pads, the lower circuit board being formed with second electroplated holes registered respectively with the first electroplated holes.
9. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with at least two die-receiving cavities at a bottom surface of the circuit board unit, at least two bores to access a respective one of the die-receiving cavities at a top surface of the circuit board unit, and a plurality of contact pads on the top surface of the circuit board unit;
(b) forming at least two dies, each having an upper surface provided with a plurality of solder pads;
(c) placing each of the dies in a respective one of the die-receiving cavities such that the solder pads on each of the dies are exposed via a respective one of the bores in the circuit board unit;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires that extend through the bores;
(e) placing a lead frame on top of the circuit board unit, and bonding leads on the lead frame onto corresponding ones of the contact pads on edge portions of the circuit board unit via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
10. The method of
claim 9
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
11. The method of
claim 9
, wherein the conductive contact layer used in step (e) is formed from solder paste.
12. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with at least two die-receiving cavities and a plurality of contact pads at a top surface of the circuit board unit;
(b) forming at least two dies, each having an upper surface provided with a plurality of solder pads;
(c) placing each of the dies in a respective one of the die-receiving cavities such that the solder pads on each of the dies are exposed from the respective one of the die receiving cavities;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires;
(e) placing a lead frame on top of the circuit board unit, and bonding leads on the lead frame onto corresponding ones of the contact pads on edge portions of the circuit board unit via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
13. The method of
claim 12
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
14. The method of
claim 12
, wherein the conductive contact layer used in step (e) is formed from solder paste.
15. A method for fabricating an integrated circuit chip, comprising:
(a) forming a first circuit board unit with a first die-receiving cavity at a bottom surface of the first circuit board unit, a first bore to access the first die-receiving cavity at a top surface of the first circuit board unit, a plurality of first contact pads on the top surface of the first circuit board unit, and a plurality of first electroplated holes that are registered respectively with the first contact pads and that extend through the bottom surface of the first circuit board unit;
(b) forming a first die having an upper surface provided with a plurality of first solder pads;
(c) placing the first die in the first die-receiving cavity such that the first solder pads on the first die are exposed via the first bore in the first circuit board unit;
(d) wire-bonding the first solder pads to the first contact pads by means of first conductive wires that extend through the first bore;
(e) placing a lead frame below the first circuit board unit, and bonding leads on the lead frame onto the first electroplated holes to establish electrical connection with corresponding ones of the first contact pads via a first conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the first circuit board unit and at least a portion of the lead frame.
16. The method of
claim 15
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
17. The method of
claim 15
, wherein the conductive contact layer used in step (e) is formed from solder paste.
18. The method of
claim 15
, further comprising, prior to step (f):
forming a second circuit board unit with a second die-receiving cavity at a bottom surface of the second circuit board unit, a second bore to access the second die-receiving cavity at a top surface of the second circuit board unit, a plurality of second contact pads on the top surface of the second circuit board unit, and a plurality of second electroplated holes that are registered respectively with the second contact pads and that extend through the bottom surface of the second circuit board unit;
forming a second die having an upper surface provided with a plurality of second solder pads;
placing the second die in the second die-receiving cavity such that the second solder pads on the second die are exposed via the second bore in the second circuit board unit;
wire-bonding the second solder pads to the second contact pads by means of second conductive wires that extend through the second bore; and
with the lead frame disposed between the first and second circuit board units, bonding the leads on the lead frame onto the second electroplated holes to establish electrical connection with corresponding ones of the second contact pads via a second conductive contact layer.
19. A method for fabricating an integrated circuit chip, comprising:
(a) forming a first circuit board unit with a first die-receiving cavity and a plurality of first contact pads on a top surface of the first circuit board unit, and a plurality of first electroplated holes that are registered respectively with the first contact pads and that extend through a bottom surface of the first circuit board unit;
(b) forming a first die having an upper surface provided with a plurality of first solder pads;
(c) placing the first die in the first die-receiving cavity such that the first solder pads on the first die are exposed from the first die-receiving cavity;
(d) wire-bonding the first solder pads to the first contact pads by means of first conductive wires;
(e) placing a lead frame below the first circuit board unit, and bonding leads on the lead frame onto the first electroplated holes to establish electrical connection with corresponding ones of the first contact pads via a first conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the first circuit board unit and at least a portion of the lead frame.
20. The method of
claim 19
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
21. The method of
claim 19
, wherein the conductive contact layer used in step (e) is formed from solder paste.
22. The method of
claim 19
, further comprising, prior to step (f):
forming a second circuit board unit with a second die-receiving cavity and a plurality of second contact pads on a top surface of the second circuit board unit, and a plurality of second electroplated holes that are registered respectively with the second contact pads and that extend through a bottom surface of the second circuit board unit;
forming a second die having an upper surface provided with a plurality of second solder pads;
placing the second die in the second die-receiving cavity such that the second solder pads on the second die are exposed from the second die-receiving cavity;
wire-bonding the second solder pads to the second contact pads by means of second conductive wires; and
with the lead frame disposed between the first and second circuit board units, bonding the leads on the lead frame onto the second electroplated holes to establish electrical connection with corresponding ones of the second contact pads via a second conductive contact layer.
23. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with a die-receiving cavity at a bottom surface of the circuit board unit, a bore to access the die-receiving cavity at a top surface of the circuit board unit, a plurality of contact pads on the top surface of the circuit board unit, and a plurality of positioning notches that are disposed on opposite side portions of the circuit board unit and that correspond respectively to the contact pads;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed via the bore in the circuit board unit;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires that extend through the bore;
(e) inserting one end of each of a plurality of leads of a lead frame into a respective one of the positioning notches, and bonding the leads on the lead frame onto corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
24. The method of
claim 23
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
25. The method of
claim 23
, wherein the conductive contact layer used in step (e) is formed from solder paste.
26. The method of
claim 23
, wherein, in step (a), the circuit board unit includes a lower circuit board formed with the die-receiving cavity, and an upper circuit board superimposed on the lower circuit board and formed with the bore, the upper circuit board being formed with first electroplated holes registered respectively with the contact pads, the lower circuit board being formed with second electroplated holes registered respectively with the first electroplated holes.
27. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with a die-receiving cavity and a plurality of contact pads on a top surface of the circuit board unit, and a plurality of positioning notches that are disposed on opposite side portions of the circuit board unit and that correspond respectively to the contact pads;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed from the die-receiving cavity;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires;
(e) inserting one end of each of a plurality of leads of a lead frame into a respective one of the positioning notches, and bonding the leads on the lead frame onto corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
28. The method of
claim 27
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
29. The method of
claim 27
, wherein the conductive contact layer used in step (e) is formed from solder paste.
30. The method of
claim 27
, wherein, in step (a), the circuit board unit includes a lower circuit board, and an upper circuit board superimposed on the lower circuit board and formed with the die-receiving cavity, the upper circuit board being formed with first electroplated holes registered respectively with the contact pads, the lower circuit board being formed with second electroplated holes registered respectively with the first electroplated holes.
31. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with at least two die-receiving cavities at a bottom surface of the circuit board unit, at least two bores to access a respective one of the die-receiving cavities at a top surface of the circuit board unit, a plurality of contact pads on the top surface of the circuit board unit, and a plurality of positioning notches that are disposed on opposite side portions of the circuit board unit and that correspond respectively to the contact pads;
(b) forming at least two dies, each having an upper surface provided with a plurality of solder pads;
(c) placing each of the dies in a respective one of the die-receiving cavities such that the solder pads on each of the dies are exposed via a respective one of the bores in the circuit board unit;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires that extend through the bores;
(e) inserting one end of each of a plurality of leads of a lead frame into a respective one of the positioning notches, and bonding the leads on the lead frame onto corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
32. The method of
claim 31
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
33. The method of
claim 31
, wherein the conductive contact layer used in step (e) is formed from solder paste.
34. A method for fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with at least two die-receiving cavities and a plurality of contact pads at a top surface of the circuit board unit, and a plurality of positioning notches that are disposed on opposite side portions of the circuit board unit and that correspond respectively to the contact pads;
(b) forming at least two dies, each having an upper surface provided with a plurality of solder pads;
(c) placing each of the dies in a respective one of the die-receiving cavities such that the solder pads on each of the dies are exposed from the respective one of the die receiving cavities;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires;
(e) inserting one end of each of a plurality of leads of a lead frame into a respective one of the positioning notches, and bonding the leads on the lead frame onto corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
35. The method of
claim 34
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
36. The method of
claim 34
, wherein the conductive contact layer used in step (e) is formed from solder paste.
37. An integrated circuit chip comprising:
a circuit board unit having a bottom surface formed with a die-receiving cavity, a top surface formed with a bore to access said die-receiving cavity, and a plurality of contact pads on said top surface of said circuit board unit;
a die having an upper surface provided with a plurality of solder pads, said die being placed inside said die-receiving cavity such that said solder pads are exposed via said bore in said circuit board unit;
a plurality of conductive wires that extend through said bore and that wire-bond said solder pads to said contact pads;
a lead frame placed on top of said circuit board unit, said lead frame having a plurality of leads;
a conductive contact layer disposed between said lead frame and said circuit board unit to bond said leads on said lead frame onto corresponding ones of said contact pads; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
38. The integrated circuit chip of
claim 37
, wherein said conductive contact layer is formed from a silver epoxy.
39. The integrated circuit chip of
claim 37
, wherein said conductive contact layer is formed from solder paste.
40. The integrated circuit chip of
claim 37
, wherein said circuit board unit includes a lower circuit board formed with said die-receiving cavity, and an upper circuit board superimposed on said lower circuit board and formed with said bore, said upper circuit board being formed with first electroplated holes registered respectively with said contact pads, said lower circuit board being formed with second electroplated holes registered respectively with said first electroplated holes.
41. An integrated circuit chip comprising:
a circuit board unit having a top surface formed with a die-receiving cavity and a plurality of contact pads;
a die having an upper surface provided with a plurality of solder pads, said die being placed in said die-receiving cavity such that said solder pads are exposed from said die-receiving cavity;
a plurality of conductive wires for wire-bonding said solder pads to said contact pads;
a lead frame placed on top of said circuit board unit, said lead frame having a plurality of leads;
a conductive contact layer disposed between said lead frame and said circuit board unit to bond said leads on said lead frame onto corresponding ones of said contact pads; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
42. The integrated circuit chip of
claim 41
, wherein said conductive contact layer is formed from a silver epoxy.
43. The integrated circuit chip of
claim 41
, wherein said conductive contact layer is formed from solder paste.
44. The integrated circuit chip of
claim 41
, wherein said circuit board unit includes a lower circuit board and an upper circuit board superimposed on said lower circuit board and formed with said die-receiving cavity, said upper circuit board being formed with first electroplated holes registered respectively with said contact pads, said lower circuit board being formed with second electroplated holes registered respectively with said first electroplated holes.
45. An integrated circuit chip comprising:
a circuit board unit having a bottom surface formed with at least two die-receiving cavities, and a top surface formed with at least two bores to access a respective one of said die-receiving cavities and further formed with a plurality of contact pads;
at least two dies, each having an upper surface provided with a plurality of solder pads, each of said, dies being placed in a respective one of said die-receiving cavities such that said solder pads on each of said dies are exposed via a respective one of said bores in said circuit board unit;
a plurality of conductive wires that extend through said bores and that wire-bond said solder pads to said contact pads;
a lead frame placed on top of said circuit board unit, said lead frame having a plurality of leads;
a conductive contact layer disposed between said lead frame and said circuit board unit to bond said leads on said lead frame onto corresponding ones of said contact pads; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
46. The integrated circuit chip of
claim 45
, wherein said conductive contact layer is formed from a epoxy.
47. The integrated circuit chip of
claim 45
, wherein said conductive contact layer is formed from solder paste.
48. An integrated circuit chip comprising:
a circuit board unit having a top surface formed with at least two die-receiving cavities and a plurality of contact pads;
at least two dies, each having an upper surface provided with a plurality of solder pads, each of said dies being placed in a respective one of said die-receiving cavities such that said solder pads on each of said dies are exposed from the respective one of said die receiving cavities;
a plurality of conductive wires that wire-bond said solder pads to said contact pads;
a lead frame placed on top of said circuit board unit, said lead frame having a plurality of leads;
a conductive contact layer that bonds said leads on said lead frame onto corresponding ones of said contact pads; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
49. The integrated circuit chip of
claim 48
, wherein said conductive contact layer is formed from a silver epoxy.
50. The integrated circuit chip of
claim 48
, wherein said conductive contact layer is formed from solder paste.
51. An integrated circuit chip comprising:
a first circuit board unit having a bottom surface formed with a first die-receiving cavity, a top surface formed with a first bore to access said first die-receiving cavity and further formed with a plurality of first contact pads, and a plurality of first electroplated holes that are registered respectively with said first contact pads and that extend through said bottom surface of said first circuit board unit;
a first die having an upper surface provided with a plurality of first solder pads, said first die being placed in said first die-receiving cavity such that said first solder pads on said first die are exposed via said first bore in said first circuit board unit;
a plurality of first conductive wires that extend through said first bore and that wire-bond said first solder pads to said first contact pads;
a lead frame placed below said first circuit board unit, said lead frame having a plurality of leads;
a first conductive contact layer to bond said leads on said lead frame onto said first electroplated holes to establish electrical connection with corresponding ones of said first contact pads; and
a plastic protective layer to encapsulate said first circuit board unit and at least a portion of said lead frame.
52. The integrated circuit chip of
claim 51
, wherein said conductive contact layer is formed from a silver epoxy.
53. The integrated circuit chip of
claim 51
, wherein said conductive contact layer is formed from solder paste.
54. The integrated circuit chip of
claim 51
, further comprising:
a second circuit board unit having a bottom surface formed with a second die-receiving cavity, a top surface formed with a second bore to access said second die-receiving cavity and further formed with a plurality of second contact pads, and a plurality of second electroplated holes that are registered respectively with said second contact pads and that extend through said bottom surface of said second circuit board unit, said lead frame being disposed between said first and second circuit board units;
a second die having an upper surface provided with a plurality of second solder pads, said second die being placed in said second die-receiving cavity such that said second solder pads are exposed via said second bore in said second circuit board unit;
a plurality of second conductive wires that extend through said second bore and that wire-bond said second solder pads to said second contact pads; and
a second conductive contact layer to bond said leads on said lead frame onto said second electroplated holes to establish electrical connection with corresponding ones of said second contact pads.
55. An integrated circuit chip comprising:
a first circuit board unit having a top surface formed with a first die-receiving cavity and a plurality of first contact pads, and a plurality of first electroplated holes that are registered respectively with said first contact pads and that extend through a bottom surface of said first circuit board unit;
a first die having an upper surface provided with a plurality of first solder pads, said first die being placed in said first die-receiving cavity such that said first solder pads are exposed from said first die-receiving cavity;
a plurality of first conductive wires that wire-bond said first solder pads to said first contact pads;
a lead frame placed below said first circuit board unit, said lead frame having a plurality of leads;
a first conductive layer to bond said leads on said lead frame onto said first electroplated holes to establish electrical connection with corresponding ones of said first contact pads; and
a plastic protective layer to encapsulate said first circuit board unit and at least a portion of said lead frame.
56. The integrated circuit chip of
claim 55
, wherein said conductive contact layer is formed from a silver epoxy.
57. The integrated circuit chip of
claim 55
, wherein said conductive contact layer is formed from solder paste.
58. The integrated circuit chip of
claim 55
, further comprising:
a second circuit board unit having a top surface formed with a second die-receiving cavity and a plurality of second contact pads, and a plurality of second electroplated holes that are registered respectively with said second contact pads and that extend through a bottom surface of said second circuit board unit, said lead frame being disposed between said first and second circuit board units;
a second die having an upper surface provided with a plurality of second solder pads, said second die being placed in said second die-receiving cavity such that said second solder pads are exposed from said second die-receiving cavity;
a plurality of second conductive wires to wire-bond said second solder pads to said second contact pads; and
a second conductive contact layer to bond said leads on said lead frame onto said second electroplated holes to establish electrical connection with corresponding ones of said second contact pads.
59. An integrated circuit chip comprising:
a circuit board unit having a bottom surface formed with a die-receiving cavity, a top surface formed with a bore to access said die-receiving cavity and further formed with a plurality of contact pads, and opposite side portions formed with a plurality of positioning notches that correspond respectively to said contact pads;
a die having an upper surface provided with a plurality of solder pads, said die being placed in said die-receiving cavity such that said solder pads are exposed via said bore in said circuit board unit;
a plurality of conductive wires that extend through said bore and that wire-bond said solder pads to said contact pads;
a lead frame having a plurality of leads, one end of each of said leads being inserted into a respective one of said positioning notches;
a conductive contact layer to bond said leads on said lead frame onto corresponding ones of said contact pads adjacent to said side portions of said circuit board unit; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
60. The integrated circuit chip of
claim 59
, wherein said conductive contact layer is formed from a silver epoxy.
61. The integrated circuit chip of
claim 59
, wherein said conductive contact layer is formed from solder paste.
62. An integrated circuit chip comprising:
a circuit board unit having a top surface formed with a die-receiving cavity and a plurality of contact pads, and opposite side portions formed with a plurality of positioning notches that correspond respectively to said contact pads;
a die having an upper surface provided with a plurality of solder pads, said die being placed in said die-receiving cavity such that said solder pads on said die are exposed from said die-receiving cavity;
a plurality of conductive wires that wire-bond said solder pads to said contact pads;
a lead frame having a plurality of leads, one end of each of said leads being inserted into a respective one of said positioning notches;
a conductive contact layer to bond said leads on said lead frame onto corresponding ones of said contact pads adjacent to said opposite side portions of said circuit board unit; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
63. The integrated circuit chip of
claim 62
, wherein said conductive contact layer is formed from a silver epoxy.
64. The integrated circuit chip of
claim 62
, wherein said conductive contact layer is formed from solder paste.
65. An integrated circuit chip comprising:
a circuit board unit having a bottom surface formed with at least two die-receiving cavities, a top surface formed with at least two bores to access a respective one of said die-receiving cavities and further formed with a plurality of contact pads, and opposite side portions formed with a plurality of positioning notches that correspond respectively to said contact pads;
at least two dies, each having an upper surface provided with a plurality of solder pads, each of said dies being placed in a respective one of said die-receiving cavities such that said solder pads on each of said dies are exposed via a respective one of said bores in said circuit board unit;
a plurality of conductive wires that extend through said bores and that wire-bond said solder pads to said contact pads;
a lead frame having a plurality of leads, one end of each of said leads being inserted into a respective one of said positioning notches;
a conductive contact layer to bond said leads on said lead frame onto corresponding ones of said contact pads adjacent to said side portions of said circuit board unit; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
66. The integrated circuit chip of
claim 65
, wherein said conductive contact layer is formed from a silver epoxy.
67. The integrated circuit chip of
claim 65
, wherein said conductive contact layer is formed from solder paste.
68. An integrated circuit chip comprising:
a circuit board unit having a top surface formed with at least two die-receiving cavities and a plurality of contact pads, and opposite side portions formed with a plurality of positioning notches that correspond respectively to said contact pads;
at least two dies, each having an upper surface provided with a plurality of solder pads, each of said dies being placed in a respective one of said die-receiving cavities such that said solder pads on each of said dies are exposed from the respective one of said die-receiving cavities;
a plurality of conductive wires that wire-bond said solder pads to said contact pads;
a lead frame having a plurality of leads, one end of each of said leads being inserted into a respective one of said positioning notches;
a conductive contact layer to bond said leads on said lead frame onto corresponding ones of said contact pads adjacent to said opposite side portions of said circuit board unit; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
69. The integrated circuit chip of
claim 68
, wherein said conductive contact layer is formed from a silver epoxy.
70. The integrated circuit chip of
claim 68
, wherein said conductive contact layer is formed from solder paste.
71. A method of fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with a bore, and a plurality of contact pads on a top surface of the circuit board unit;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) attaching the die onto a bottom surface of the circuit board unit such that the solder pads on the die are exposed via the bore in the circuit board unit;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires that extend through the bore;
(e) placing a lead frame on top of the circuit board unit, and bonding leads on the lead frame onto corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
72. The method of
claim 71
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
73. The method of
claim 71
, wherein the conductive contact layer used in step (e) is formed from solder paste.
74. A method of fabricating an integrated circuit chip, comprising:
(a) forming a first circuit board unit with a first bore, a plurality of first contact pads on a top surface of the first circuit board unit, and a plurality of first electroplated holes that are registered respectively with the first contact pads and that extend through a bottom surface of the first circuit board unit;
(b) forming a first die having an upper surface provided with a plurality of first solder pads;
(c) attaching the first die onto the bottom surface of the first circuit board unit such that the first solder pads are exposed via the first bore in the first circuit board unit;
(d) wire-bonding the first solder pads to the first contact pads by means of first conductive wires that extend through the first bore;
(e) placing a lead frame below the first circuit board unit, and bonding leads on the lead frame onto the first electroplated holes to establish electrical connection with corresponding ones of the first contact pads via a first conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the first circuit board unit and at least a portion of the lead frame.
75. The method of
claim 74
, wherein the first conductive contact layer used in step (e) is formed from a silver epoxy.
76. The method of
claim 74
, wherein the first conductive contact layer used in step (e) is formed from solder paste.
77. The method of
claim 74
, further comprising, prior to step (f):
forming a second circuit board unit with a second bore, a plurality of second contact pads on a top surface of the second circuit board unit, and a plurality of second electroplated holes that are registered respectively with the second contact pads and that extend through a bottom surface of the second circuit board unit;
forming a second die having an upper surface provided with a plurality of second solder pads;
attaching the second die onto the bottom surface of the second circuit board unit such that the second solder pads are exposed via the second bore in the second circuit board unit;
wire-bonding the second solder pads to the second contact pads by means of second conductive wires that extend through the second bore; and
with the lead frame between the first and second circuit board units, bonding the leads on the lead frame onto the second electroplated holes to establish electrical connection with corresponding ones of the second contact pads via a second conductive contact layer.
78. A method of fabricating an integrated circuit chip, comprising:
(a) forming a circuit board unit with a bore, a plurality of contact pads on a top surface of the circuit board unit, and a plurality of positioning notches that are disposed on opposite side portions of the circuit board unit And that correspond respectively to the contact pads;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) attaching the die onto a bottom surface of the circuit board unit such that the solder pads on the die are exposed via the bore in the circuit board unit;
(d) wire-bonding the solder pads to the contact pads by means of conductive wires that extend through the bore;
(e) inserting one end of each of a plurality of leads of a lead frame into a respective one of the positioning notches, and bonding the leads on the lead frame onto corresponding ones of the contact pads adjacent to the opposite side portions of the circuit board unit via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
79. The method of
claim 78
, wherein the conductive contact layer used in step (e) is formed from a silver epoxy.
80. The method of
claim 78
, wherein the conductive contact layer used in step (e) is formed from solder paste.
81. An integrated circuit chip comprising:
a circuit board unit having a top surface formed with a bore and a plurality of contact pads;
a die having an upper surface provided with a plurality of solder pads, said die being attached to a bottom surface of said circuit board unit such that said solder pads on said die are exposed via said bore in said circuit board unit;
a plurality of conductive wires that extend through said bore and that wire-bond said solder pads to said contact pads;
a lead frame placed on top of said circuit board unit, said lead frame having a plurality of leads;
a conductive contact layer that bonds said leads on said lead frame onto corresponding ones of said contact pads; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
82. The integrated circuit chip of
claim 81
, wherein said conductive contact layer is formed from a silver epoxy.
83. The integrated circuit chip of
claim 81
, wherein said conductive contact layer is formed from solder paste.
84. An integrated circuit chip, comprising:
a first circuit board unit having a first bore, a top surface formed with a plurality of first contact pads, and a plurality of first electroplated holes that are registered respectively with said first contact pads and that extend through a bottom surface of said first circuit board unit;
a first die having an upper surface provided with a plurality of first solder pads, said first die being attached onto the bottom surface of said first circuit board unit such that said first solder pads are exposed via said first bore in said first circuit board unit;
a plurality of first conductive wires that extend through said first bore and that wire-bond said first solder pads to said first contact pads;
a lead frame placed below said first circuit board unit, said lead frame having a plurality of leads;
a first conductive contact layer to bond said leads on said lead frame onto said first electroplated holes to establish electrical connection with corresponding ones of said first contact pads; and
a plastic protective layer to encapsulate said first circuit board unit and at least a portion of said lead frame.
85. The integrated circuit chip of
claim 84
, wherein said first conductive contact layer is formed from a silver epoxy.
86. The integrated circuit chip of
claim 84
, wherein said first conductive contact layer is formed from solder paste.
87. The integrated circuit chip of
claim 84
, further comprising:
a second circuit board unit having a second bore, a top surface formed with a plurality of second contact pads, and a plurality of second electroplated holes that are registered respectively with said second contact pads and that extend through a bottom surface of said second circuit board unit, said lead frame being disposed between said first and second circuit board units;
a second die having an upper surface provided with a plurality of second solder pads, said second die being attached onto the bottom surface of said second circuit board unit such that said second solder pads are exposed via said second bore in said second circuit board unit;
a plurality of second conductive wires that extend through said second bore and that wire-bond said second solder pads to said second contact pads; and
a second conductive contact layer to bond said leads on said lead frame onto said second electroplated holes to establish electrical connection with corresponding ones of said second contact pads.
88. An integrated circuit chip comprising:
a circuit board unit having a bore, a top surface formed with a plurality of contact pads, and opposite side portions formed with a plurality of positioning notches that correspond respectively to said contact pads;
a die having an upper surface provided with a plurality of solder pads, said die being attached onto a bottom surface of said circuit board unit such that said solder pads on said die are exposed via said bore in said circuit board unit;
a plurality of conductive wires that extend through said bore and that wire-bond said solder pads to said contact pads;
a lead frame having a plurality of leads, one end of each of said leads being inserted into a respective one of said positioning notches;
a conductive contact layer that bonds said leads on said lead frame onto corresponding ones of said contact pads adjacent to said opposite side portions of said circuit board unit; and
a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
89. The integrated circuit chip of
claim 88
, wherein said conductive contact layer is formed from a silver epoxy.
90. The integrated circuit chip of
claim 88
, wherein said conductive contact layer is formed from solder paste.
US09/791,137 1998-10-27 2001-02-22 Integrated circuit chip and method for fabricating the same Expired - Fee Related US6429535B2 (en)

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TW087117753A TW368707B (en) 1998-10-27 1998-10-27 Packaging method for semiconductor die and the product of the same
TW87117753U 1998-10-27
US09/303,142 US6271586B1 (en) 1998-10-27 1999-04-30 Integrated circuit chip and method for fabricating the same
US09/791,137 US6429535B2 (en) 1998-10-27 2001-02-22 Integrated circuit chip and method for fabricating the same

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US09/791,076 Expired - Lifetime US6670707B2 (en) 1998-10-27 2001-02-22 Integrated circuit chip
US09/791,082 Abandoned US20010005038A1 (en) 1998-10-27 2001-02-22 Integrated circuit chip and method for fabricating the same
US09/791,077 Expired - Fee Related US6429514B2 (en) 1998-10-27 2001-02-22 Integrated circuit chip and method for fabricating the same
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US09/791,082 Abandoned US20010005038A1 (en) 1998-10-27 2001-02-22 Integrated circuit chip and method for fabricating the same
US09/791,077 Expired - Fee Related US6429514B2 (en) 1998-10-27 2001-02-22 Integrated circuit chip and method for fabricating the same
US09/791,094 Expired - Lifetime US6534344B2 (en) 1998-10-27 2001-02-22 Integrated circuit chip and method for fabricating the same

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JP (1) JP3025685B1 (en)
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TW368707B (en) 1999-09-01
US6429514B2 (en) 2002-08-06
US20010008307A1 (en) 2001-07-19
US20010008308A1 (en) 2001-07-19
US6670707B2 (en) 2003-12-30
JP2000133673A (en) 2000-05-12
US20010005038A1 (en) 2001-06-28
JP3025685B1 (en) 2000-03-27
US6271586B1 (en) 2001-08-07
DE19929606A1 (en) 2000-05-11
US6429535B2 (en) 2002-08-06
US20010007782A1 (en) 2001-07-12

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