US20010009300A1 - Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element - Google Patents
Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element Download PDFInfo
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- US20010009300A1 US20010009300A1 US09/803,027 US80302701A US2001009300A1 US 20010009300 A1 US20010009300 A1 US 20010009300A1 US 80302701 A US80302701 A US 80302701A US 2001009300 A1 US2001009300 A1 US 2001009300A1
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- external connection
- connection terminals
- semiconductor
- semiconductor element
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 168
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 230000003287 optical effect Effects 0.000 claims abstract description 113
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000005259 measurement Methods 0.000 claims abstract description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 claims description 10
- 238000005538 encapsulation Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 238000003384 imaging method Methods 0.000 abstract description 5
- 239000007787 solid Substances 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 16
- 230000001070 adhesive effect Effects 0.000 description 11
- 239000000126 substance Substances 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 9
- 238000005549 size reduction Methods 0.000 description 7
- 238000012360 testing method Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 206010040844 Skin exfoliation Diseases 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/0554—External layer
- H01L2224/0555—Shape
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- H01L2224/05554—Shape in top view being square
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/484—Connecting portions
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- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01079—Gold [Au]
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the present invention relates to a semiconductor element having external connection terminals, a method of manufacturing the semiconductor element, and a semiconductor device equipped with the semiconductor elements and, more particularly, a semiconductor element, a method of manufacturing the semiconductor element, and a semiconductor device, capable of reducing a placement area of external connection terminals on an integrated circuit mounting surface.
- a semiconductor device comprises a semiconductor element and a package in which the semiconductor device is mounted.
- external connection terminals electrodes
- Lead wirings are provided on the package.
- the external connection terminals of the semiconductor element and the lead wirings are electrically connected indirectly via wires formed by means of wire bonding technique or directly by wireless bonding technique.
- an optical element 1 such as an image sensor, a solid state imaging device, etc. in the prior art includes at least a photo detector 3 and external connection terminals 5 disposed in the neighboring area of the photo detector 3 on its surface.
- the photo detector 3 can execute so-called photoelectric conversion to convert optical signals into electric signals.
- peripheral circuits such as a CCD (Charge Coupled Device) which can transfer sequentially the electric signals derived by photoelectric conversion by use of the photo detector 3 are disposed around the photo detector 3 .
- the external connection terminals 5 connect electrically the photo detector 3 and the external device (not shown).
- an optical device 10 comprise the optical element 1 and a package 12 in which the optical element 1 is mounted.
- a glass lid 14 which is able to transmit the optical signals is provided on the package 12 .
- the optical device 10 can be hermetic-sealed by the glass lid 14 and the package 12 .
- the lead wirings 13 are formed in the outer periphery of the optical element 1 on the package 12 .
- the external connection terminals 5 of the optical element 1 and the lead wirings 13 are connected electrically by bonding wires 9 .
- the optical element 1 is bonded to the package 12 by die bonding technique.
- FIG. 15 is a sectional view showing the wire bonding which is now applied to the optical element.
- the bonding wire 9 is pushed against the external connection terminal 5 by use of a capillary 15 and then bonded to the external connection terminal 5 in terms of ultrasonic vibration.
- the external connection terminals 5 are disposed closer to each other and in addition the photo detector 3 and the external connection terminal 5 are disposed closer to each other.
- the capillary 15 does not abut upon the external connection terminal 5 exactly, but upon a protection film coated on the surface of the optical element 1 . Therefore, there has been caused another disadvantage that a part of the protection film is peeled off and then such peeled films also fall to the photo detector 3 and then stick thereto as adhesive substance 16 .
- FIG. 16(A) in the case that, for example, the adhesive substance 16 falls to a pixel 3 c out of a plurality of pixels 3 a to 3 e constituting the photo detector 3 , there are some cases where a white level signal which should be output properly from the pixel 3 c is converted into a black level signal, as shown in FIG. 16(B), when a light is incident into the photo detector 3 . As a consequence, proper signal output values cannot be output from the photo detector 3 .
- FIG. 17 is a view showing a configuration of the semiconductor element 1 a in the prior art.
- the external connection terminals 5 are disposed on side surfaces of the semiconductor element 1 a , so that an occupied area of the external connection terminals 5 on a surface of the semiconductor element 1 a can be reduced, which results in reduction in the surface area of the semiconductor element 1 a .
- the external connection terminals 5 can be formed on the side surfaces of the semiconductor element 1 a , but the electrical measuring electrodes 17 used to execute the electrical measurement of the integrated circuit in the course of production process (wafer process) is required separately.
- the electrical measuring electrodes 17 are arranged on the surface of the semiconductor element 1 a as the integrated circuit mounting surface.
- the electrical measuring electrodes 17 and the external connection terminals 5 are connected electrically by the wirings 18 respectively, so that the external connection terminals 5 are connected electrically to the not shown integrated circuit in the semiconductor element 1 a via the wirings 18 and the electrical measuring electrodes 17 respectively.
- the electrical measuring electrodes 17 as well as the photo detector 3 are arranged on the surface of the optical element 1 and the external connection terminals 5 are arranged on the side surfaces of the optical element 1 .
- the occupied areas of the electrical measuring electrodes 17 are small rather than those of the external connection terminals 5 .
- the occupied areas of the electrical measuring electrodes 17 are not so small as they can be neglected. For this reason, the element area of the optical element 1 cannot be sufficiently reduced because the electrical measuring electrodes 17 are required substantially as many as the external connection terminals 5 .
- the increase in the element area of the optical element 1 results in an increase in size of the package 12 and therefore the optical device 10 is enlarged in size.
- the present invention has been made to overcome the above problems, and it is an object of the present invention to provide a semiconductor element capable of reducing an element area by reducing occupied areas of external connection terminals and electrical measuring electrodes used only in production processes. More particularly, it is an object of the present invention to provide an optical element capable of reducing an element area and also preventing degradation in characteristics due to adhesive substance being generated upon bonding.
- a semiconductor element comprising wirings formed on an integrated circuit mounting surface of a semiconductor chip to extend from an integrated circuit to end portions of the semiconductor chip; and external connection terminals connected to the wirings so as to connect electrically the integrated circuit and an external device arranged on an outside of the semiconductor chip, at least bonding areas of the external connection terminals being disposed only on side surfaces, a back surface, or both the side surfaces and the back surface of the semiconductor chip.
- the wirings are disconnected from electrical measuring electrodes which are formed on dicing lines and then connected to the external connection terminals.
- the wirings being extended up to an end portion of the semiconductor chip and the external connection terminals are connected electrically by terminal wiring connection members which are formed integrally with the external connection terminals and are extended from the side surface or the back surface of the semiconductor chip to the integrated circuit mounting surface respectively.
- the external connection terminals and the terminal wiring connection members are formed of same conductive plate material respectively.
- the wirings being extended up to an end portion of the semiconductor chip and the external connection terminals are connected electrically by terminal wiring connection members which are formed of material different from those of the external connection terminals and the wirings ,and are extended from the side surface or the back surface of the semiconductor chip to the integrated circuit mounting surface respectively.
- the external connection terminals are formed of either gold bump electrodes or electrodes which are formed with use of a TAB (Tape Automated Bonding) technique.
- the external connection terminals are disposed on the side surfaces or the back surface of the semiconductor chip via an insulator.
- the semiconductor element further comprises a CCD (Charge Coupled Device) provided in the integrated circuit.
- the external connection terminals are disposed only on the side surfaces, the back surface, or both the side surfaces and the back surface of the semiconductor chip.
- at least bonding areas of the external connection terminals are disposed only on side surfaces, a back surface, or both the side surfaces and the back surface of the semiconductor chip.
- the electrical measuring electrodes used to measure electric characteristics of the integrated circuit are disposed on the dicing lines to be connected to the wirings, and then removed by dicing process after the electrical measurement (characteristic evaluation test) has been completed, so that the electrical measuring electrodes are disconnected from the wirings.
- the external connection terminals are connected electrically to the wirings from which the electrical measuring electrodes have been disconnected.
- the external connection terminals can be formed on the side surfaces or the back surface of the semiconductor chip.
- the integrated circuit and the wirings are formed on the integrated circuit mounting surface of the semiconductor element, but the electrical measuring electrodes are not formed on the integrated circuit mounting surface of the semiconductor element. For this reason, the element surface area of the semiconductor element can be reduced.
- the semiconductor element consists of the optical element which has the photo detector and the CCD in the integrated circuit
- the photo detector and the external connection terminals can be formed on different surfaces of the semiconductor element respectively and therefore adhesive substance which is generated upon bonding and dropped down onto the photo detector can be lessened. For this reason, degradation in characteristics of the photo detector due to such adhesive substance can be prevented while reducing the element area.
- the wirings and the external connection terminals can be connected simply by the terminal wiring connection members.
- a method of manufacturing a semiconductor element comprising the steps of forming, on a surface of a semiconductor wafer, a plurality of semiconductor elements having integrated circuits therein respectively, electrical measuring electrodes arranged on dicing lines between the semiconductor elements, for measuring electric characteristics of each integrated circuit in each semiconductor element, and wirings for connecting electrically the integrated circuits and the electrical measuring electrodes; executing electrical measurement of the integrated circuits provided in the semiconductor elements by use of the electrical measuring electrodes; dividing the semiconductor wafer into individual semiconductor elements along the dicing lines and simultaneously removing the electrical measuring electrodes from the semiconductor elements; and forming external connection terminals on side surfaces or a back surface or both the side surfaces and the back surface of the semiconductor element to be electrically connected to the wirings from which the electrical measuring electrodes are removed.
- the semiconductor element comprises the photo detectors and CCD in the integrated circuit
- the semiconductor element can be formed which enables reduction in the element area.
- the semiconductor element can also be formed which can prevent degradation in characteristics while reducing the element area. Since the electrical measuring electrodes can be removed at the same time dicing process is executed, the number of production process can be reduced by eliminating an individual step of removing the electrical measuring electrodes.
- a semiconductor device on which a semiconductor element is mounted comprising a semiconductor element including the above integrated circuit, wirings, and external connection terminals; and an encapsulation package having lead wirings connected electrically to the external connection terminals of the semiconductor element thereon, the semiconductor element being mounted in the encapsulation package.
- the semiconductor element comprises the photo detectors and CCD in the integrated circuits.
- the external connection terminals of the semiconductor element are connected electrically to the lead wirings of the encapsulation package by direct contact or via wires.
- the semiconductor element includes a photo detector and a CCD in the integrated circuit
- the encapsulation package includes a light transmission glass provided on the photo detector to transmit optical signals, and is made of a ceramic package with high moisture resistance.
- the element area of the semiconductor element can be reduced as stated above, a size reduction of the encapsulation package can be implemented so that a size reduction of the semiconductor device can be achieved.
- the optical device can be provided which enables a size reduction.
- FIG. 1 is a perspective view showing a semiconductor element according to a first embodiment of the present invention
- FIG. 2 is a sectional view showing the semiconductor element shown in FIG. 1;
- FIG. 3(A) is a plan view showing a semiconductor wafer used to explain a method of manufacturing the semiconductor element shown in FIG. 1;
- FIG. 3(B) is an enlarged plan view showing a pertinent portion of the semiconductor wafer shown in FIG. 3(A), which is now subjected to electrical measurement;
- FIG. 4(A) is a plan view showing the semiconductor wafer shown in FIG. 3(A), which has undergone the dicing process;
- FIG. 4(B) is a perspective view showing a semiconductor element which is separated from the semiconductor wafer shown in FIG. 4(A) by the dicing process;
- FIG. 5(A) is an enlarged perspective view showing the semiconductor element according to the first embodiment of the present invention, on which external connection terminals have been formed;
- FIG. 5(B) is an enlarged perspective view showing the semiconductor element according to a modification of the first embodiment of the present invention, on which another external connection terminals have been formed;
- FIG. 5(C) is an enlarged perspective view showing the semiconductor element according to another modification of the first embodiment of the present invention, on which still another external connection terminals have been formed;
- FIG. 6 is a sectional view showing a semiconductor device in which the semiconductor element shown in FIG. 1 is mounted;
- FIG. 7 is a perspective view showing a semiconductor element according to a second embodiment of the present invention.
- FIG. 8 is a sectional view showing the semiconductor element shown in FIG. 7;
- FIG. 9 is an enlarged perspective view showing the semiconductor element shown in FIG. 7;
- FIG. 10 is a sectional view showing another semiconductor device in which the semiconductor element shown in FIG. 7 is mounted;
- FIG. 11 is a sectional view showing still another semiconductor device in which the semiconductor element shown in FIG. 7 is mounted;
- FIG. 12 is a perspective view showing an optical element as a semiconductor element in the prior art
- FIG. 13 is a sectional view showing an optical device in the prior art on which the optical element in FIG. 12 is mounted;
- FIG. 14 is an enlarged sectional view showing a pertinent portion of the optical device shown in FIG. 13;
- FIG. 15 is a fragmental sectional view showing the optical device shown in FIG. 13, which is now being subjected to wire bonding;
- FIG. 16(A) is a fragmental plan view showing the optical element in the prior art
- FIG. 16(B) is a view showing output signal values which are output from the optical element in the prior art
- FIG. 17 is a perspective view showing a semiconductor element in the prior art.
- FIG. 18 is an enlarged sectional view showing a pertinent portion of the optical device in the prior art.
- an optical element (semiconductor element) 20 to be mounted on an optical device ( 30 , described later) comprises an integrated circuit 21 , wirings 23 , and external connection terminals (electrodes) 25 .
- the optical element 20 is formed of a semiconductor chip made of a single crystal silicon substrate.
- An integrated circuit 21 and the wirings 23 are disposed on an integrated circuit mounting surface of the semiconductor chip.
- the integrated circuit 21 comprises a photo detector 22 , and peripheral circuits such as CCD, driver circuit, signal detector circuit, etc. disposed around the photo detector 22 , though not shown.
- the photo detector 22 is composed of pixels made up of a plurality of photodiodes, etc. which are aligned in one or two-dimensional fashion. The pixels can convert optical signals into electric signals by means of photoelectric conversion.
- the CCD as the peripheral circuit can transmit sequentially the electric signals derived by the photo detector 22 .
- the driver circuit can select predetermined pixels of the photo detector 22 .
- the signal detector circuits can detect the electric signals derived from the pixels.
- the optical element 20 is composed as a one-line-dimensional image sensor, a two-area-dimensional image sensor, a solid state imaging device, or the like.
- the wirings 23 are formed around the integrated circuit 21 to extend from the integrated circuit 21 to end portions of the integrated circuit mounting surface.
- respective wirings 23 are extended on the integrated circuit mounting surface to reach the edge of the side surface of the semiconductor chip.
- the wirings 23 are electrically connected to the external connection terminals 25 in one-by-one correspondence and are then connected electrically to an external device via the external connection terminals 25 .
- control signals for the image sensor or the solid state imaging device are input from the external device to the integrated circuit 21 via the external connection terminals 25 and the wirings 23 respectively.
- image information or picture information are output from the integrated circuit 21 to the external device.
- the wirings 23 are also used as test wires which transmit various signals obtained by electrical measurement (characteristic evaluation test) carried out in the course of production process.
- the external connection terminals 25 are connected electrically to the wirings 23 and thus used as terminals which connect electrically the wirings 23 and the external device.
- the external connection terminals 25 are aligned only on the side surfaces of the semiconductor chip which are different from the integrated circuit mounting surface of the semiconductor chip.
- the optical elements 20 , the wirings 23 , and the electrical measuring electrodes 23 T are formed on the surface of the semiconductor wafer 28 which is made of a single crystal silicon substrate.
- a plurality of optical elements 20 are aligned regularly, and all adjacent optical elements 20 are formed integrally with each other in this stage.
- the electrical measuring electrodes 23 T are formed on dicing lines (scribe areas) 29 between the optical elements 20 .
- the wirings 23 are formed to extend from the integrated circuit 21 on the optical element 20 to the electrical measuring electrodes 23 T so as to connect electrically the integrated circuit 21 and the electrical measuring electrodes 23 T.
- the wirings 23 can be formed by a manufacturing step identical to that used for the wirings which connect respective elements or circuits in the integrated circuit 21 . It is preferable that the wirings 23 and the electrical measuring electrodes 23 T are formed by the same wiring layer to reduce the number of production steps.
- the wirings 23 may be made of either a single-layer film such as aluminum thin film, aluminum alloy thin film, copper thin film, copper alloy thin film, etc. or a laminated film which is formed mainly of these thin films.
- the electrical measurement (probe test) of the integrated circuit 21 of the optical element 20 is executed with the use of the electrical measuring electrodes 23 T.
- the electrical measurement is carried out when the optical element 20 is still in its wafer state, and the selection whether the optical element 20 is good or bad can be implemented by such electrical measurement. If such quality selection of the optical elements 20 can be accomplished in their wafer state, there is no necessity of selecting the quality of every optical element 20 after a plurality of optical elements 20 have been separated from one sheet of semiconductor wafer 28 by the dicing process, and therefore wasteful packaging of defective optical elements 20 can be avoided. Accordingly, in order to carry out the electrical measurement of optical elements 20 in their wafer state, the electrical measuring electrodes 23 T must be formed on the surface of the semi-conductor wafer 28 before the dicing process is executed.
- the electrical measurement is carried out by bring the probe stylus 40 connected to a tester (not shown) into contact with the electrical measuring electrodes 23 T so as to transmit test signals from the tester to the integrated circuit 21 via the probe stylus 40 , the electrical measuring electrodes 23 T, and the wirings 23 respectively.
- the semiconductor wafer 28 is divided into a plurality of individual optical elements 20 by the dicing process on the dicing lines 29 .
- dicing process is carried out by cutting the dicing lines 29 of the semiconductor wafer 28 by a thin diamond grinding wheel (dicing saw) which is rotated at high speed.
- the semiconductor wafer 28 is divided into the plurality of optical elements 20 and at the same time the electrical measuring electrodes 23 T formed on the surfaces of the dicing lines 29 are disconnected from the wirings 23 to be removed from respective optical elements 20 .
- FIG. 4(B) the optical element 20 without the electrical measuring electrodes 23 T can be formed.
- the external connection terminals 25 are fitted to the side surfaces of the optical element 20 to be connected electrically to the wirings 23 .
- a terminal wiring connection member 25 a formed like an L-shape which is brought into tight contact with the side surface and the integrated circuit mounting surface of the optical element 20 respectively is formed integrally with the external connection terminal 25 .
- the terminal wiring connection members 25 a are formed to be extended from the external connection terminals 25 .
- the terminal wiring connection members 25 a which are formed integrally with the external connection terminals 25 may be extended onto the integrated circuit mounting surface of the optical device 20 .
- the external connection terminals 25 and the terminal wiring connection members 25 a are made of conductive plate material such as copper plate or gold plate, for example.
- the terminal wiring connection members 25 a are formed by machining, for example.
- the terminal wiring connection members 25 a formed as above are able to connect easily the external connection terminals 25 and the wirings 23 .
- the external connection terminals 25 are fitted to the side surface of the optical element 20 via an insulating film 26 respectively.
- a resin film having adhesive property such as epoxy resin film, polyimide resin film, etc. may be employed as the insulating film 26 .
- the terminal wiring connection members 25 a which are formed integrally with the external connection terminals 25 and folded to the integrated circuit mounting surface side come directly into contact with the wiring 23 . In such contacting area, the wiring 23 is exposed from a protection film 24 .
- the protection film 24 covers a substantially whole area of the integrated circuit mounting surface of the optical element 20 such as the integrated circuit 21 , the wirings 23 , etc.
- any of gold bump electrodes (projection electrodes) 25 B shown in FIG. 5(B) and TAB electrodes 25 T formed by a TAB (Tape Automated Bonding) technique shown in FIG. 5(C) may be employed as the external connection terminal 25 .
- the gold bump electrodes 25 B shown in FIG. 5(B) are formed by bonding gold balls on a surface of the insulating film 26 with the use of a bump bonder like the wire bonder.
- the gold balls per se can be used as the external connection terminal 25 .
- Such gold ball is formed by heating a top end of the gold wire and then working the heated top end into a ball shape.
- a rear end side of the gold wire is used as a terminal wiring connection member 25 B a which is bonded to the wiring 23 . If the gold bump electrode 25 B is used as the external connection terminal 25 , such material that has high junction property with gold is formed at least on an uppermost layer of the insulating film 26 .
- the TAB electrodes 25 T formed by the TAB technique shown in FIG. 5(C) are formed on a surface of the tape type insulating film 26 having adhesive property.
- the TAB electrodes 25 T and the wirings 23 are connected electrically via terminal wiring connection members 25 T a which are extended from the side surfaces to the integrated circuit mounting surface of the optical element 20 .
- a polyimide resin tape may be used as the insulating film 26
- the gold wire may be used as the terminal wiring connection member 25 T a .
- the gold wire can be bonded by the ordinary wire bonding technique.
- the terminal wiring connection member 25 T a is formed of material different from those of the wiring 23 and the TAB electrodes 25 T.
- the optical element 20 is then packaged to thus complete an optical device 30 , as shown in FIG. 6.
- the optical device 30 comprises the optical element 20 and a package 31 which can hermetic-seal the optical element 20 therein.
- the package 31 includes a light transmission glass (glass lid or window) 33 over the photo detector 23 of the optical element 20 so as to input optical signals into the photo detector 23 .
- a light transmission glass glass lid or window
- borosilicate glass may be used as the light transmission glass 33 .
- a cavity in which the optical element 20 is placed is formed in the package 31 .
- Lead wirings 32 which are to be connected electrically to the external connection terminals 25 of the optical element 20 are formed on a surface of the cavity.
- the external connection terminals 25 of the optical element 20 are brought into contact directly with the lead wirings 32 by means of wireless bonding.
- wireless bonding For instance, solder may be employed to bond the external connection terminals 25 and the lead wirings 32 .
- the size reduction of the package 31 can be achieved since occupied area required for routing of the wires can be reduced.
- the package 31 may be formed by a ceramic package or a plastic package. If moisture resistance is required for the package, the ceramic package will be utilized. If cost of the package has to be suppressed lower, the plastic package will be utilized. Further, the lead wirings 23 may be formed of aluminum clad or copper clad, for example.
- the external connection terminals 25 are formed on the back surface of the optical element 20 . As shown in FIGS. 7 and 8, the external connection terminals 25 are arranged on the back surface of the semiconductor chip, i.e., the surface opposing to the integrated circuit mounting surface of the optical element 20 .
- terminal wiring connection members 25 a each formed like a C-shape which is brought into tight contact with the back surface, the side surface, and the integrated circuit mounting surface of the optical element 20 respectively so as to be extended from the back surface to the integrated circuit mounting surface via the side surface are formed integrally with the external connection terminals 25 .
- the terminal wiring connection members 25 a which are formed integrally with the external connection terminals 25 may be extended onto the integrated circuit mounting surface of the optical element 20 . Since a basic structure of the external connection terminal 25 is similar to that of the external connection terminal 25 in the above first embodiment, its explanation will be omitted in the second embodiment.
- the optical element 20 As shown in FIG. 10, the optical element 20 , on the back surface of which the external connection terminals 25 are aligned, is packaged in the package 31 , so that the optical device 30 is completed. On the bottom surface of the cavity of the package 31 are formed previously the lead wirings 32 which are connected, by means of wireless bonding, to the external connection terminals 25 which are formed on the back surface of the optical element 20 .
- the optical device 30 can be packaged by bringing the photo detector 22 previously into direct contact with the back surface of the light transmission glass 33 , then mounting the optical element 20 on the light transmission glass 33 , and then installing the optical element 20 in the package 31 .
- adhesion of foreign substance such as dust, etc. between the photo detector 22 for photoelectric conversion and the light transmission glass 33 can be prevented and therefore defects due to such adhesion of the foreign substance can be reduced.
- the optical element 20 in which the external connection terminals 25 are aligned on its back surface can be mounted directly on the back surface of the light transmission glass 33 which has the lead wirings 32 on its back surface.
- the external connection terminals 25 formed on the back surface of the optical element 20 and the lead wirings 32 formed on the back surface of the light transmission glass 33 are connected electrically by bonding wires 35 .
- size reduction can be implemented much more since the package 31 can be neglected.
- the external connection terminals 25 are arranged only on the side surfaces, the back surface, or both the side surfaces and the back surface of the optical element 20 .
- the electrical measuring electrodes 23 T used to measure electric characteristics of the integrated circuit 21 are arranged on the dicing lines 29 so as to be connected to the wirings 23 and then removed by dicing process after the electrical measurement has been completed, so that the electrical measuring electrodes 23 T are disconnected from the wirings 23 .
- the external connection terminals 25 are connected electrically to the wirings 23 from which the electrical measuring electrodes 23 T have been disconnected. Accordingly, the external connection terminals 25 can be formed on the side surfaces or the back surface of the optical element 20 .
- the semiconductor element consists of the optical element 20 which has the photo detector 22 and the CCD in the integrated circuit 21
- the photo detector 22 and the external connection terminals 25 can be formed on different surfaces of the optical element 20 respectively and as a result adhesive substance which is generated upon bonding and dropped down onto the photo detector 22 can be lessened. Therefore, degradation in characteristics of the photo detector 22 due to such adhesive substance can be prevented while reducing the element area.
- the number of production process can be reduced by eliminating an individual step of removing the electrical measuring electrodes 23 T since the electrical measuring electrodes 23 T can be removed at the same time when dicing process is executed.
- the element area of the optical element 20 can be reduced as stated above, a size reduction of the package 31 can be implemented so that a size reduction of the optical device 30 can be achieved.
- the present invention should be interpreted not to be limited to the above embodiments.
- the external connection terminals 25 may be provided previously to the lead wirings 32 of the package 31 in positions corresponding to the side surfaces, the back surface, or both the side surfaces and the back surface of the optical element 20 and then the external connection terminals 25 and the wirings 23 of the optical element 20 may be connected electrically. Otherwise, the lead wirings per se may be formed as the external connection terminals 25 .
- the present invention is not limited to the optical element 20 such as the image sensor, the solid state imaging device, etc.
- the present invention may be applied to other optical elements such as a photo detector without the CCD used in a photo coupler.
- the present invention may be applied to all semiconductor elements such as memory element, logical element, etc. According to the present invention, the semiconductor devices in which these semiconductor elements are mounted respectively can achieve the same advantages as those as described above.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor element having external connection terminals, a method of manufacturing the semiconductor element, and a semiconductor device equipped with the semiconductor elements and, more particularly, a semiconductor element, a method of manufacturing the semiconductor element, and a semiconductor device, capable of reducing a placement area of external connection terminals on an integrated circuit mounting surface.
- 2. Description of the Prior Art
- In general, a semiconductor device comprises a semiconductor element and a package in which the semiconductor device is mounted. On a surface of the semiconductor element are formed external connection terminals (electrodes) which connect electrically an integrated circuit formed on the semiconductor element to an external device placed on the outside of the package. Lead wirings are provided on the package. The external connection terminals of the semiconductor element and the lead wirings are electrically connected indirectly via wires formed by means of wire bonding technique or directly by wireless bonding technique.
- As shown in FIG. 12, an
optical element 1 such as an image sensor, a solid state imaging device, etc. in the prior art includes at least aphoto detector 3 andexternal connection terminals 5 disposed in the neighboring area of thephoto detector 3 on its surface. Thephoto detector 3 can execute so-called photoelectric conversion to convert optical signals into electric signals. Though not shown, peripheral circuits such as a CCD (Charge Coupled Device) which can transfer sequentially the electric signals derived by photoelectric conversion by use of thephoto detector 3 are disposed around thephoto detector 3. Theexternal connection terminals 5 connect electrically thephoto detector 3 and the external device (not shown). - As shown in FIG. 13, an
optical device 10 comprise theoptical element 1 and apackage 12 in which theoptical element 1 is mounted. Aglass lid 14 which is able to transmit the optical signals is provided on thepackage 12. Theoptical device 10 can be hermetic-sealed by theglass lid 14 and thepackage 12. - As shown in FIGS. 13 and 14, the
lead wirings 13 are formed in the outer periphery of theoptical element 1 on thepackage 12. In the case that the wire bonding is employed, theexternal connection terminals 5 of theoptical element 1 and thelead wirings 13 are connected electrically bybonding wires 9. Theoptical element 1 is bonded to thepackage 12 by die bonding technique. - With the high advance and complication of LSIs in recent years, there has been a tendency that the number of terminals required for the semiconductor element is increased. However, if the number of terminals are simply increased based on a layout rule for the external connection terminals on the semiconductor element in the prior art, an increase in an element area is brought about. In order to overcome this drawback, such a method can be considered that the increase in the element area should be avoided by reducing a distance between the external connection terminals respectively. In this case, the bonding technique with extremely high accuracy is requested since the distance between the external connection terminals must be narrowed rather than that in prior art.
- FIG. 15 is a sectional view showing the wire bonding which is now applied to the optical element. The
bonding wire 9 is pushed against theexternal connection terminal 5 by use of a capillary 15 and then bonded to theexternal connection terminal 5 in terms of ultrasonic vibration. However, in theoptical element 1 shown in FIG. 12, theexternal connection terminals 5 are disposed closer to each other and in addition thephoto detector 3 and theexternal connection terminal 5 are disposed closer to each other. As a result, there has been caused such a disadvantage that a part of a surface of theexternal connection terminal 5 is peeled off upon bonding and then such peelings fall to thephoto detector 3 and then stick thereto asadhesive substance 16. In addition, unless enough bonding accuracy can be achieved, thecapillary 15 does not abut upon theexternal connection terminal 5 exactly, but upon a protection film coated on the surface of theoptical element 1. Therefore, there has been caused another disadvantage that a part of the protection film is peeled off and then such peeled films also fall to thephoto detector 3 and then stick thereto asadhesive substance 16. - As shown in FIG. 16(A), in the case that, for example, the
adhesive substance 16 falls to apixel 3 c out of a plurality ofpixels 3 a to 3 e constituting thephoto detector 3, there are some cases where a white level signal which should be output properly from thepixel 3 c is converted into a black level signal, as shown in FIG. 16(B), when a light is incident into thephoto detector 3. As a consequence, proper signal output values cannot be output from thephoto detector 3. - In order to overcome the above disadvantages, a semiconductor element set forth in Patent Application Publication (KOKAI) 3-104246 has been proposed. FIG. 17 is a view showing a configuration of the
semiconductor element 1 a in the prior art. In thissemiconductor element 1 a, theexternal connection terminals 5 are disposed on side surfaces of thesemiconductor element 1 a, so that an occupied area of theexternal connection terminals 5 on a surface of thesemiconductor element 1 a can be reduced, which results in reduction in the surface area of thesemiconductor element 1 a. In addition, if the semiconductor element set forth in the above Patent Application Publication (KOKAI) 3-104246 is applied to the aboveoptical device 10, there has not been caused the disadvantage due to theadhesive substance 16 generated during wire bonding since thephoto detector 3 and theexternal connection terminals 5 of theoptical element 1 are formed on different surfaces of theoptical element 1, as shown in FIG. 18. - Nevertheless, in the
above semiconductor element 1 a shown in FIG. 17, theexternal connection terminals 5 can be formed on the side surfaces of thesemiconductor element 1 a, but theelectrical measuring electrodes 17 used to execute the electrical measurement of the integrated circuit in the course of production process (wafer process) is required separately. Theelectrical measuring electrodes 17 are arranged on the surface of thesemiconductor element 1 a as the integrated circuit mounting surface. Theelectrical measuring electrodes 17 and theexternal connection terminals 5 are connected electrically by thewirings 18 respectively, so that theexternal connection terminals 5 are connected electrically to the not shown integrated circuit in thesemiconductor element 1 a via thewirings 18 and theelectrical measuring electrodes 17 respectively. In theoptical device 10, theelectrical measuring electrodes 17 as well as thephoto detector 3 are arranged on the surface of theoptical element 1 and theexternal connection terminals 5 are arranged on the side surfaces of theoptical element 1. The occupied areas of theelectrical measuring electrodes 17 are small rather than those of theexternal connection terminals 5. However, the occupied areas of theelectrical measuring electrodes 17 are not so small as they can be neglected. For this reason, the element area of theoptical element 1 cannot be sufficiently reduced because theelectrical measuring electrodes 17 are required substantially as many as theexternal connection terminals 5. - In addition, the increase in the element area of the
optical element 1 results in an increase in size of thepackage 12 and therefore theoptical device 10 is enlarged in size. - The present invention has been made to overcome the above problems, and it is an object of the present invention to provide a semiconductor element capable of reducing an element area by reducing occupied areas of external connection terminals and electrical measuring electrodes used only in production processes. More particularly, it is an object of the present invention to provide an optical element capable of reducing an element area and also preventing degradation in characteristics due to adhesive substance being generated upon bonding.
- It is another object of the present invention to provide a method of manufacturing a semiconductor element and, more particularly, a method of manufacturing an optical element capable of reducing the number of production process while achieving reduction in the element area.
- It is still another object of the present invention to provide a semiconductor device capable of achieving reduction of the element area while reducing a size of a package to thus reduce a size of overall semiconductor device. More particularly, it is still another object of the present invention to provide an optical device capable of reducing a size of overall optical device.
- In order to achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor element comprising wirings formed on an integrated circuit mounting surface of a semiconductor chip to extend from an integrated circuit to end portions of the semiconductor chip; and external connection terminals connected to the wirings so as to connect electrically the integrated circuit and an external device arranged on an outside of the semiconductor chip, at least bonding areas of the external connection terminals being disposed only on side surfaces, a back surface, or both the side surfaces and the back surface of the semiconductor chip. The wirings are disconnected from electrical measuring electrodes which are formed on dicing lines and then connected to the external connection terminals. The wirings being extended up to an end portion of the semiconductor chip and the external connection terminals are connected electrically by terminal wiring connection members which are formed integrally with the external connection terminals and are extended from the side surface or the back surface of the semiconductor chip to the integrated circuit mounting surface respectively. The external connection terminals and the terminal wiring connection members are formed of same conductive plate material respectively. The wirings being extended up to an end portion of the semiconductor chip and the external connection terminals are connected electrically by terminal wiring connection members which are formed of material different from those of the external connection terminals and the wirings ,and are extended from the side surface or the back surface of the semiconductor chip to the integrated circuit mounting surface respectively. Preferably the external connection terminals are formed of either gold bump electrodes or electrodes which are formed with use of a TAB (Tape Automated Bonding) technique. The external connection terminals are disposed on the side surfaces or the back surface of the semiconductor chip via an insulator. It is preferable that the semiconductor element further comprises a CCD (Charge Coupled Device) provided in the integrated circuit.
- With the above configuration, in the semiconductor element, basically the external connection terminals are disposed only on the side surfaces, the back surface, or both the side surfaces and the back surface of the semiconductor chip. In more detail, at least bonding areas of the external connection terminals are disposed only on side surfaces, a back surface, or both the side surfaces and the back surface of the semiconductor chip. The electrical measuring electrodes used to measure electric characteristics of the integrated circuit are disposed on the dicing lines to be connected to the wirings, and then removed by dicing process after the electrical measurement (characteristic evaluation test) has been completed, so that the electrical measuring electrodes are disconnected from the wirings. The external connection terminals are connected electrically to the wirings from which the electrical measuring electrodes have been disconnected. As a consequence, the external connection terminals can be formed on the side surfaces or the back surface of the semiconductor chip. In addition, only the integrated circuit and the wirings are formed on the integrated circuit mounting surface of the semiconductor element, but the electrical measuring electrodes are not formed on the integrated circuit mounting surface of the semiconductor element. For this reason, the element surface area of the semiconductor element can be reduced.
- Besides, in the case that the semiconductor element consists of the optical element which has the photo detector and the CCD in the integrated circuit, the photo detector and the external connection terminals can be formed on different surfaces of the semiconductor element respectively and therefore adhesive substance which is generated upon bonding and dropped down onto the photo detector can be lessened. For this reason, degradation in characteristics of the photo detector due to such adhesive substance can be prevented while reducing the element area.
- Further, the wirings and the external connection terminals can be connected simply by the terminal wiring connection members.
- According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor element comprising the steps of forming, on a surface of a semiconductor wafer, a plurality of semiconductor elements having integrated circuits therein respectively, electrical measuring electrodes arranged on dicing lines between the semiconductor elements, for measuring electric characteristics of each integrated circuit in each semiconductor element, and wirings for connecting electrically the integrated circuits and the electrical measuring electrodes; executing electrical measurement of the integrated circuits provided in the semiconductor elements by use of the electrical measuring electrodes; dividing the semiconductor wafer into individual semiconductor elements along the dicing lines and simultaneously removing the electrical measuring electrodes from the semiconductor elements; and forming external connection terminals on side surfaces or a back surface or both the side surfaces and the back surface of the semiconductor element to be electrically connected to the wirings from which the electrical measuring electrodes are removed. It is preferable that basically the electrical measuring electrodes and the wirings are formed as an identical wiring layer. Like the above, it is preferable that the semiconductor element comprises the photo detectors and CCD in the integrated circuits.
- With the above configuration, the semiconductor element can be formed which enables reduction in the element area. The semiconductor element can also be formed which can prevent degradation in characteristics while reducing the element area. Since the electrical measuring electrodes can be removed at the same time dicing process is executed, the number of production process can be reduced by eliminating an individual step of removing the electrical measuring electrodes.
- According to a third aspect of the present invention, there is provided a semiconductor device on which a semiconductor element is mounted, comprising a semiconductor element including the above integrated circuit, wirings, and external connection terminals; and an encapsulation package having lead wirings connected electrically to the external connection terminals of the semiconductor element thereon, the semiconductor element being mounted in the encapsulation package. As explained above, it is preferable that the semiconductor element comprises the photo detectors and CCD in the integrated circuits. The external connection terminals of the semiconductor element are connected electrically to the lead wirings of the encapsulation package by direct contact or via wires. Further, it is preferable that the semiconductor element includes a photo detector and a CCD in the integrated circuit, and the encapsulation package includes a light transmission glass provided on the photo detector to transmit optical signals, and is made of a ceramic package with high moisture resistance.
- With the above configuration, since the element area of the semiconductor element can be reduced as stated above, a size reduction of the encapsulation package can be implemented so that a size reduction of the semiconductor device can be achieved. In addition, the optical device can be provided which enables a size reduction.
- Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.
- FIG. 1 is a perspective view showing a semiconductor element according to a first embodiment of the present invention;
- FIG. 2 is a sectional view showing the semiconductor element shown in FIG. 1;
- FIG. 3(A) is a plan view showing a semiconductor wafer used to explain a method of manufacturing the semiconductor element shown in FIG. 1;
- FIG. 3(B) is an enlarged plan view showing a pertinent portion of the semiconductor wafer shown in FIG. 3(A), which is now subjected to electrical measurement;
- FIG. 4(A) is a plan view showing the semiconductor wafer shown in FIG. 3(A), which has undergone the dicing process;
- FIG. 4(B) is a perspective view showing a semiconductor element which is separated from the semiconductor wafer shown in FIG. 4(A) by the dicing process;
- FIG. 5(A) is an enlarged perspective view showing the semiconductor element according to the first embodiment of the present invention, on which external connection terminals have been formed;
- FIG. 5(B) is an enlarged perspective view showing the semiconductor element according to a modification of the first embodiment of the present invention, on which another external connection terminals have been formed;
- FIG. 5(C) is an enlarged perspective view showing the semiconductor element according to another modification of the first embodiment of the present invention, on which still another external connection terminals have been formed;
- FIG. 6 is a sectional view showing a semiconductor device in which the semiconductor element shown in FIG. 1 is mounted;
- FIG. 7 is a perspective view showing a semiconductor element according to a second embodiment of the present invention;
- FIG. 8 is a sectional view showing the semiconductor element shown in FIG. 7;
- FIG. 9 is an enlarged perspective view showing the semiconductor element shown in FIG. 7;
- FIG. 10 is a sectional view showing another semiconductor device in which the semiconductor element shown in FIG. 7 is mounted;
- FIG. 11 is a sectional view showing still another semiconductor device in which the semiconductor element shown in FIG. 7 is mounted;
- FIG. 12 is a perspective view showing an optical element as a semiconductor element in the prior art;
- FIG. 13 is a sectional view showing an optical device in the prior art on which the optical element in FIG. 12 is mounted;
- FIG. 14 is an enlarged sectional view showing a pertinent portion of the optical device shown in FIG. 13;
- FIG. 15 is a fragmental sectional view showing the optical device shown in FIG. 13, which is now being subjected to wire bonding;
- FIG. 16(A) is a fragmental plan view showing the optical element in the prior art;
- FIG. 16(B) is a view showing output signal values which are output from the optical element in the prior art;
- FIG. 17 is a perspective view showing a semiconductor element in the prior art; and
- FIG. 18 is an enlarged sectional view showing a pertinent portion of the optical device in the prior art.
- As shown in FIGS. 1 and 2, an optical element (semiconductor element)20 to be mounted on an optical device (30, described later) comprises an
integrated circuit 21, wirings 23, and external connection terminals (electrodes) 25. Theoptical element 20 is formed of a semiconductor chip made of a single crystal silicon substrate. Anintegrated circuit 21 and thewirings 23 are disposed on an integrated circuit mounting surface of the semiconductor chip. - The integrated
circuit 21 comprises aphoto detector 22, and peripheral circuits such as CCD, driver circuit, signal detector circuit, etc. disposed around thephoto detector 22, though not shown. Thephoto detector 22 is composed of pixels made up of a plurality of photodiodes, etc. which are aligned in one or two-dimensional fashion. The pixels can convert optical signals into electric signals by means of photoelectric conversion. The CCD as the peripheral circuit can transmit sequentially the electric signals derived by thephoto detector 22. The driver circuit can select predetermined pixels of thephoto detector 22. The signal detector circuits can detect the electric signals derived from the pixels. In other words, theoptical element 20 is composed as a one-line-dimensional image sensor, a two-area-dimensional image sensor, a solid state imaging device, or the like. - The
wirings 23 are formed around theintegrated circuit 21 to extend from the integratedcircuit 21 to end portions of the integrated circuit mounting surface. In more detail,respective wirings 23 are extended on the integrated circuit mounting surface to reach the edge of the side surface of the semiconductor chip. Thewirings 23 are electrically connected to theexternal connection terminals 25 in one-by-one correspondence and are then connected electrically to an external device via theexternal connection terminals 25. More particularly, control signals for the image sensor or the solid state imaging device are input from the external device to theintegrated circuit 21 via theexternal connection terminals 25 and thewirings 23 respectively. On the contrary, image information or picture information are output from the integratedcircuit 21 to the external device. In addition, thewirings 23 are also used as test wires which transmit various signals obtained by electrical measurement (characteristic evaluation test) carried out in the course of production process. - As explained above, the
external connection terminals 25 are connected electrically to thewirings 23 and thus used as terminals which connect electrically thewirings 23 and the external device. In the first embodiment, theexternal connection terminals 25 are aligned only on the side surfaces of the semiconductor chip which are different from the integrated circuit mounting surface of the semiconductor chip. After theabove wirings 23 have been used as the test wires, electrical measuring electrodes (23T, described later) (see FIG. 3(B)) are disconnected from thewire 23 and then theexternal connection terminals 25 are connected electrically to the disconnectedwirings 23. Respective structures of theexternal connection terminals 25 will be explained in detail later. - As shown in FIGS. 1 and 2, a difference between the
optical element 20 according to the first embodiment and theoptical element 1 and thesemiconductor element 1 a in the prior art resides in that both theexternal connection terminals 25 and the electrical measuring electrodes 23T, to be described later, are not placed on the integrated circuit mounting surface and thus the element area can be reduced sufficiently. This difference will be explained in more detail along with a manufacturing method (wafer process) of theoptical element 20. - At first, as shown in FIGS.3(A) and 3(B) respectively, the
optical elements 20, thewirings 23, and the electrical measuring electrodes 23T are formed on the surface of thesemiconductor wafer 28 which is made of a single crystal silicon substrate. A plurality ofoptical elements 20 are aligned regularly, and all adjacentoptical elements 20 are formed integrally with each other in this stage. The electrical measuring electrodes 23T are formed on dicing lines (scribe areas) 29 between theoptical elements 20. Thewirings 23 are formed to extend from the integratedcircuit 21 on theoptical element 20 to the electrical measuring electrodes 23T so as to connect electrically theintegrated circuit 21 and the electrical measuring electrodes 23T. Thewirings 23 can be formed by a manufacturing step identical to that used for the wirings which connect respective elements or circuits in theintegrated circuit 21. It is preferable that thewirings 23 and the electrical measuring electrodes 23T are formed by the same wiring layer to reduce the number of production steps. For example, thewirings 23 may be made of either a single-layer film such as aluminum thin film, aluminum alloy thin film, copper thin film, copper alloy thin film, etc. or a laminated film which is formed mainly of these thin films. - Next, as shown in FIG. 3(B), the electrical measurement (probe test) of the
integrated circuit 21 of theoptical element 20 is executed with the use of the electrical measuring electrodes 23T. The electrical measurement is carried out when theoptical element 20 is still in its wafer state, and the selection whether theoptical element 20 is good or bad can be implemented by such electrical measurement. If such quality selection of theoptical elements 20 can be accomplished in their wafer state, there is no necessity of selecting the quality of everyoptical element 20 after a plurality ofoptical elements 20 have been separated from one sheet ofsemiconductor wafer 28 by the dicing process, and therefore wasteful packaging of defectiveoptical elements 20 can be avoided. Accordingly, in order to carry out the electrical measurement ofoptical elements 20 in their wafer state, the electrical measuring electrodes 23T must be formed on the surface of thesemi-conductor wafer 28 before the dicing process is executed. - The electrical measurement is carried out by bring the
probe stylus 40 connected to a tester (not shown) into contact with the electrical measuring electrodes 23T so as to transmit test signals from the tester to theintegrated circuit 21 via theprobe stylus 40, the electrical measuring electrodes 23T, and thewirings 23 respectively. - Next, as shown in FIGS.4(A) and 4(B) respectively, the
semiconductor wafer 28 is divided into a plurality of individualoptical elements 20 by the dicing process on the dicing lines 29. In other words, such dicing process is carried out by cutting the dicinglines 29 of thesemiconductor wafer 28 by a thin diamond grinding wheel (dicing saw) which is rotated at high speed. According to this dicing process, thesemiconductor wafer 28 is divided into the plurality ofoptical elements 20 and at the same time the electrical measuring electrodes 23T formed on the surfaces of the dicing lines 29 are disconnected from thewirings 23 to be removed from respectiveoptical elements 20. As a result, as shown in FIG. 4(B), theoptical element 20 without the electrical measuring electrodes 23T can be formed. - In turn, as shown FIG. 5(A), the
external connection terminals 25 are fitted to the side surfaces of theoptical element 20 to be connected electrically to thewirings 23. In order to connect theexternal connection terminal 25 to thewiring 23 formed on the integrated circuit mounting surface, a terminalwiring connection member 25 a formed like an L-shape which is brought into tight contact with the side surface and the integrated circuit mounting surface of theoptical element 20 respectively is formed integrally with theexternal connection terminal 25. In other words, the terminalwiring connection members 25 a are formed to be extended from theexternal connection terminals 25. In the present invention, if theexternal connection terminals 25 serving as bonding pads to connect theoptical element 20 to the external device are formed on the side surfaces of theoptical element 20, the terminalwiring connection members 25 a which are formed integrally with theexternal connection terminals 25 may be extended onto the integrated circuit mounting surface of theoptical device 20. Theexternal connection terminals 25 and the terminalwiring connection members 25 a are made of conductive plate material such as copper plate or gold plate, for example. The terminalwiring connection members 25 a are formed by machining, for example. The terminalwiring connection members 25 a formed as above are able to connect easily theexternal connection terminals 25 and thewirings 23. - The
external connection terminals 25 are fitted to the side surface of theoptical element 20 via an insulatingfilm 26 respectively. For instance, a resin film having adhesive property such as epoxy resin film, polyimide resin film, etc. may be employed as the insulatingfilm 26. - The terminal
wiring connection members 25 a which are formed integrally with theexternal connection terminals 25 and folded to the integrated circuit mounting surface side come directly into contact with thewiring 23. In such contacting area, thewiring 23 is exposed from aprotection film 24. Theprotection film 24 covers a substantially whole area of the integrated circuit mounting surface of theoptical element 20 such as theintegrated circuit 21, thewirings 23, etc. - Moreover, any of gold bump electrodes (projection electrodes)25B shown in FIG. 5(B) and
TAB electrodes 25T formed by a TAB (Tape Automated Bonding) technique shown in FIG. 5(C) may be employed as theexternal connection terminal 25. - The
gold bump electrodes 25B shown in FIG. 5(B) are formed by bonding gold balls on a surface of the insulatingfilm 26 with the use of a bump bonder like the wire bonder. The gold balls per se can be used as theexternal connection terminal 25. Such gold ball is formed by heating a top end of the gold wire and then working the heated top end into a ball shape. A rear end side of the gold wire is used as a terminal wiring connection member 25Ba which is bonded to thewiring 23. If thegold bump electrode 25B is used as theexternal connection terminal 25, such material that has high junction property with gold is formed at least on an uppermost layer of the insulatingfilm 26. - The
TAB electrodes 25T formed by the TAB technique shown in FIG. 5(C) are formed on a surface of the tapetype insulating film 26 having adhesive property. TheTAB electrodes 25T and thewirings 23 are connected electrically via terminal wiring connection members 25Ta which are extended from the side surfaces to the integrated circuit mounting surface of theoptical element 20. For example, a polyimide resin tape may be used as the insulatingfilm 26, and the gold wire may be used as the terminal wiring connection member 25Ta. The gold wire can be bonded by the ordinary wire bonding technique. The terminal wiring connection member 25Ta is formed of material different from those of thewiring 23 and theTAB electrodes 25T. - After the above wafer process has been completed and, as shown in FIG. 5(A) (or FIG. 5(B) or FIG. 5(C)), the
external connection terminals 25 have been fitted to the side surfaces of theoptical element 20, theoptical element 20 is then packaged to thus complete anoptical device 30, as shown in FIG. 6. Theoptical device 30 comprises theoptical element 20 and apackage 31 which can hermetic-seal theoptical element 20 therein. - The
package 31 includes a light transmission glass (glass lid or window) 33 over thephoto detector 23 of theoptical element 20 so as to input optical signals into thephoto detector 23. For example, borosilicate glass may be used as thelight transmission glass 33. In addition, a cavity in which theoptical element 20 is placed is formed in thepackage 31. Lead wirings 32 which are to be connected electrically to theexternal connection terminals 25 of theoptical element 20 are formed on a surface of the cavity. - In the first embodiment, the
external connection terminals 25 of theoptical element 20 are brought into contact directly with the lead wirings 32 by means of wireless bonding. For instance, solder may be employed to bond theexternal connection terminals 25 and the lead wirings 32. In the event that such wireless bonding is employed, the size reduction of thepackage 31 can be achieved since occupied area required for routing of the wires can be reduced. - The
package 31 may be formed by a ceramic package or a plastic package. If moisture resistance is required for the package, the ceramic package will be utilized. If cost of the package has to be suppressed lower, the plastic package will be utilized. Further, the lead wirings 23 may be formed of aluminum clad or copper clad, for example. - In a second embodiment, the
external connection terminals 25 are formed on the back surface of theoptical element 20. As shown in FIGS. 7 and 8, theexternal connection terminals 25 are arranged on the back surface of the semiconductor chip, i.e., the surface opposing to the integrated circuit mounting surface of theoptical element 20. - As shown in FIG. 9, in order to connect electrically the
external connection terminal 25 placed on the back surface of theoptical element 20 to thewiring 23 formed on the integrated circuit mounting surface, terminalwiring connection members 25 a each formed like a C-shape which is brought into tight contact with the back surface, the side surface, and the integrated circuit mounting surface of theoptical element 20 respectively so as to be extended from the back surface to the integrated circuit mounting surface via the side surface are formed integrally with theexternal connection terminals 25. In the present invention, like the first embodiment, if theexternal connection terminals 25 are formed on the side surfaces of theoptical element 20, the terminalwiring connection members 25 a which are formed integrally with theexternal connection terminals 25 may be extended onto the integrated circuit mounting surface of theoptical element 20. Since a basic structure of theexternal connection terminal 25 is similar to that of theexternal connection terminal 25 in the above first embodiment, its explanation will be omitted in the second embodiment. - As shown in FIG. 10, the
optical element 20, on the back surface of which theexternal connection terminals 25 are aligned, is packaged in thepackage 31, so that theoptical device 30 is completed. On the bottom surface of the cavity of thepackage 31 are formed previously the lead wirings 32 which are connected, by means of wireless bonding, to theexternal connection terminals 25 which are formed on the back surface of theoptical element 20. - Further, as shown in FIG. 10, the
optical device 30 can be packaged by bringing thephoto detector 22 previously into direct contact with the back surface of thelight transmission glass 33, then mounting theoptical element 20 on thelight transmission glass 33, and then installing theoptical element 20 in thepackage 31. In theoptical device 30 formed in this manner, adhesion of foreign substance such as dust, etc. between thephoto detector 22 for photoelectric conversion and thelight transmission glass 33 can be prevented and therefore defects due to such adhesion of the foreign substance can be reduced. - Furthermore, as shown in FIG. 11, while the
photo detector 22 and the back surface of thelight transmission glass 33 are brought into contact with each other, theoptical element 20 in which theexternal connection terminals 25 are aligned on its back surface can be mounted directly on the back surface of thelight transmission glass 33 which has the lead wirings 32 on its back surface. Theexternal connection terminals 25 formed on the back surface of theoptical element 20 and the lead wirings 32 formed on the back surface of thelight transmission glass 33 are connected electrically by bondingwires 35. In theoptical device 30 thus formed, size reduction can be implemented much more since thepackage 31 can be neglected. - As explained as above, in the present invention, in essence the
external connection terminals 25 are arranged only on the side surfaces, the back surface, or both the side surfaces and the back surface of theoptical element 20. The electrical measuring electrodes 23T used to measure electric characteristics of theintegrated circuit 21 are arranged on the dicing lines 29 so as to be connected to thewirings 23 and then removed by dicing process after the electrical measurement has been completed, so that the electrical measuring electrodes 23T are disconnected from thewirings 23. Theexternal connection terminals 25 are connected electrically to thewirings 23 from which the electrical measuring electrodes 23T have been disconnected. Accordingly, theexternal connection terminals 25 can be formed on the side surfaces or the back surface of theoptical element 20. Only theintegrated circuit 21 and thewirings 23 are formed on the integrated circuit mounting surface of theoptical element 20, but the electrical measuring electrodes 23T are not formed on the integrated circuit mounting surface of theoptical element 20. Consequently, the element surface area of theoptical element 20 can be reduced. - In addition, in the case that the semiconductor element consists of the
optical element 20 which has thephoto detector 22 and the CCD in theintegrated circuit 21, thephoto detector 22 and theexternal connection terminals 25 can be formed on different surfaces of theoptical element 20 respectively and as a result adhesive substance which is generated upon bonding and dropped down onto thephoto detector 22 can be lessened. Therefore, degradation in characteristics of thephoto detector 22 due to such adhesive substance can be prevented while reducing the element area. - Moreover, according to the present invention, in the manufacturing method of the
semiconductor element 20, the number of production process can be reduced by eliminating an individual step of removing the electrical measuring electrodes 23T since the electrical measuring electrodes 23T can be removed at the same time when dicing process is executed. - Furthermore, in the present invention, since the element area of the
optical element 20 can be reduced as stated above, a size reduction of thepackage 31 can be implemented so that a size reduction of theoptical device 30 can be achieved. - The present invention should be interpreted not to be limited to the above embodiments. For instance, in the present invention, the
external connection terminals 25 may be provided previously to the lead wirings 32 of thepackage 31 in positions corresponding to the side surfaces, the back surface, or both the side surfaces and the back surface of theoptical element 20 and then theexternal connection terminals 25 and thewirings 23 of theoptical element 20 may be connected electrically. Otherwise, the lead wirings per se may be formed as theexternal connection terminals 25. - Furthermore, the present invention is not limited to the
optical element 20 such as the image sensor, the solid state imaging device, etc. For example, the present invention may be applied to other optical elements such as a photo detector without the CCD used in a photo coupler. In addition, the present invention may be applied to all semiconductor elements such as memory element, logical element, etc. According to the present invention, the semiconductor devices in which these semiconductor elements are mounted respectively can achieve the same advantages as those as described above. - Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/803,027 US6346432B2 (en) | 1997-01-10 | 2001-03-12 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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JP9-003192 | 1997-01-10 | ||
JP00319297A JP3462026B2 (en) | 1997-01-10 | 1997-01-10 | Method for manufacturing semiconductor device |
JPP09-3192 | 1997-01-10 | ||
US09/003,808 US6232655B1 (en) | 1997-01-10 | 1998-01-07 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element |
US09/803,027 US6346432B2 (en) | 1997-01-10 | 2001-03-12 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element |
Related Parent Applications (1)
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US09/003,808 Division US6232655B1 (en) | 1997-01-10 | 1998-01-07 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element |
Publications (2)
Publication Number | Publication Date |
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US20010009300A1 true US20010009300A1 (en) | 2001-07-26 |
US6346432B2 US6346432B2 (en) | 2002-02-12 |
Family
ID=11550553
Family Applications (2)
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US09/003,808 Expired - Fee Related US6232655B1 (en) | 1997-01-10 | 1998-01-07 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element |
US09/803,027 Expired - Fee Related US6346432B2 (en) | 1997-01-10 | 2001-03-12 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element |
Family Applications Before (1)
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US09/003,808 Expired - Fee Related US6232655B1 (en) | 1997-01-10 | 1998-01-07 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element |
Country Status (2)
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US (2) | US6232655B1 (en) |
JP (1) | JP3462026B2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
US6346432B2 (en) | 2002-02-12 |
JP3462026B2 (en) | 2003-11-05 |
JPH10199887A (en) | 1998-07-31 |
US6232655B1 (en) | 2001-05-15 |
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