US20010016409A1 - High-q inductive elements - Google Patents
High-q inductive elements Download PDFInfo
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- US20010016409A1 US20010016409A1 US09/467,991 US46799199A US2001016409A1 US 20010016409 A1 US20010016409 A1 US 20010016409A1 US 46799199 A US46799199 A US 46799199A US 2001016409 A1 US2001016409 A1 US 2001016409A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
Definitions
- An inductive element 203 can be used in a communications system 400 , such as a cellular telephone, as illustrated in FIG. 4. Multiple inductive elements 203 may be coupled in series and/or in parallel to provide a desired inductance value.
- the communications system 400 includes antennas 406 respectively coupled to a receiver 404 and a transmitter 402 .
- the receiver 404 is coupled to a speaker 410 .
- the transmitter 402 is coupled to a microphone 408 .
- the transmitter 402 and receiver 404 each may include an inductive element 203 coupled to a semiconductor device 422 , such as a transistor or a diode.
- inductive elements 203 can be formed in conjunction with standard silicon IC processes. Furthermore, it is an additional benefit of the present invention that it provides inductive elements 203 that can be used in a communications system to improve selectivity, noise figure and efficiency.
Abstract
Description
- This application is related to a patent application entitled “BURIED CONDUCTORS,” (attorney docket no. 303.367US1) hereby incorporated by reference, contemporaneously filed with this application.
- The present invention relates generally to integrated circuits, and more specifically to electrical components of integrated circuits.
- Analog integrated circuits (ICs) are now being extensively used, for example, in wireless radio frequency (RF) applications such as cellular telephones where high frequencies are encountered. Many analog ICs include inductive elements, such as inductors, formed by a conductor. Inductive elements with a relatively high quality (Q) factor, or low loss, are preferably used in analog ICs. As a result, the analog integrated circuits have superior performance, including selectivity, noise figure, and efficiency. Relatively high Q inductors have been formed on insulating bulk semiconductors, such as gallium arsenide.
- Most integrated circuits, however, are formed on silicon. In comparison to gallium arsenide ICs, silicon ICs can be fabricated relatively inexpensively. Also, analog and digital circuits may be readily combined on silicon ICs. However, unlike gallium arsenide, silicon is a conductive bulk semiconductor. As a result, conventional inductive elements formed on silicon are relatively lossy, and thus have relatively low Q factors. For example, Q factors of 3 to 8 are reported for inductors fabricated on silicon in Nguyen et al., “Si IC-compatible inductors and LC Passive Filters,” IEEE Journal of Solid-State Circuits, vol. 25, no. 4, p. 1028-1031, 1990, herein incorporated by reference.
- An inductor formed on an IC101 may be a conventional rectangular
spiral inductor 103, as illustrated in FIG. 1A. The conventional rectangularspiral inductor 103 includes substantially parallelconductive branches 121 that are mutually coupled to increase the rectangular spiral inductor's 103 effective inductance. - The conventional rectangular
spiral inductor 103 is formed in the following manner. Afirst conductor 109 is patterned on the IC 101. Then, an insulator, such as resist, defining the location ofair bridges 105, is patterned on theIC 101. Next, asecond conductor 107 is patterned on the IC 101. However, where anair bridge 105 is to be formed, the insulator separates the first andsecond conductors conventional air bridges 105 are formed by removing the insulator. -
Conventional air bridges 105, in this example, permit the twoconductors Conventional air bridges 105 are formed by substantiallyperpendicular conductors conductors conductors conductors - FIG. 1C illustrates a prior art first order lumped element electrical model of the rectangular
spiral inductor 103 that describes the electrical characteristics of the rectangularspiral inductor 103 below its self-resonant frequency. The self resonant frequency is the maximum frequency at which the rectangularspiral inductor 103 acts as an inductor. Above the self resonant frequency, for example, the rectangular spiral inductor may exhibit capacitive characteristics. - L is the effective inductance of the rectangular
spiral inductor 103. The effective inductance represents the sum of both self and mutual inductances of thebranches 121. The inductance, L, of the rectangularspiral inductor 103 is determined by (1) the length of thebranches 121, (2) the spacing between thebranches 121, and (3) the number ofbranches 121, or turns. - The other model elements are parasitics that result from the physical implementation of the rectangular
spiral inductor 103. RDC and RSKIN EFFECT are respectively the lumped element equivalent DC and skin effect resistances of theconductors conductors conductors conductive branches 121. CS is determined by both the distance betweenadjacent branches 121, and the dielectric constant of the material proximate to thoseadjacent branches 121. The CpS are lumped element equivalent capacitances representing capacitances between theconductors IC 101 on which the rectangularspiral inductor 103 is formed. The CpS correspond to the width of theconductors conductors spiral inductor 103 are a function of the reactances and resistances described by the electrical model of FIG. 1C. - To increase its Q factor, resistances and/or capacitances of the rectangular
spiral inductor 103 should be reduced. One technique for reducing the Q factor of the inductor is disclosed in J. N. Burghartz et al., “Integrated RF and Microwave Components in BiCMOS Technology,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1559-1570, 1996 (herein after the “Burghartz Article”), herein incorporated by reference. The Burghartz Article discloses inductors, on silicon ICs, whose conductors are displaced above the silicon, and are encased in oxide. These inductors have Q factors exceeding 10. The higher Q factors arise, in part, because the inductors, disclosed in the Burghartz Article, have relatively lower values of Cp because the conductors are farther displaced from the IC ground plane by the oxide. - Further, the inductors disclosed in the Burghartz Article require a complex five-level metal silicon technology that is more complicated than conventional two- to four-level metal silicon technologies. Therefore, there is a need for inductors having relatively high Q factors that can be formed with conventional silicon technologies.
- The present invention provides a method of forming air bridges, on a substrate or an integrated circuit, which may be used to form inductors and other devices. A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator. A second conductor is formed on the second insulator, and is electrically coupled to the first conductor by the via hole. The second conductor is patterned. A cavity is formed under the second conductor, and in the first and second insulators. In one embodiment, the first and second conductors form air bridges.
- In another embodiment, a support structure is formed during the step of forming the cavity. In yet another embodiment, a conductive pad is formed over the support structure during the step of patterning the second conductor.
- In a further embodiment, the present invention provides an air bridge or inductive element on a substrate or integrated circuit. A first insulator is formed on a base layer. A first conductor is formed and patterned on the first insulator. A second insulator is formed on the first insulator. A via hole is formed in the second insulator. A masking layer is developed on the integrated circuit. A cavity, defined by the developed masking layer, is formed in the first and second insulators. The cavity is filled with a polymer. The integrated circuit is cleaned. A second conductor is formed on the polymer, and coupled to the first conductor by the via hole. The second conductor is patterned. In yet a further embodiment, the cavity is filled with a polymer that is foam.
- In yet a further embodiment, the inductive element includes a second via hole in the support structure that couples the first and second conductors. In another embodiment, the cavity is filled with a polymer. In yet a further embodiment, the the polymer is a foam.
- In another embodiment, an inductive element on a substrate, or an integrated circuit, comprises a base layer. A first conductor is buried in the base layer. An insulator is formed on the base layer. A second conductor, having first and second branches that are substantially parallel, is formed on the second insulator. A plug, formed in the base layer, is coupled to the first conductor. A via hole, formed in the insulator, couples the plug to the second conductor. A cavity, under second conductor, is formed in the insulator. A support structure, in the cavity, props up the second conductor above the base layer.
- In yet a further embodiment, an inductive element is formed, on a substrate or an integrated circuit, with a low dielectric inorganic insulator. A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed, over the first insulator, from the low dielectric inorganic insulator. A portion of the second insulator is oxidized. The oxidized portion of the second insulator is removed. A via hole is formed in the second insulator. A second conductor, formed on the second insulator, is coupled to the first conductor by the via hole. The second conductor is patterned.
- It is a benefit of the present invention that the inductive elements described above have an enhanced Q factor. It is a further advantage of the present invention that the inductive elements described above have an enhanced self-resonant frequency. It is yet a further benefit of the present invention that the inductive elements described above can be formed in conjunction with standard silicon IC processes.
- The inductive elements described above can be incorporated in a receiver and/or a transmitter of a communications systems. As a result, the communications system will exhibit higher selectivity and efficiency, and lower noise figure.
- The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.
- FIG. 1A illustrates a plan view of a prior art rectangular spiral inductor.
- FIG. 1B illustrates a cross-sectional diagram of a prior art air bridge.
- FIG. 1C illustrates a prior art first order lumped element electrical model of a rectangular spiral inductor.
- FIG. 2A illustrates a plan view of an integrated circuit including an inductive element.
- FIG. 2B illustrates a cross-sectional diagram of the integrated circuit including the inductive element.
- FIG. 2C illustrates a cross-sectional diagram of an integrated circuit including an inductive element and a via hole in a support structure.
- FIG. 3 illustrates a cross-sectional diagram of an integrated circuit including an inductive element and a buried conductor.
- FIG. 4 illustrates a communications system including an inductive element according the present invention.
- In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms base layer, wafer, and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Base layer, wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. A ground plane may lay underneath the base layer, wafer or substrate. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
- This application is related to patent application Ser. No. 09/030,430, entitled “METHODS AND STRUCTURES FOR METAL INTERCONNECTIONS IN INTEGRATED CIRCUITS,” hereby incorporated by reference. This application is also related to patent application Ser. No. 08/892,114, entitled “METHOD OF FORMING INSULATING MATERIAL FOR AN INTEGRATED CIRCUIT AND INTEGRATED CIRCUITS RESULTING FROM SAME,” hereby incorporated by reference. This application is also related to patent application Ser. No. 08/954,450, entitled “METHOD AND SUPPORT STRUCTURE FOR AIR BRIDGE WIRING OF AN INTEGRATED CIRCUIT,” hereby incorporated by reference. This application is also related to patent application Ser. No. 08/347,673, entitled “ALUMINUM BASED ALLOY BRIDGE STRUCTURE AND METHOD OF FORMING SAME,” hereby incorporated by reference.
- FIG. 2A illustrates a plan view of one embodiment of the present invention, an
inductive element 203, specifically a rectangular spiral inductor, formed on an integrated circuit (IC) 201. The rectangular spiral inductor is formed byair bridges 205 propped up bysupport structures 215, to diminish undesired capacitive coupling to a ground plane beneath theIC 201. Substantially parallel conductive branches of the spiral inductors are formed by air bridges. FIG. 2B illustrates a cross-sectional view of theinductive element 203. Theinductive element 203 can be formed in conjunction with standard silicon processes, for example using only two conductor levels, utilizing the techniques described below. - In one embodiment, the
inductive element 203 is formed in the following manner. Afirst insulator 206 is formed on abase layer 204. In one embodiment, thefirst insulator 206 andbase layer 204 are respectively an oxide, such as silicon dioxide, and a semiconductor, such as silicon. - Then, a
first conductor 209 is formed on thefirst insulator 206. In one embodiment, thefirst conductor 209 is an aluminum alloy. Thefirst conductor 209 is then patterned to form interconnects to the terminals of theinductive element 203. - Next, a
second insulator 210 is formed over thefirst insulator 206. In one embodiment, thesecond insulator 210 may be an oxide, such as silicon dioxide. Then, viaholes 211 are formed in thesecond insulator 210. The via holes 211 are filled with a conductor such as an aluminum alloy. - The integrated
circuit 201, including thesecond insulator 210, is subsequently planarized, for example by chemical-mechanical planarization (CMP). Next, asecond conductor 207, substantially defining theinductive element 203, is formed and patterned on theintegrated circuit 201. In one embodiment, thesecond conductor 207 is an aluminum alloy. Thesecond conductor 207 is electrically coupled to thefirst conductor 209 by the via holes 211. - In one embodiment, the unterminated end of the
second conductor 207, proximate to the center of theinductive element 203, is electrically coupled to thefirst conductor 209 by a viahole 212 in asupport structure 215, as illustrated in FIG. 2C. In such an embodiment, thefirst conductor 209 extends into asupport structure 215. Alternatively, the viahole 212 in thesupport structure 215 is not required when asupport structure 215 is formed with a conductive core and insulating sheath in a manner known to those skilled in the art. In either case, thefirst conductor 209 is formed at a different height in thecavity 213, and therefore does not directly make electrical contact with thesecond conductor 207. - A
cavity 213 under thesecond conductor 209 is then formed by directionally etching the first andsecond insulators second conductor 207 or aseparate masking layer 233 formed on theintegrated circuit 201 may be used to define the cross section of thecavity 213, and thesupport structures 215 for propping up the first andsecond conductors second insulator second conductor 207, while not substantially diminishing thesupport structures 215. - Because the first and
second conductors base layer 204 and the underlying ground plane by a relatively low-dielectric-constant insulator, air, the CpS, of FIG. 1C, are reduced. Additionally, because the substantially perpendicular branches of theinductive element 203 are capacitively coupled through air, instead of the oxide or silicon, the CS, of FIG. 1C, is also reduced. As a result, the Q factor of theinductive element 203 is increased. Further, the self-resonant frequency of theinductive element 203 is also increased. - In another embodiment of the present invention,
conductive pads 231 can be formed during the patterning of thesecond conductor 207. Theconductive pads 231 are formed from thesecond conductor 207. Theconductive pads 231 have a width greater than the width of thesecond conductor 207 so that theconductive pads 231 have a relatively large surface area that covers thesupport structures 215. As a result, theconductive pads 231 prevent the anisotropic etch from removing substantially all of thesupport structures 215 formed beneath theconductive pads 231. The actual size of thesupport structure 215 is a function of the thickness of theinsulators conductive pads 231 may be formed at any point along thesecond conductor 207 where asupport structure 215 is made, but is commonly formed where the path of thesecond conductor 207 changes directions, such as at the corners as shown in FIG. 2A. - In an alternative embodiment, the
cavity 213 andsupport structures 215 may be formed in a manner that does not necessarily require the anisotropic etch described above. Using the initial steps described above, through formation of the via holes 211, amasking layer 233 is then formed on thesecond insulator 210 of theintegrated circuit 201. Themasking layer 233 is developed to define the cross-section of acavity 213 andsupport structures 215. Thecavity 213 is formed by isotropically etching theinsulator masking layer 233. Thesupport structures 215 are in thecavity 213. - The
cavity 213 andsupport structures 215 are formed by removing, for example by etching, some of the first andsecond insulators cavity 213 is formed simultaneously during the formation of the via holes 211 illustrated in FIG. 2B, in a manner know to those skilled in the art. - In one embodiment, an anisotropic etch is used to remove
first insulator 206 covered by thefirst conductor 209 in thecavity 213. In such a case, theconductive pads 231, described above, are preferably formed over thesupport structures 215. - The
cavity 213 is then filled, for example, with apolymer 225, such as Parylene C, polyimide, or a foam. In one embodiment, the polyimide may be PMDA-ODA. In another embodiment, the foam may be a foam like those disclosed in R. D. Miller et al., “Low Dielectric Constant Polyimides and Polyimide Nanofoams,” Seventh Meeting of the DuPont Symposium on Polyimides in Microelectronics, Sep. 16-18, 1996, herein incorporated by reference. - The integrated
circuit 201, including thepolymer 225, is then planarized, for example with CMP or etch back techniques until at least the viahole 211 is exposed. Then, theintegrated circuit 201, including thepolymer 225 andsecond insulator 210, is cleaned to permit thesecond conductor 207 to form a low resistivity contact to the viahole 211. Next, thesecond conductor 207, which substantially defines theinductive element 203, is formed and patterned on theintegrated circuit 201. Thesecond conductor 207 is formed over thecavity 213 and on thesupport structures 215. - In one embodiment, the
polymer 225 is then removed from thecavity 213 of theintegrated circuit 201. As described above, because the first andsecond conductors cavity 213 are substantially formed over a low dielectric insulator, such as air or thepolymer 225, theinductive element 203 has both an enhanced Q factor and self-resonant frequency. - In yet a further embodiment, the
first conductor 209 andsecond insulator 210 can be replaced with a conductor buried in thebase layer 304, otherwise known as a buriedconductor 364, as illustrated in FIG. 3. In FIG. 3,base layer 304 actually comprises a series oflayers Buried conductors 364 facilitate increasedIC 201 density. In one embodiment, the buriedconductor 364 is positioned between two buriedinsulators 362, such as oxides. In one embodiment, the buriedconductor 364 is tungsten. In this embodiment, the buriedinsulators 362 separate the buriedconductor 364 from first and second semiconductor layers 360, 368, which are respectively N+ and P− doped silicon. The buriedconductor 364 is electrically coupled to thesecond conductor 207 through aplug 366, which can also be made from tungsten, and a viahole 211. - In yet another embodiment, an
inductive element 203 is formed without acavity 213, diminishingIC 201 processing requirements. Afirst insulator 206 is formed on thebase layer 204. Afirst conductor 209 is formed on thefirst insulator 206. Thefirst conductor 209 is patterned. Asecond insulator 210 is formed, over thefirst insulator 206, from a low dielectric inorganic insulator. The low dielectric inorganic insulator may be formed from silicon and germanium which are deposited on theintegrated circuit 201 at a temperature below the melting point of the metal used for thefirst conductor 209. A technique for depositing silicon and germanium is described by T. J. King, “Deposition and Properties of Low-Pressure Chemical-Vapor Deposited Polycrystalline Silicon-Germanium Films,” Journal of the Electro-Chemical Society, August 1994, pp. 2235-41, which is hereby incorporated by reference. After silicon and germanium deposition is complete, thesecond insulator 210 is oxidized. The oxidized second insulator contains extractable germanium oxide, which is removed from thesecond insulator 210. A viahole 211 is formed in thesecond insulator 210. Asecond conductor 207 is formed on thesecond insulator 210. Thesecond conductor 207 is coupled to thefirst conductor 209 by the viahole 211. Thesecond conductor 207 is patterned. - This process provides a
second insulator 210 that is porous, and has a relatively low dielectric constant. As a result, the effective dielectric constant of the portion of the IC underlying thesecond conductor 207 is reduced, which diminishes Cp. Thus, the Q factor and the self-resonant frequency of theinductive element 203 are enhanced. Further, the capacitances ofother IC 201 conductors, over thesecond insulator 210, are desirably diminished. - Further, in another embodiment, the foregoing process can be used to form low
dielectric support structures 215 in aninductive element 203 having acavity 213. As a result, the effective dielectric constant of thesupport structures 215 is reduced, further diminishing the CpS. Thus, the Q factor and the self-resonant frequency of theinductive element 203 are enhanced. Further, the capacitances ofother IC 201 conductors, over thesecond insulator 210, are desirably diminished. - An
inductive element 203 according to the present invention can be used in acommunications system 400, such as a cellular telephone, as illustrated in FIG. 4. Multipleinductive elements 203 may be coupled in series and/or in parallel to provide a desired inductance value. Thecommunications system 400 includesantennas 406 respectively coupled to areceiver 404 and atransmitter 402. Thereceiver 404 is coupled to aspeaker 410. Thetransmitter 402 is coupled to amicrophone 408. Thetransmitter 402 andreceiver 404 each may include aninductive element 203 coupled to asemiconductor device 422, such as a transistor or a diode. - The
inductive elements 203 in thecommunications system 400 enhancereceiver 404 andtransmitter 402 performance. Theinductive element 203 improves the selectivity and noise figure of thereceiver 404. Theinductive element 203 improves the efficiency of the transmitter. - It is an advantage of the present invention that it enhances the Q and self-resonant frequency of
inductive elements 203. It is also a benefit of the present invention thatinductive elements 203 can be formed in conjunction with standard silicon IC processes. Furthermore, it is an additional benefit of the present invention that it providesinductive elements 203 that can be used in a communications system to improve selectivity, noise figure and efficiency. - It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. For example, the
inductive elements 203 may be inductors, transformers or auto-transformers. Theinductive elements 203 may be formed withconductors inductive elements 203 may have a variety of shapes, which include, but are not limited to, rectangles, octagonals and spirals. Furthermore, the techniques described above can be used to form air bridge structures other than forinductive elements 203. Also, if the air bridge structures are sufficiently long,additional support structures 215, not shown, can be used to prop up the air bridge structures. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (68)
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US09/467,991 US6376895B2 (en) | 1998-04-29 | 1999-12-20 | High-Q inductive elements |
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US09/069,346 US6025261A (en) | 1998-04-29 | 1998-04-29 | Method for making high-Q inductive elements |
US09/467,991 US6376895B2 (en) | 1998-04-29 | 1999-12-20 | High-Q inductive elements |
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US09/867,281 Expired - Lifetime US6377156B2 (en) | 1998-04-29 | 2001-05-29 | High-Q inductive elements |
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Also Published As
Publication number | Publication date |
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US20010024153A1 (en) | 2001-09-27 |
US6377156B2 (en) | 2002-04-23 |
US6376895B2 (en) | 2002-04-23 |
US6025261A (en) | 2000-02-15 |
US6239684B1 (en) | 2001-05-29 |
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