US20010023994A1 - Semiconductor device and the method for manufacturing the same - Google Patents
Semiconductor device and the method for manufacturing the same Download PDFInfo
- Publication number
- US20010023994A1 US20010023994A1 US09/799,803 US79980301A US2001023994A1 US 20010023994 A1 US20010023994 A1 US 20010023994A1 US 79980301 A US79980301 A US 79980301A US 2001023994 A1 US2001023994 A1 US 2001023994A1
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- Prior art keywords
- semiconductor chip
- die pad
- adhesive layer
- top surface
- electrodes
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to a semiconductor device, and to the method for manufacturing the same.
- FIG. 9 shows a schematic diagram of a conventional semiconductor device molded with resin.
- FIG. 10 shows a top-view of the semiconductor device.
- QFP Quad Flat Package
- This semiconductor device has a first semiconductor chip 91 , a second semiconductor chip 92 , a die pad 93 , a first adhesive layer 94 , a second adhesive layer 95 , electrodes 96 on the first semiconductor chip, electrodes 97 on the second semiconductor chip, inner leads 98 , metal wires 99 , 910 , a package portion 912 , outer leads 913 , and a pad support portion 914 .
- the semiconductor chips 91 and 92 are stacked on a die pad 93 .
- the die pad 93 is lower than the inner leads 98 as shown in FIG. 9 and FIG. 10.
- the hanging portion of the die pad 93 is bent, and the die pad and the inner leads are not in the same level.
- the bent portion is indicated by reference numeral 1011 in FIG. 10.
- This structure is called downset.
- the thickness t 1 of the resin on the semiconductor chip 92 is the same as the thickness t 2 of the resin under the die pad 93 in the conventional design.
- the resin is filled proportionally during transfer molding because the thickness of resin on the semiconductor chip 92 and the thickness of resin under the die pad 93 are the same. Therefore, a short-circuit of wires on the semiconductor chip 91 and the semiconductor chip 92 is prevented. The warp of the package is also prevented.
- the semiconductor chip 91 is fixed over the die pad 93 by the first adhesive layer 94 .
- the semiconductor chip 92 is fixed over the semiconductor chip 91 by the second adhesive layer 5 .
- the electrodes 96 , 97 on each semiconductor chips are connected to inner leads 98 via metal wires 99 , 910 .
- metal wires 99 , 910 For example, gold wires connect electrodes and inner leads.
- Some electrodes 97 on the semiconductor chip 92 are connected to the electrodes 96 on the semiconductor chip 91 .
- a resin for example, epoxy resin
- the outer leads 13 are plated with solder. The outer leads 13 are then transformed into a predetermined form.
- An object of the present invention is to provide a semiconductor device and the method for manufacturing the same that do not need a downset process. Therefore the yield is improved during the formation of a lead frame.
- a semiconductor device comprises, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the top surface of the first semiconductor chip is fixed on the bottom surface of the die pad, the bottom surface of the second semiconductor chip is fixed on the top surface of the die pad.
- a method for manufacturing the semiconductor device comprises forming a first adhesive layer on a bottom surface of a die pad, forming a second adhesive layer on a top surface of the die pad, fixing a top surface of a first semiconductor chip on the first adhesive layer, fixing a bottom surface of a second semiconductor chip which is smaller than the first semiconductor chip on the second adhesive layer.
- FIG. 1 shows a cross sectional view of a semiconductor device of a first preferred embodiment.
- FIG. 2 shows a perspective diagram from the top view of the semiconductor device in the first preferred embodiment.
- FIG. 3 shows a cross sectional view of a semiconductor device of a second preferred embodiment.
- FIG. 4 shows a perspective diagram from the top view of the semiconductor device of the second preferred embodiment.
- FIG. 5 shows a cross sectional view of the method for manufacturing the semiconductor device of the third p referred embodiment.
- FIG. 6 shows a cross sectional view of the method for manufacturing a semiconductor device of the fourth preferred embodiment.
- FIG. 7 shows a cross sectional view of the method for manufacturing a semiconductor device of the fifth preferred embodiment.
- FIG. 8 shows a cross sectional view diagram of the method for manufacturing a semiconductor device of the sixth preferred embodiment.
- FIG. 9 shows a cross sectional view of a conventional semiconductor device.
- FIG. 10 shows a top view of the conventional semiconductor device.
- FIG. 1 shows a cross sectional view of the semiconductor device of a first preferred embodiment.
- FIG. 2 shows a perspective diagram from the top view of the semiconductor device in the first embodiment.
- This semiconductor device has a first semiconductor chip 1 , a second semiconductor chip 2 , a die pad 3 , a first adhesive layer 4 , a second adhesive layer 5 , electrodes 6 on the first semiconductor chip, electrodes 7 on the second semiconductor chip, inner leads 8 , metal wires 9 , 10 , a package portion 12 , outer leads 13 , and a pad support portion 14 .
- the package is not limited to the drawings.
- the inner leads 8 can be formed with an interconnection on Ball Grid Array (BGA) substrate.
- BGA Ball Grid Array
- the die pad 3 for mounting a semiconductor chip is not downset.
- the pad support portion 14 is not bent. Therefore, the die pad 3 and the inner leads 8 are formed on the same level.
- the second adhesive layer 5 is formed on the top surface of the die pad 3 (the die pad top surface) and the first adhesive layer 4 is formed on the bottom surface of the die pad 3 (die pad bottom surface). That is to say, the die pad 3 is disposed between the first and second adhesive layers.
- the first semiconductor chip 1 is fixed on the first adhesive layer 4 .
- the top surface of the first semiconductor chip 1 touches the first adhesive layer 4 , and the first chip top surface is the main surface on which the circuits and electrodes are formed.
- the second semiconductor chip 2 is fixed on the second adhesive layer 5 .
- the bottom surface of the second semiconductor chip 2 touches the second adhesive layer 5 , and the circuits are not formed on this bottom surface.
- the electrodes 6 on the first semiconductor chip are connected to inner leads 8 via metal wires 9 .
- the electrodes 7 on the second semiconductor chip are connected to inner leads 8 via metal wires 10 .
- Some electrodes 6 on the first semiconductor chip 1 are connected to the electrodes 7 on the second semiconductor chip 2 via wires 11 .
- the electrical signal of the semiconductor chips 1 , 2 is outputted through the electrodes 6 , 7 , wires 9 , 10 , 11 , inner leads 8 , and outer leads 13 .
- the package portion 12 is formed by molding resin (for example, epoxy resin) on predetermined portion of the semiconductor device.
- the total thickness of the first adhesive layer 4 plus the first semiconductor chip 1 is the same as the total thickness of the second adhesive layer 5 plus the second semiconductor chip 2 . Therefore, The thickness t 1 of the resin on the second semiconductor chip 2 is the same as the thickness t 2 of the resin under the first semiconductor chip 1 .
- the die pad 3 is disposed between the first semiconductor chip 1 and the second semiconductor chip 2 . Therefore, the hanging portion of the die pad is not have to be bent.
- the first semiconductor chip 1 is wider than the second semiconductor chip 2 and the die pad 3 in this embodiment.
- the electrodes 6 on the first semiconductor chip 1 are disposed outside of the region that is defined by the edge of the second semiconductor chip 2 .
- the electrodes 6 on the first semiconductor chip and the electrodes 7 on the second semiconductor chip do mot overlap from the top view as shown in FIG. 2.
- the first chip top surface 1 is fixed on the first adhesive layer 4
- the second chip bottom surface 2 is fixed on the second adhesive layer 5 . Therefore, all of the electrodes 6 , 7 are not covered with the die pad 3 . It is desirable that the difference of the size between the first semiconductor chip 1 and the second semiconductor chip 2 is at least 0.3 mm in each side. This is a minimum width to form an interconnecting wire between the electrodes 6 on the first semiconductor chip 1 and the electrodes 7 on the second semiconductor chip 2 .
- the electrodes 7 on the second semiconductor chip and the electrodes 6 on the first semiconductor chip 1 do not overlap. Therefore, all of the wire bonding to connect electrodes 6 and electrodes 7 , electrodes 6 and inner lead 8 , and electrodes 7 and inner lead 8 are performed in the same step.
- the wire bonding is performed from the same side (die pad top surface side) in the first preferred embodiment, and there is no wire connected by wire bonding from another side (die pad bottom surface side), and the wire, which has a loop summit at the die pad bottom surface, does not exist. Therefore, the thickness of the semiconductor device can be decreased.
- the die pad top surface 3 is preferably wider than the bottom surface of the semiconductor chip 2 .
- the die pad bottom surface 3 is preferably smaller than the top surface of the semiconductor chip 1 .
- the adhesive layer 5 is prevented from running onto the top surface of the semiconductor chip 1 because the die pad 3 is wider than the semiconductor chip 2 , when the semiconductor chip 2 is fixed.
- An insulating adhesive is used as the adhesive layer 4 because the adhesive layer 4 bonds the first chip top surface, which is formed with circuit, to the die pad 3 .
- a conductive adhesive for example solder paste
- solder paste can be used as the adhesive layer 5 because the second chip bottom surface 2 is fixed on the die pad 3 . Therefore, electric potential can be applied to the second semiconductor chip accordingly.
- a semiconductor device which has a logic semiconductor chip and a memory semiconductor device, is suitable for use a conductive adhesive as the adhesive layer 5 .
- a certain potential should be applied to the substrate of a conventional memory semiconductor chip in order to stabilize an operation, on the other hand, there are many cases that the logic semiconductor chip does not need some potential at its substrate, therefore, the logic semiconductor chip can be used as the first semiconductor chip and the memory semiconductor chip can be used as the second semiconductor chip in the first preferred embodiment.
- This semiconductor device has a simple structure without downset. Therefore the yield of the lead-frame is improved during manufacturing, and the cost of manufacturing is declined.
- the area of the die pad 3 relates to the effect of noise reduction.
- FIG. 3 shows a cross sectional view of the semiconductor device of the second preferred embodiment.
- FIG. 4 shows a perspective diagram from the top view of the semiconductor device in the second embodiment. The same reference numerals are applied for the elements those are described in the first embodiment.
- the die pad 3 of the second preferred embodiment is not downset either.
- the area of the die pad 3 is much smaller than the areas of the first semiconductor chip 1 and the second semiconductor chip 2 . It is desirable that the area of the die pad 3 is smaller than half of the top surface area of the first semiconductor chip 1 .
- the first chip top surface 1 is fixed on the die pad 3 .
- the die pad 3 is smaller than the semiconductor chips 1 and 2 in this embodiment.
- the contact area between the first semiconductor chip 1 and the die pad 3 shrinks because the area of the die pad 3 is small. Therefore the stress and the damage on the surface of the first semiconductor chip are decreased.
- this semiconductor device of the embodiment does not need a coating layer on the first chip top surface 1 because the passivation layer is enough to protect the top surface from damage.
- the coating process is reduced and the cost of manufacturing declines.
- the amount of adhesive required to fix the semiconductor chips is reduced because the area of the die pad 3 is small. It also becomes easy to spread the adhesive uniformly on the total surface of the die pad 3 . Therefore the adhesive strength is enough to fix each semiconductor chip.
- the electrodes 7 on the second semiconductor chip and the electrodes 6 on the first semiconductor chip 1 do not overlap in the same way as the first embodiment. Therefore, all of the wire bonding are performed substantially in the same step.
- the conductive adhesive can be used as the adhesive layer 5 in the second embodiment in the same way as the first embodiment. Therefore, the logic semiconductor chip can be used as the first semiconductor chip and the memory semiconductor chip can be used as the second semiconductor chip in the first preferred embodiment.
- FIGS. 5 A- 5 D show cross sectional views of the method for manufacturing the semiconductor device according to the third preferred embodiment. The same reference numerals are applied for the elements those are described in the first preferred embodiment.
- the die pad 3 which is not downset, is prepared as shown in FIG. 5A.
- the insulating adhesive layer (first adhesive layer) 4 is formed on a bottom surface of the die pad 3 .
- the insulating or conductive adhesive layer 5 (second adhesive layer) is formed over a top surface of the die pad 3 .
- Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape may be used as these adhesive layers. These adhesive layers preferably have some viscosity before hardening. This viscosity allows a semiconductor chip to be aligned on the die pad 3 .
- the first semiconductor chip 1 is put on the die pad bottom surface as shown in FIG. 5B.
- the first semiconductor chip 1 , the first adhesive layer 4 and the die pad 3 are heated from the lower side of the first semiconductor chip 1 .
- the adhesive layer 4 fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
- the second semiconductor chip 2 is put over the die pad top surface 3 as shown in FIG. 5C.
- the second semiconductor chip 2 , the second adhesive layer 5 and the die pad 3 are heated from the lower side of the first semiconductor chip 2 .
- the adhesive layer 5 fixes the second semiconductor chip 2 on the die pad 3 after this heat treatment.
- the manufacturing step is simplified because the downset process is lessened. Therefore the yield of the lead-frame is improved during manufacturing, and the cost of manufacturing is reduced.
- the adhesive layers are formed before the semiconductor chips are put on the die pad 3 . Therefore the spread of the adhesive layer can be easily controlled when the semiconductor chips are pressed on the die pad 3 .
- the possibility that the adhesive layer 5 runs onto the top surface of the semiconductor chip 1 is decreased. Therefore the distance between the edge of the first semiconductor chip 1 and the edge of the second semiconductor chip 2 is minimized. This minimized distance means the shortest distance that the electrodes 6 on the first semiconductor chip 1 can be connected to the electrodes 7 on the second semiconductor chip 2 via metal wire.
- the wire bonding ban be performed from the same side (die pad top surface side) and in the same step in the first preferred embodiment.
- the wire which has a loop summit at the die pad bottom surface, does not exist. Therefore, turning over the semiconductor device does not have to be performed to perform wire bonding of another side.
- FIG. 6 shows a cross sectional view of the method for manufacturing the semiconductor device of a fourth preferred embodiment.
- the same reference numerals are applied for the elements those are described in the first preferred embodiment.
- the die pad 3 which is not downset, is prepared.
- the insulating adhesive layer 4 (first adhesive layer) is formed on a bottom surface of the die pad 3 .
- the insulating or conductive adhesive layer 5 (second adhesive layer) is formed on a top surface of the die pad 3 .
- Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape may be used as these adhesive layers. These adhesive layers have some viscosity before hardening. This viscosity allows aligning a semiconductor chip on the die pad 3 .
- the first adhesive layer 64 and the second adhesive layer 65 are partly formed on each surface in this embodiment.
- the portion on which the first adhesive layer 64 is formed in the die pad bottom surface does not correspond to the portion on which the second adhesive layer 65 is formed on the die pad top surface.
- thermosetting adhesive is used as the adhesive layers 64 , 65 .
- first semiconductor chip 1 When the first semiconductor chip 1 is fixed, only the first portion, which the first adhesive layer 64 is formed on, are heated. The retained heat does not have an influence on the second adhesive layer 65 . Therefore the second adhesive layer 65 is protected from the changing of the viscosity property.
- the adhesive layers 64 , 65 are formed on each surface of the die pad 3 as described above.
- the first semiconductor chip 1 is put on the die pad bottom surface.
- the adhesive layer 64 fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
- the second semiconductor chip 2 is put over the die pad top surface 3 .
- the second semiconductor chip 2 , the second adhesive layer 65 and the die pad 3 are heated from the lower side of the first semiconductor chip 1 .
- the second adhesive layer 65 fixes the second semiconductor chip 2 on the die pad 3 after this heat treatment.
- the second adhesive layer 65 and the corresponding portion in the die pad 3 are not heated directory during the heat treatment to fix the first semiconductor chip 1 . Therefore the second adhesive layer 65 is protected from the changing of the viscosity property.
- FIG. 7 shows a cross sectional view of the method for manufacturing the semiconductor device of a fifth preferred embodiment. The same numerals are applied for the elements those are described in the first embodiment.
- the die pad 3 which is not downset, is prepared.
- the insulating adhesive layer 74 (first adhesive layer) is formed on the bottom surface of the die pad 3 .
- the insulating or conductive adhesive layer 65 (second adhesive layer) is formed on the top surface of the die pad 3 .
- Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape can be used as these adhesive layers 64 , 65 .
- These adhesive 64 , 65 layers preferably have some viscosity before hardening. This viscosity allows a semiconductor chip to be aligned on the die pad 3 .
- the softening (or hardening) temperature of the first adhesive layer 74 is different from that of the second adhesive layer 75 in this embodiment.
- the same thermoplastic adhesive can be used as the adhesive layers.
- the first semiconductor chip 1 is fixed before the second semiconductor chip 2 is fixed.
- the second adhesive layer is softened by heating from the lower side of the first semiconductor chip 1 .
- the first adhesive layer 1 may be softened during this second heat treatment.
- the softening of the first adhesive layer 74 during the second heat treatment is not preferable to fix the first semiconductor chip tightly and precisely. If the softening temperature of the first adhesive layer is higher than that of the second adhesive layer, this problem does not occur.
- the fixing would be performed more tightly.
- thermoplastic adhesive as an example is described below in order to more fully illustrate this embodiment. This is the opposite example of thermo characteristic to the above example. This method is substantially similar to the third embodiment.
- the die pad 3 which is not downset, is prepared.
- the insulating adhesive layer 74 (first adhesive layer) is formed on bottom surface of the die pad 3 .
- the softening temperature of the first adhesive layer is about 50° C.
- the insulating or conductive adhesive layer 75 (second adhesive layer) is formed on top surface of the die pad 3 .
- the softening temperature of the second adhesive layer is about 100° C.
- the first semiconductor chip 1 is put on the die pad bottom surface 3 .
- the first semiconductor chip 1 , the first adhesive layer 4 and the die pad 3 are heated at the temperature of 50° C. from the lower side of the first semiconductor chip 1 .
- the adhesive layer 4 is hardened because this is a thermosetting adhesive, and it fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
- the second adhesive layer is not hardened during this heat treatment because softened temperature is higher than about 50° C.
- the second semiconductor chip 2 is put over the die pad top surface 3 .
- the second semiconductor chip 2 , the second adhesive layer 5 and the die pad 3 are heated at the temperature of about 100° C. from the lower side of the first semiconductor chip 2 .
- the adhesive layer 4 is hardened and it fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
- FIG. 8 shows a cross sectional view of the method for manufacturing the semiconductor device of the sixth preferred embodiment.
- the same reference numerals are applied for the elements those are described in the first embodiment.
- thermosetting adhesive paste thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape are preferably used as adhesive layers.
- the die pad 3 which is not downset, is prepared.
- the insulating adhesive layer 84 (first adhesive layer) is formed on bottom surface of the die pad 3 .
- the first semiconductor chip 1 is put on the die pad bottom surface 3 .
- the first semiconductor chip 1 , the first adhesive layer 4 and the die pad 3 are heated from the lower side of the first semiconductor chip 1 .
- the adhesive layer 4 fixes the first semiconductor chip 1 on the die pad 3 after this heat treatment.
- the insulating or conductive adhesive layer 5 (second adhesive layer) is formed over the top surface of the die pad 3 .
- the second semiconductor chip 2 is put over the die pad top surface 3 .
- the second semiconductor chip 2 , the second adhesive layer 5 and the die pad 3 are heated from the lower side of the first semiconductor chip 2 .
- the adhesive layer 5 fixes the second semiconductor chip 2 on the die pad 3 after this heat treatment.
- the second adhesive layer can be selected according to the needs, because the second adhesive layer is formed after the fixing of the first semiconductor chip. It can be selected in this method whether the second chip bottom surface must have potential or not even after the first semiconductor chip has fixed.
Abstract
A semiconductor device includes, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed, and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the first chip top surface is fixed on the die pad bottom surface, the second chip bottom surface is fixed on the die pad top surface.
Description
- The present invention relates to a semiconductor device, and to the method for manufacturing the same.
- FIG. 9 shows a schematic diagram of a conventional semiconductor device molded with resin. FIG. 10 shows a top-view of the semiconductor device. These drawings show a Quad Flat Package (QFP).
- This semiconductor device has a
first semiconductor chip 91, asecond semiconductor chip 92, adie pad 93, a firstadhesive layer 94, a secondadhesive layer 95,electrodes 96 on the first semiconductor chip,electrodes 97 on the second semiconductor chip,inner leads 98,metal wires package portion 912,outer leads 913, and apad support portion 914. Thesemiconductor chips die pad 93. - The die
pad 93 is lower than theinner leads 98 as shown in FIG. 9 and FIG. 10. The hanging portion of thedie pad 93 is bent, and the die pad and the inner leads are not in the same level. The bent portion is indicated byreference numeral 1011 in FIG. 10. This structure is called downset. The thickness t1 of the resin on thesemiconductor chip 92 is the same as the thickness t2 of the resin under thedie pad 93 in the conventional design. The resin is filled proportionally during transfer molding because the thickness of resin on thesemiconductor chip 92 and the thickness of resin under thedie pad 93 are the same. Therefore, a short-circuit of wires on thesemiconductor chip 91 and thesemiconductor chip 92 is prevented. The warp of the package is also prevented. - The
semiconductor chip 91 is fixed over the diepad 93 by the firstadhesive layer 94. Thesemiconductor chip 92 is fixed over thesemiconductor chip 91 by the secondadhesive layer 5. - The
electrodes inner leads 98 viametal wires electrodes 97 on thesemiconductor chip 92 are connected to theelectrodes 96 on thesemiconductor chip 91. After the wire bonding, a resin (for example, epoxy resin) is molded on semiconductor chips. After the forming of thepackage portion 12, theouter leads 13 are plated with solder. Theouter leads 13 are then transformed into a predetermined form. - An object of the present invention is to provide a semiconductor device and the method for manufacturing the same that do not need a downset process. Therefore the yield is improved during the formation of a lead frame.
- According to an embodiment of this invention, a semiconductor device comprises, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the top surface of the first semiconductor chip is fixed on the bottom surface of the die pad, the bottom surface of the second semiconductor chip is fixed on the top surface of the die pad.
- A method for manufacturing the semiconductor device comprises forming a first adhesive layer on a bottom surface of a die pad, forming a second adhesive layer on a top surface of the die pad, fixing a top surface of a first semiconductor chip on the first adhesive layer, fixing a bottom surface of a second semiconductor chip which is smaller than the first semiconductor chip on the second adhesive layer.
- FIG. 1 shows a cross sectional view of a semiconductor device of a first preferred embodiment.
- FIG. 2 shows a perspective diagram from the top view of the semiconductor device in the first preferred embodiment.
- FIG. 3 shows a cross sectional view of a semiconductor device of a second preferred embodiment.
- FIG. 4 shows a perspective diagram from the top view of the semiconductor device of the second preferred embodiment.
- FIG. 5 shows a cross sectional view of the method for manufacturing the semiconductor device of the third p referred embodiment.
- FIG. 6 shows a cross sectional view of the method for manufacturing a semiconductor device of the fourth preferred embodiment.
- FIG. 7 shows a cross sectional view of the method for manufacturing a semiconductor device of the fifth preferred embodiment.
- FIG. 8 shows a cross sectional view diagram of the method for manufacturing a semiconductor device of the sixth preferred embodiment.
- FIG. 9 shows a cross sectional view of a conventional semiconductor device.
- FIG. 10 shows a top view of the conventional semiconductor device.
- Preferred embodiments are described below using drawings.
- FIG. 1 shows a cross sectional view of the semiconductor device of a first preferred embodiment. FIG. 2 shows a perspective diagram from the top view of the semiconductor device in the first embodiment.
- This semiconductor device has a
first semiconductor chip 1, asecond semiconductor chip 2, adie pad 3, a firstadhesive layer 4, a secondadhesive layer 5, electrodes 6 on the first semiconductor chip,electrodes 7 on the second semiconductor chip,inner leads 8,metal wires package portion 12,outer leads 13, and apad support portion 14. The package is not limited to the drawings. For example, theinner leads 8 can be formed with an interconnection on Ball Grid Array (BGA) substrate. - The die
pad 3 for mounting a semiconductor chip is not downset. Thepad support portion 14 is not bent. Therefore, thedie pad 3 and theinner leads 8 are formed on the same level. The secondadhesive layer 5 is formed on the top surface of the die pad 3 (the die pad top surface) and the firstadhesive layer 4 is formed on the bottom surface of the die pad 3 (die pad bottom surface). That is to say, thedie pad 3 is disposed between the first and second adhesive layers. - The
first semiconductor chip 1 is fixed on the firstadhesive layer 4. The top surface of the first semiconductor chip 1 (first chip top surface) touches the firstadhesive layer 4, and the first chip top surface is the main surface on which the circuits and electrodes are formed. - The
second semiconductor chip 2 is fixed on the secondadhesive layer 5. The bottom surface of the second semiconductor chip 2 (second chip bottom surface) touches the secondadhesive layer 5, and the circuits are not formed on this bottom surface. - The electrodes6 on the first semiconductor chip are connected to
inner leads 8 viametal wires 9. Theelectrodes 7 on the second semiconductor chip are connected toinner leads 8 viametal wires 10. Some electrodes 6 on thefirst semiconductor chip 1 are connected to theelectrodes 7 on thesecond semiconductor chip 2 viawires 11. The electrical signal of thesemiconductor chips electrodes 6, 7,wires inner leads 8, andouter leads 13. - The
package portion 12 is formed by molding resin (for example, epoxy resin) on predetermined portion of the semiconductor device. - The total thickness of the first
adhesive layer 4 plus thefirst semiconductor chip 1 is the same as the total thickness of the secondadhesive layer 5 plus thesecond semiconductor chip 2. Therefore, The thickness t1 of the resin on thesecond semiconductor chip 2 is the same as the thickness t2 of the resin under thefirst semiconductor chip 1. - The die
pad 3 is disposed between thefirst semiconductor chip 1 and thesecond semiconductor chip 2. Therefore, the hanging portion of the die pad is not have to be bent. - The
first semiconductor chip 1 is wider than thesecond semiconductor chip 2 and thedie pad 3 in this embodiment. The electrodes 6 on thefirst semiconductor chip 1 are disposed outside of the region that is defined by the edge of thesecond semiconductor chip 2. The electrodes 6 on the first semiconductor chip and theelectrodes 7 on the second semiconductor chip do mot overlap from the top view as shown in FIG. 2. - The first chip
top surface 1 is fixed on the firstadhesive layer 4, and the secondchip bottom surface 2 is fixed on the secondadhesive layer 5. Therefore, all of theelectrodes 6, 7 are not covered with thedie pad 3. It is desirable that the difference of the size between thefirst semiconductor chip 1 and thesecond semiconductor chip 2 is at least 0.3 mm in each side. This is a minimum width to form an interconnecting wire between the electrodes 6 on thefirst semiconductor chip 1 and theelectrodes 7 on thesecond semiconductor chip 2. - The
electrodes 7 on the second semiconductor chip and the electrodes 6 on thefirst semiconductor chip 1 do not overlap. Therefore, all of the wire bonding to connect electrodes 6 andelectrodes 7, electrodes 6 andinner lead 8, andelectrodes 7 andinner lead 8 are performed in the same step. The wire bonding is performed from the same side (die pad top surface side) in the first preferred embodiment, and there is no wire connected by wire bonding from another side (die pad bottom surface side), and the wire, which has a loop summit at the die pad bottom surface, does not exist. Therefore, the thickness of the semiconductor device can be decreased. - The die pad
top surface 3 is preferably wider than the bottom surface of thesemiconductor chip 2. The die padbottom surface 3 is preferably smaller than the top surface of thesemiconductor chip 1. - In the first preferred embodiment, the
adhesive layer 5 is prevented from running onto the top surface of thesemiconductor chip 1 because thedie pad 3 is wider than thesemiconductor chip 2, when thesemiconductor chip 2 is fixed. - An insulating adhesive is used as the
adhesive layer 4 because theadhesive layer 4 bonds the first chip top surface, which is formed with circuit, to thedie pad 3. - A conductive adhesive (for example solder paste) can be used as the
adhesive layer 5 because the secondchip bottom surface 2 is fixed on thedie pad 3. Therefore, electric potential can be applied to the second semiconductor chip accordingly. For example, a semiconductor device, which has a logic semiconductor chip and a memory semiconductor device, is suitable for use a conductive adhesive as theadhesive layer 5. A certain potential should be applied to the substrate of a conventional memory semiconductor chip in order to stabilize an operation, on the other hand, there are many cases that the logic semiconductor chip does not need some potential at its substrate, therefore, the logic semiconductor chip can be used as the first semiconductor chip and the memory semiconductor chip can be used as the second semiconductor chip in the first preferred embodiment. - There are some effects described below according to this preferred embodiment.
- This semiconductor device has a simple structure without downset. Therefore the yield of the lead-frame is improved during manufacturing, and the cost of manufacturing is declined.
- The transformation of the lead frame is decreased during the carry and the molding. Because this semiconductor device does not have an downset structure. Therefore the yield of the assembly process is improved, and the cost of manufacturing is declined.
- There is a
die pad 3 between thefirst semiconductor chip 1 and thesecond semiconductor chip 2. Therefore, the noises between thesemiconductor chips - The area of the
die pad 3 relates to the effect of noise reduction. - The second preferred embodiment is described below.
- FIG. 3 shows a cross sectional view of the semiconductor device of the second preferred embodiment. FIG. 4 shows a perspective diagram from the top view of the semiconductor device in the second embodiment. The same reference numerals are applied for the elements those are described in the first embodiment.
- The
die pad 3 of the second preferred embodiment is not downset either. - The area of the
die pad 3 is much smaller than the areas of thefirst semiconductor chip 1 and thesecond semiconductor chip 2. It is desirable that the area of thedie pad 3 is smaller than half of the top surface area of thefirst semiconductor chip 1. The first chiptop surface 1 is fixed on thedie pad 3. - The
die pad 3 is smaller than thesemiconductor chips first semiconductor chip 1 and thedie pad 3 shrinks because the area of thedie pad 3 is small. Therefore the stress and the damage on the surface of the first semiconductor chip are decreased. - Consequently, this semiconductor device of the embodiment does not need a coating layer on the first chip
top surface 1 because the passivation layer is enough to protect the top surface from damage. The coating process is reduced and the cost of manufacturing declines. - The amount of adhesive required to fix the semiconductor chips is reduced because the area of the
die pad 3 is small. It also becomes easy to spread the adhesive uniformly on the total surface of thedie pad 3. Therefore the adhesive strength is enough to fix each semiconductor chip. - The
electrodes 7 on the second semiconductor chip and the electrodes 6 on thefirst semiconductor chip 1 do not overlap in the same way as the first embodiment. Therefore, all of the wire bonding are performed substantially in the same step. - In other words, all of the wire bonding are performed without a step of turning over the semiconductor device.
- The conductive adhesive can be used as the
adhesive layer 5 in the second embodiment in the same way as the first embodiment. Therefore, the logic semiconductor chip can be used as the first semiconductor chip and the memory semiconductor chip can be used as the second semiconductor chip in the first preferred embodiment. - FIGS.5A-5D show cross sectional views of the method for manufacturing the semiconductor device according to the third preferred embodiment. The same reference numerals are applied for the elements those are described in the first preferred embodiment.
- The
die pad 3, which is not downset, is prepared as shown in FIG. 5A. The insulating adhesive layer (first adhesive layer) 4 is formed on a bottom surface of thedie pad 3. The insulating or conductive adhesive layer 5 (second adhesive layer) is formed over a top surface of thedie pad 3. Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape may be used as these adhesive layers. These adhesive layers preferably have some viscosity before hardening. This viscosity allows a semiconductor chip to be aligned on thedie pad 3. - The
first semiconductor chip 1 is put on the die pad bottom surface as shown in FIG. 5B. Thefirst semiconductor chip 1, the firstadhesive layer 4 and thedie pad 3 are heated from the lower side of thefirst semiconductor chip 1. Theadhesive layer 4 fixes thefirst semiconductor chip 1 on thedie pad 3 after this heat treatment. - The
second semiconductor chip 2 is put over the die padtop surface 3 as shown in FIG. 5C. Thesecond semiconductor chip 2, the secondadhesive layer 5 and thedie pad 3 are heated from the lower side of thefirst semiconductor chip 2. Theadhesive layer 5 fixes thesecond semiconductor chip 2 on thedie pad 3 after this heat treatment. - The final hardening of the adhesive layers is performed, and the semiconductor chips are perfectly fixed on the
die pad 3. This fixing process is called a die bonding process.Electrodes 6, 7 on thesemiconductor chips inner leads 8 or another electrode viametal wire - There are some effects described below according to this preferred embodiment.
- The manufacturing step is simplified because the downset process is lessened. Therefore the yield of the lead-frame is improved during manufacturing, and the cost of manufacturing is reduced.
- The adhesive layers are formed before the semiconductor chips are put on the
die pad 3. Therefore the spread of the adhesive layer can be easily controlled when the semiconductor chips are pressed on thedie pad 3. The possibility that theadhesive layer 5 runs onto the top surface of thesemiconductor chip 1 is decreased. Therefore the distance between the edge of thefirst semiconductor chip 1 and the edge of thesecond semiconductor chip 2 is minimized. This minimized distance means the shortest distance that the electrodes 6 on thefirst semiconductor chip 1 can be connected to theelectrodes 7 on thesecond semiconductor chip 2 via metal wire. - The wire bonding ban be performed from the same side (die pad top surface side) and in the same step in the first preferred embodiment. The wire, which has a loop summit at the die pad bottom surface, does not exist. Therefore, turning over the semiconductor device does not have to be performed to perform wire bonding of another side.
- FIG. 6 shows a cross sectional view of the method for manufacturing the semiconductor device of a fourth preferred embodiment. The same reference numerals are applied for the elements those are described in the first preferred embodiment.
- The
die pad 3, which is not downset, is prepared. The insulating adhesive layer 4 (first adhesive layer) is formed on a bottom surface of thedie pad 3. The insulating or conductive adhesive layer 5 (second adhesive layer) is formed on a top surface of thedie pad 3. Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape may be used as these adhesive layers. These adhesive layers have some viscosity before hardening. This viscosity allows aligning a semiconductor chip on thedie pad 3. - The first adhesive layer64 and the second adhesive layer 65 are partly formed on each surface in this embodiment. The portion on which the first adhesive layer 64 is formed in the die pad bottom surface does not correspond to the portion on which the second adhesive layer 65 is formed on the die pad top surface.
- For example, thermosetting adhesive is used as the adhesive layers64, 65. When the
first semiconductor chip 1 is fixed, only the first portion, which the first adhesive layer 64 is formed on, are heated. The retained heat does not have an influence on the second adhesive layer 65. Therefore the second adhesive layer 65 is protected from the changing of the viscosity property. - The method of manufacturing of the fourth embodiment is described below. This method is approximately the same as the third embodiment.
- The adhesive layers64, 65 are formed on each surface of the
die pad 3 as described above. - The
first semiconductor chip 1 is put on the die pad bottom surface. The first adhesive layer 64 and the portions, those preferably corresponds to the first adhesive layer 64 in thefirst semiconductor chip 1 and thedie pad 3, are heated. The adhesive layer 64 fixes thefirst semiconductor chip 1 on thedie pad 3 after this heat treatment. - The
second semiconductor chip 2 is put over the die padtop surface 3. Thesecond semiconductor chip 2, the second adhesive layer 65 and thedie pad 3 are heated from the lower side of thefirst semiconductor chip 1. The second adhesive layer 65 fixes thesecond semiconductor chip 2 on thedie pad 3 after this heat treatment. - The final hardening of the adhesive layers is performed, and the first and second semiconductor chips are perfectly fixed on the
die pad 3. - The second adhesive layer65 and the corresponding portion in the
die pad 3 are not heated directory during the heat treatment to fix thefirst semiconductor chip 1. Therefore the second adhesive layer 65 is protected from the changing of the viscosity property. - FIG. 7 shows a cross sectional view of the method for manufacturing the semiconductor device of a fifth preferred embodiment. The same numerals are applied for the elements those are described in the first embodiment.
- The
die pad 3, which is not downset, is prepared. The insulating adhesive layer 74 (first adhesive layer) is formed on the bottom surface of thedie pad 3. The insulating or conductive adhesive layer 65 (second adhesive layer) is formed on the top surface of thedie pad 3. Thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape can be used as these adhesive layers 64, 65. These adhesive 64, 65 layers preferably have some viscosity before hardening. This viscosity allows a semiconductor chip to be aligned on thedie pad 3. - The softening (or hardening) temperature of the first adhesive layer74 is different from that of the second adhesive layer 75 in this embodiment.
- For example, the same thermoplastic adhesive can be used as the adhesive layers. The
first semiconductor chip 1 is fixed before thesecond semiconductor chip 2 is fixed. Then the second adhesive layer is softened by heating from the lower side of thefirst semiconductor chip 1. The firstadhesive layer 1 may be softened during this second heat treatment. The softening of the first adhesive layer 74 during the second heat treatment is not preferable to fix the first semiconductor chip tightly and precisely. If the softening temperature of the first adhesive layer is higher than that of the second adhesive layer, this problem does not occur. - For example, if the softening temperature of the first adhesive layer74 is 100° C. and the softening temperature of the second adhesive layer is 50° C. the fixing would be performed more tightly.
- Therefore using different adhesive layers respectively having different softening temperature for each surface makes the fixing of the semiconductor chips more precise and tight.
- The method of manufacturing of the fifth embodiment using thermoplastic adhesive as an example is described below in order to more fully illustrate this embodiment. This is the opposite example of thermo characteristic to the above example. This method is substantially similar to the third embodiment.
- The
die pad 3, which is not downset, is prepared. The insulating adhesive layer 74 (first adhesive layer) is formed on bottom surface of thedie pad 3. The softening temperature of the first adhesive layer is about 50° C. The insulating or conductive adhesive layer 75 (second adhesive layer) is formed on top surface of thedie pad 3. The softening temperature of the second adhesive layer is about 100° C. - The
first semiconductor chip 1 is put on the die padbottom surface 3. Thefirst semiconductor chip 1, the firstadhesive layer 4 and thedie pad 3 are heated at the temperature of 50° C. from the lower side of thefirst semiconductor chip 1. Theadhesive layer 4 is hardened because this is a thermosetting adhesive, and it fixes thefirst semiconductor chip 1 on thedie pad 3 after this heat treatment. The second adhesive layer is not hardened during this heat treatment because softened temperature is higher than about 50° C. - The
second semiconductor chip 2 is put over the die padtop surface 3. Thesecond semiconductor chip 2, the secondadhesive layer 5 and thedie pad 3 are heated at the temperature of about 100° C. from the lower side of thefirst semiconductor chip 2. Theadhesive layer 4 is hardened and it fixes thefirst semiconductor chip 1 on thedie pad 3 after this heat treatment. - The final hardening of the adhesive layers is performed, and the semiconductor chips are perfectly fixed on the
die pad 3. - FIG. 8 shows a cross sectional view of the method for manufacturing the semiconductor device of the sixth preferred embodiment. The same reference numerals are applied for the elements those are described in the first embodiment.
- The featuring point of this embodiment is that the second
adhesive layer 5 is formed after the first semiconductor chip is fixed. One of thermosetting adhesive paste, thermoplastic adhesive paste, thermosetting adhesive tape, or thermoplastic adhesive tape are preferably used as adhesive layers. - The
die pad 3, which is not downset, is prepared. The insulating adhesive layer 84 (first adhesive layer) is formed on bottom surface of thedie pad 3. - The
first semiconductor chip 1 is put on the die padbottom surface 3. Thefirst semiconductor chip 1, the firstadhesive layer 4 and thedie pad 3 are heated from the lower side of thefirst semiconductor chip 1. Theadhesive layer 4 fixes thefirst semiconductor chip 1 on thedie pad 3 after this heat treatment. - Then, The insulating or conductive adhesive layer5 (second adhesive layer) is formed over the top surface of the
die pad 3. - The
second semiconductor chip 2 is put over the die padtop surface 3. Thesecond semiconductor chip 2, the secondadhesive layer 5 and thedie pad 3 are heated from the lower side of thefirst semiconductor chip 2. Theadhesive layer 5 fixes thesecond semiconductor chip 2 on thedie pad 3 after this heat treatment. - The final hardening of the adhesive layers is performed, and the semiconductor chips are perfectly fixed on the
die pad 3. This fixing process is called die bonding process. Electrodes of the semiconductor chips are electrically connected to inner leads or another electrode viametal wire - In this embodiment, the second adhesive layer can be selected according to the needs, because the second adhesive layer is formed after the fixing of the first semiconductor chip. It can be selected in this method whether the second chip bottom surface must have potential or not even after the first semiconductor chip has fixed.
- This invention is not limited by these embodiments.
Claims (21)
1. A semiconductor device comprising:
a die pad having a die pad top surface and a die pad bottom surface;
a first semiconductor chip having a first chip top surface and a first chip bottom surface, and the first chip top surface having a first plurality of electrodes thereon,
a second semiconductor chip having a second chip top surface and a second chip bottom surface, the second chip top surface having a second plurality of electrodes thereon, and the second semiconductor chip being smaller than the first semiconductor chip;
wherein the first chip top surface is fixed under the die pad bottom surface, the second chip bottom surface is fixed over the die pad top surface.
2. The semiconductor device according to , wherein the second semiconductor chip is smaller than the die pad.
claim 1
3. The semiconductor device according to , wherein the area of the die pad bottom surface is smaller than half of the area of the first chip top surface.
claim 1
4. The semiconductor device according to , wherein the first semiconductor chip is a logic semiconductor chip, and the second semiconductor chip is a memory semiconductor chip.
claim 1
5. The semiconductor device according to , further comprising inner leads, wherein the inner leads and the die pad are formed substantially at the same level.
claim 1
6. The semiconductor device according to , wherein the first plurality of electrodes are disposed on the outside of a region that is defined by an edge of the second semiconductor chip.
claim 1
7. The semiconductor device according to , wherein the first plurality of electrodes are disposed on the outside of the die pad.
claim 1
8. The semiconductor device according to , further comprising a metal wire which electrically connects at least one of the first plurality of electrodes to at least one of the second plurality of electrodes.
claim 6
9. The semiconductor device according to , further comprising
claim 3
a first metal wire which connects at least one of the first plurality of electrodes to the inner leads;
a second metal wire which connects at least one of the second plurality of electrodes to the inner leads.
10. The semiconductor device according to , wherein the first metal wire and the second metal wire are formed in a side of the die pad top surface.
claim 8
11. The semiconductor device according to , further comprising:
claim 1
a molding resin that molds the first semiconductor chip, the second semiconductor chip, and the die pad,
wherein the thickness of the resin over the second semiconductor chip is substantially the same as the thickness of the resin under the first semiconductor chip.
12. A method for manufacturing the semiconductor device comprising
forming a first adhesive layer over a die pad bottom surface;
forming a second adhesive layer over a die pad top surface;
fixing a top surface of a first semiconductor chip on the first adhesive layer, the top surface of the first semiconductor chip having a first plurality of electrodes thereon, and
fixing a bottom surface of a second semiconductor chip, which is smaller than the first semiconductor chip, on the second adhesive layer, a top surface of the second semiconductor chip having a second plurality of electrodes thereon.
13. The method according to , wherein forming the second adhesive layer is performed after fixing the first semiconductor layer.
claim 12
14. The method according to , wherein the first adhesive layer and the second adhesive layer have a thermosetting characteristic.
claim 12
15. The method according to , wherein a second hardening temperature of the second adhesive layer is higher than a first hardening temperature of the first adhesive layer.
claim 14
16. The method according to claim. 12, wherein the first adhesive layer and the second adhesive layer have a thermoplastic characteristic.
17. The method according to , wherein a second softening temperature of the second adhesive layer is lower than a first softening temperature of the first adhesive layer.
claim 16
18. The method according to , wherein the first adhesive layer and the second adhesive layer are partly formed on the die pad top surface and the die pad bottom surface, a first portion on the die pad bottom surface, which corresponds to the first adhesive layer is different from a second portion on the die pad top surface which corresponds to the second adhesive layer.
claim 14
19. The method according to , wherein the first adhesive layer and the second adhesive layer are partly formed on the die pad top surface and the die pad bottom surface, a first portion on the die pad bottom surface, which corresponds to the first adhesive layer is different from a second portion on the die pad top surface which corresponds to the second adhesive layer.
claim 16
20. The method according to , further comprising;
claim 12
connecting some of the first plurality of electrodes on the first semiconductor chip to some of the second plurality of electrodes on the second semiconductor chip,
wherein the electrodes on the first semiconductor chip are disposed on the outside of the region that is defined by an edge of the second semiconductor chip.
21. The method according to , further comprising;
claim 12
first connecting at least one of the first plurality of electrodes on the first semiconductor chip to at least one of inner leads;
second connecting at least one of the second plurality of electrodes on the second semiconductor chip to at least one of inner leads,
wherein said first connecting and second connecting is performed subsequently in the same step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/201,275 US6777264B2 (en) | 2000-03-07 | 2002-07-24 | Method of manufacturing a semiconductor device having a die pad without a downset |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000062268A JP3429245B2 (en) | 2000-03-07 | 2000-03-07 | Semiconductor device and manufacturing method thereof |
KR062268/2000 | 2000-03-07 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/201,275 Division US6777264B2 (en) | 2000-03-07 | 2002-07-24 | Method of manufacturing a semiconductor device having a die pad without a downset |
Publications (1)
Publication Number | Publication Date |
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US20010023994A1 true US20010023994A1 (en) | 2001-09-27 |
Family
ID=18582300
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US09/799,803 Abandoned US20010023994A1 (en) | 2000-03-07 | 2001-03-07 | Semiconductor device and the method for manufacturing the same |
US10/201,275 Expired - Fee Related US6777264B2 (en) | 2000-03-07 | 2002-07-24 | Method of manufacturing a semiconductor device having a die pad without a downset |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US10/201,275 Expired - Fee Related US6777264B2 (en) | 2000-03-07 | 2002-07-24 | Method of manufacturing a semiconductor device having a die pad without a downset |
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US (2) | US20010023994A1 (en) |
JP (1) | JP3429245B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20020043717A1 (en) * | 2000-10-16 | 2002-04-18 | Toru Ishida | Semiconductor device |
US20020125556A1 (en) * | 2001-03-09 | 2002-09-12 | Oh Kwang Seok | Stacking structure of semiconductor chips and semiconductor package using it |
US7157790B2 (en) | 2002-07-31 | 2007-01-02 | Microchip Technology Inc. | Single die stitch bonding |
US7326594B2 (en) | 2002-07-31 | 2008-02-05 | Microchip Technology Incorporated | Connecting a plurality of bond pads and/or inner leads with a single bond wire |
US7675180B1 (en) | 2006-02-17 | 2010-03-09 | Amkor Technology, Inc. | Stacked electronic component package having film-on-wire spacer |
US8129849B1 (en) | 2006-05-24 | 2012-03-06 | Amkor Technology, Inc. | Method of making semiconductor package with adhering portion |
EP2104142B1 (en) * | 2008-03-18 | 2016-11-02 | MediaTek Inc. | Semiconductor chip package |
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JP4637380B2 (en) * | 2001-02-08 | 2011-02-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US7816182B2 (en) * | 2004-11-30 | 2010-10-19 | Stmicroelectronics Asia Pacific Pte. Ltd. | Simplified multichip packaging and package design |
US20070290332A1 (en) * | 2006-06-15 | 2007-12-20 | Powertech Technology Inc. | Stacking structure of chip package |
US7919848B2 (en) * | 2007-08-03 | 2011-04-05 | Stats Chippac Ltd. | Integrated circuit package system with multiple devices |
US7911040B2 (en) * | 2007-12-27 | 2011-03-22 | Stats Chippac Ltd. | Integrated circuit package with improved connections |
JP2018107394A (en) * | 2016-12-28 | 2018-07-05 | 新光電気工業株式会社 | Wiring board, electronic component device and manufacturing method thereof |
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US5012323A (en) * | 1989-11-20 | 1991-04-30 | Micron Technology, Inc. | Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe |
JPH053284A (en) | 1991-06-25 | 1993-01-08 | Sony Corp | Resin-sealed semiconductor device |
JPH0555452A (en) | 1991-08-27 | 1993-03-05 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
JPH05109975A (en) | 1991-10-14 | 1993-04-30 | Hitachi Ltd | Resin-sealed type semiconductor device |
US6046072A (en) * | 1993-03-29 | 2000-04-04 | Hitachi Chemical Company, Ltd. | Process for fabricating a crack resistant resin encapsulated semiconductor chip package |
US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
JP3266815B2 (en) * | 1996-11-26 | 2002-03-18 | シャープ株式会社 | Method for manufacturing semiconductor integrated circuit device |
TW384304B (en) * | 1996-12-26 | 2000-03-11 | Tomoegawa Paper Co Ltd | Adhesive tape for electronic parts |
JP3077668B2 (en) * | 1998-05-01 | 2000-08-14 | 日本電気株式会社 | Semiconductor device, lead frame for semiconductor device, and method of manufacturing the same |
US6552437B1 (en) * | 1998-10-14 | 2003-04-22 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
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2000
- 2000-03-07 JP JP2000062268A patent/JP3429245B2/en not_active Expired - Fee Related
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2001
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-
2002
- 2002-07-24 US US10/201,275 patent/US6777264B2/en not_active Expired - Fee Related
Cited By (13)
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US7199469B2 (en) * | 2000-10-16 | 2007-04-03 | Renesas Technology Corp. | Semiconductor device having stacked semiconductor chips sealed with a resin seal member |
US20020043717A1 (en) * | 2000-10-16 | 2002-04-18 | Toru Ishida | Semiconductor device |
US7485490B2 (en) | 2001-03-09 | 2009-02-03 | Amkor Technology, Inc. | Method of forming a stacked semiconductor package |
US20020125556A1 (en) * | 2001-03-09 | 2002-09-12 | Oh Kwang Seok | Stacking structure of semiconductor chips and semiconductor package using it |
US7863723B2 (en) | 2001-03-09 | 2011-01-04 | Amkor Technology, Inc. | Adhesive on wire stacked semiconductor package |
US8143727B2 (en) | 2001-03-09 | 2012-03-27 | Amkor Technology, Inc. | Adhesive on wire stacked semiconductor package |
US7157790B2 (en) | 2002-07-31 | 2007-01-02 | Microchip Technology Inc. | Single die stitch bonding |
US7326594B2 (en) | 2002-07-31 | 2008-02-05 | Microchip Technology Incorporated | Connecting a plurality of bond pads and/or inner leads with a single bond wire |
US20080099893A1 (en) * | 2002-07-31 | 2008-05-01 | Microchip Technology Incorporated | Connecting a plurality of bond pads and/or inner leads with a single bond wire |
US7675180B1 (en) | 2006-02-17 | 2010-03-09 | Amkor Technology, Inc. | Stacked electronic component package having film-on-wire spacer |
US8072083B1 (en) | 2006-02-17 | 2011-12-06 | Amkor Technology, Inc. | Stacked electronic component package having film-on-wire spacer |
US8129849B1 (en) | 2006-05-24 | 2012-03-06 | Amkor Technology, Inc. | Method of making semiconductor package with adhering portion |
EP2104142B1 (en) * | 2008-03-18 | 2016-11-02 | MediaTek Inc. | Semiconductor chip package |
Also Published As
Publication number | Publication date |
---|---|
US6777264B2 (en) | 2004-08-17 |
JP2001250833A (en) | 2001-09-14 |
JP3429245B2 (en) | 2003-07-22 |
US20030020177A1 (en) | 2003-01-30 |
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