US20010026985A1 - Fabrication method of submicron gate using anisotropic etching - Google Patents
Fabrication method of submicron gate using anisotropic etching Download PDFInfo
- Publication number
- US20010026985A1 US20010026985A1 US09/749,785 US74978500A US2001026985A1 US 20010026985 A1 US20010026985 A1 US 20010026985A1 US 74978500 A US74978500 A US 74978500A US 2001026985 A1 US2001026985 A1 US 2001026985A1
- Authority
- US
- United States
- Prior art keywords
- emitter
- region
- dummy
- gate
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000005530 etching Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 30
- 125000005842 heteroatom Chemical group 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
Definitions
- the present invention relates to a submicron gate electrode of a semiconductor device, and more particularly to a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process.
- An exemplary one of such networks is a network for local multipoint distribution services in which audio, video conference, and digital signals are simultaneously transmitted at a bandwidth of 1.3 GHz within a service area of 2 to 7 Km in radius, using a 28 GHz “Ka-band”.
- Ka-band a 28 GHz
- this technique requires an expensive exposure process, such as an electron beam writing process or a stepped exposure process, or a complex process involving a formation of sidewalls, to form a self-aligned submicron gate.
- an expensive exposure process such as an electron beam writing process or a stepped exposure process, or a complex process involving a formation of sidewalls, to form a self-aligned submicron gate.
- the present invention has been made in view of the above mentioned problems, and an object of the present invention is to provide a submicron gate fabrication method capable of fabricating a reliably self-aligned submicron gate using a simplified process.
- the present invention provides a method for fabricating a submicron gate comprising the steps of: (a) laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively; (b) defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner; (c) selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist; and (d) depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate.
- a contact metal is deposited over the resulting structure with the gate, thereby self-aligning the gate.
- the present invention also provides an effect of reducing the distance between a base and an emitter as much as possible, thereby achieving a reduction in base resistance, in that it enables a self alignment using a V-shaped submicron gate.
- FIG. 1 is a cross-sectional view illustrating an essential laminated structure according to the embodiment of the present invention
- FIG. 2 is a cross-sectional view illustrating a structure obtained after patterning a photoresist ( 21 ) using a conventional contact aligner;
- FIG. 3 is a cross-sectional view illustrating a structure obtained after selectively wet-etching a first InGaAs layer ( 12 );
- FIG. 4 is a cross-sectional view illustrating a structure obtained after selectively wet-etching a first InP layer ( 13 );
- FIG. 5 is a cross-sectional view illustrating a structure obtained after depositing a metal ( 51 ) over the entire upper surface of the structure shown in FIG. 4, for the formation of a gate;
- FIG. 6 is a cross-sectional view illustrating a structure obtained to have a V-shaped gate after lifting off the photoresist ( 21 );
- FIG. 7 is a cross-sectional view illustrating a structure obtained after sequentially removing the first InGaAs layer ( 12 ) and first InP layer ( 13 );
- FIG. 8 is a cross-sectional view illustrating a structure obtained after anisotropically wet-etching a second InGaAs layer ( 14 ) and a second InP layer ( 15 ) using the V-shaped gate ( 61 ), formed in a process of FIG. 7, as a mask; and
- FIG. 9 is a cross-sectional view illustrating a final device produced after a self-alignment of the gate.
- FIGS. 1 to 9 illustrate sequential steps of a submicron gate fabrication and self-alignment procedure according to an embodiment of the present invention, respectively.
- FIG. 1 illustrates an essential laminated structure according to the embodiment of the present invention in which a dummy emitter is laminated on a general InP/InGaAs heterojunction bipolar transistor (HBT) structure.
- HBT heterojunction bipolar transistor
- this structure is formed by laminating InGaAs layers ( 12 , 14 , and 16 ), and InP layers ( 13 and 15 ) over a Fe-doped InP substrate ( 11 ) in an alternating fashion, using a laminated growth equipment such as MOCVD or MBE.
- the second InP layer ( 15 ) defines an emitter region, the second InGaAs layer ( 14 ) an emitter cap region, and the third InGaAs layer ( 16 ) a base region, respectively.
- the first InGaAs layer ( 12 ) and the first InP layer ( 13 ) define dummy emitter regions, respectively.
- the first InP layer ( 13 ) has a thickness H1 more than the thickness H2 of the second InP layer ( 15 ) in order to obtain a self-aligned structure. That is, this thickness relation is adapted to satisfy a condition of “L2 ⁇ L3 ⁇ L1” in FIG. 8.
- a line having a width L1 of about 1 ⁇ m is then patterned on the structure of FIG. 1 using a photoresist ( 21 ), as shown in FIG. 2.
- the line width L1 is limited by the resolution of a contact aligner.
- the first InGaAs layer ( 12 ) is selectively etched under the condition in which the patterned photoresist ( 21 ) formed at the step of FIG. 2 is used as a mask, as shown in FIG. 3.
- H 3 PO 4 :H 2 O 2 :H 2 O is used as an etchant in order to achieve the selective etching of the first InGaAs layer ( 12 ) without any substantial influence on the first InP layer ( 13 ).
- the first InP layer ( 13 ) is then etched, as shown in FIG. 4.
- HCl:H 3 PO 4 is used as an etchant in order to achieve the selective etching of the first InP layer ( 13 ) without any substantial influence on the first and second InGaAs layer ( 12 and 14 ).
- FIG. 4 it can be found that the first InP layer ( 13 ) exhibits anisotropic etch characteristics due to an etch selectivity difference resulting from a variation in lattice direction in the first InP layer ( 13 ). That is, the first InP layer ( 13 ) is not isotropically etched, but anisotropically etched in accordance with the variation in lattice direction, so that it has an inclined etch cross section.
- the etching of the first InP layer ( 13 ) is carried out under the condition in which the first InGaAs layer ( 12 ) is used as a mask, as shown in FIG. 4, it is begun from the region where the first InGaAs layer ( 12 ) is opened, and then anisotropically progressed along the depth of the first InP layer ( 13 ) so that the etch cross section of the first InP layer ( 13 ) has an inclination ⁇ .
- the etching of the first InP layer ( 13 ) is stopped by the second InGaAs layer ( 14 ), so that the second InGaAs layer ( 14 ) and the second InP layer ( 15 ) are hardly etched.
- the inclination ⁇ is determined by the kind, concentration, and temperature of the etchant used.
- a contact metal ( 51 ) is deposited over the entire upper surface of the structure obtained at the step of FIG. 4, using an electron-beam evaporator or a thermal evaporator, as shown in FIG. 5.
- the contact metal ( 51 ) has a V-shaped structure at a portion thereof deposited at the region where the first InP layer ( 13 ) is etched.
- the V-shaped structure of the contact metal ( 51 ) has an inclination corresponding to the inclination formed by the anisotropic etching of the first InP layer ( 13 ).
- the first InGaAs layer ( 12 ) and first InP layer ( 13 ) are selectively etched, thereby forming a gate ( 61 ) made of the remaining contact metal ( 51 ), as shown in FIG. 7.
- the gate ( 61 ) as a mask, the second InGaAs layer ( 14 ) and second InP layer ( 15 ) arranged beneath the gate ( 61 ) are then sequentially etched in accordance with an anisotropic wet etch process.
- H 3 PO 4 :H 2 O 2 :H 2 O is used as an etchant whereas HCl:H 3 PO 4 is used as an etchant for the first and second InP layers ( 13 and 15 ).
- an inclined structure made of the second InP layer ( 15 ) is obtained which has an inclination resulting from a variation in etch selectivity exhibited in the second InP layer ( 15 ).
- the bottom width of the inclined structure, L3, is also determined by the line width L1, the inclination ⁇ , and the thickness of the second InP layer ( 15 ), H2.
- the gate ( 61 ) has a self-aligned structure in that its region includes the region defined by L3.
- a contact metal ( 91 ) is deposited over the structure obtained after the process of FIG. 8, for a self-alignment of the gate, as shown in FIG. 9.
- the fabrication of a submicron gate is carried out using the existing exposure process such as an anisotropic wet etch process without use of any separate equipment. Accordingly, it is possible to simplify the fabrication of the submicron gate, thereby achieving a reduction in the manufacturing costs.
- the present invention also provides an effect of reducing the distance between a base and an emitter as much as possible, thereby achieving a reduction in base resistance, in that it enables a self-alignment using a V-shaped submicron gate.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a submicron gate electrode of a semiconductor device, and more particularly to a method for fabricating a self-aligned submicron gate electrode using an anisotropic etching process.
- 2. Description of the Related Art
- Remarkable development recently made in radio communication fields has resulted in an increased demand for ultrahigh broadband communication networks. An exemplary one of such networks is a network for local multipoint distribution services in which audio, video conference, and digital signals are simultaneously transmitted at a bandwidth of 1.3 GHz within a service area of 2 to 7 Km in radius, using a 28 GHz “Ka-band”. In order to construct such an ultrahigh broadband communication network, it is very important to develop ultrahigh-frequency devices operating the above mentioned frequency band while achieving a miniature and high performance of devices. To this end, active research efforts have been made. In particular, devices including submicron gates have been highlighted.
- Conventional techniques associated with submicron gates are disclosed in U.S. Pat. No. 5,288,645 (entitled “Method of making a mushroom-shaped gate electrode of semiconductor device), and U.S. Pat. No. 5,053,348 (entitled “Fabrication of self-aligned, T-gate HEMT”). However, these techniques require an expensive exposure process, such as an electron beam writing process or a stepped exposure process, to form a submicron gate. Furthermore, these techniques involve execution of a number of semiconductor processes including repeated exposure, deposition and etching. In order to obtain a desired self-alignment of the submicron gate, diverse semiconductor processes for forming, for example, sidewalls, should be conducted.
- Another conventional technique is known in association with submicron gates. For example, the following references discloses a method in which an electron beam writing process is repeatedly used to form a submicron gate, and sidewalls are formed using a dielectric material to obtain a self-alignment of the submicron gate.
- [Reference]
- 1. A dielectric-defined process for the formation of T-gate field-effect transistors. G. M. Metze. IEEE MGWL. Vol. 1, No. 8, August 1991.
- 2. High-Frequency low power IC's in a scaled submicrometer HBT technology. IEEE MTT. Vol. 45, No. 12, December 1997.
- However, this technique requires an expensive exposure process, such as an electron beam writing process or a stepped exposure process, or a complex process involving a formation of sidewalls, to form a self-aligned submicron gate. As a result, there is a drawback of an increase in the manufacturing costs.
- Therefore, the present invention has been made in view of the above mentioned problems, and an object of the present invention is to provide a submicron gate fabrication method capable of fabricating a reliably self-aligned submicron gate using a simplified process.
- In order to accomplish this object, the present invention provides a method for fabricating a submicron gate comprising the steps of: (a) laminating a dummy emitter defining a dummy emitter region over a heterojunction bipolar transistor structure including layers sequentially formed over a semiconductor substrate to define a base region, an emitter region, and an emitter cap region, respectively; (b) defining a line having a width of about 1 micron on the dummy emitter by use of a photoresist while using a contact aligner; (c) selectively anisotropic etching the dummy emitter at a region where the line is defined, to allow the dummy emitter to have an etched portion having a bottom surface with a width less than the width of the line defined by the photoresist; and (d) depositing a contact metal on the etched portion of the dummy emitter, thereby forming a gate.
- A contact metal is deposited over the resulting structure with the gate, thereby self-aligning the gate.
- In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter as much as possible, thereby achieving a reduction in base resistance, in that it enables a self alignment using a V-shaped submicron gate.
- The above objects, and other features and advantages of the present invention will become more apparent after a reading of the following detailed description when taken in conjunction with the drawings, in which:
- FIG. 1 is a cross-sectional view illustrating an essential laminated structure according to the embodiment of the present invention;
- FIG. 2 is a cross-sectional view illustrating a structure obtained after patterning a photoresist (21) using a conventional contact aligner;
- FIG. 3 is a cross-sectional view illustrating a structure obtained after selectively wet-etching a first InGaAs layer (12);
- FIG. 4 is a cross-sectional view illustrating a structure obtained after selectively wet-etching a first InP layer (13);
- FIG. 5 is a cross-sectional view illustrating a structure obtained after depositing a metal (51) over the entire upper surface of the structure shown in FIG. 4, for the formation of a gate;
- FIG. 6 is a cross-sectional view illustrating a structure obtained to have a V-shaped gate after lifting off the photoresist (21);
- FIG. 7 is a cross-sectional view illustrating a structure obtained after sequentially removing the first InGaAs layer (12) and first InP layer (13);
- FIG. 8 is a cross-sectional view illustrating a structure obtained after anisotropically wet-etching a second InGaAs layer (14) and a second InP layer (15) using the V-shaped gate (61), formed in a process of FIG. 7, as a mask; and
- FIG. 9 is a cross-sectional view illustrating a final device produced after a self-alignment of the gate.
- Now, a preferred embodiment of the present invention will be described in detail, with reference to the annexed drawings.
- FIGS.1 to 9 illustrate sequential steps of a submicron gate fabrication and self-alignment procedure according to an embodiment of the present invention, respectively.
- FIG. 1 illustrates an essential laminated structure according to the embodiment of the present invention in which a dummy emitter is laminated on a general InP/InGaAs heterojunction bipolar transistor (HBT) structure. As shown in FIG. 1, this structure is formed by laminating InGaAs layers (12, 14, and 16), and InP layers (13 and 15) over a Fe-doped InP substrate (11) in an alternating fashion, using a laminated growth equipment such as MOCVD or MBE.
- The second InP layer (15) defines an emitter region, the second InGaAs layer (14) an emitter cap region, and the third InGaAs layer (16) a base region, respectively. The first InGaAs layer (12) and the first InP layer (13) define dummy emitter regions, respectively. The first InP layer (13) has a thickness H1 more than the thickness H2 of the second InP layer (15) in order to obtain a self-aligned structure. That is, this thickness relation is adapted to satisfy a condition of “L2<L3<L1” in FIG. 8.
- In order to define a region where a gate is to be formed, a line having a width L1 of about 1 μm is then patterned on the structure of FIG. 1 using a photoresist (21), as shown in FIG. 2. The line width L1 is limited by the resolution of a contact aligner.
- Thereafter, the first InGaAs layer (12) is selectively etched under the condition in which the patterned photoresist (21) formed at the step of FIG. 2 is used as a mask, as shown in FIG. 3. H3PO4:H2O2:H2O is used as an etchant in order to achieve the selective etching of the first InGaAs layer (12) without any substantial influence on the first InP layer (13).
- The first InP layer (13) is then etched, as shown in FIG. 4. At this etching step, HCl:H3PO4 is used as an etchant in order to achieve the selective etching of the first InP layer (13) without any substantial influence on the first and second InGaAs layer (12 and 14). Referring to FIG. 4, it can be found that the first InP layer (13) exhibits anisotropic etch characteristics due to an etch selectivity difference resulting from a variation in lattice direction in the first InP layer (13). That is, the first InP layer (13) is not isotropically etched, but anisotropically etched in accordance with the variation in lattice direction, so that it has an inclined etch cross section.
- Where the etching of the first InP layer (13) is carried out under the condition in which the first InGaAs layer (12) is used as a mask, as shown in FIG. 4, it is begun from the region where the first InGaAs layer (12) is opened, and then anisotropically progressed along the depth of the first InP layer (13) so that the etch cross section of the first InP layer (13) has an inclination θ. The etching of the first InP layer (13) is stopped by the second InGaAs layer (14), so that the second InGaAs layer (14) and the second InP layer (15) are hardly etched.
- The inclination θ is determined by the kind, concentration, and temperature of the etchant used.
- The bottom width of the etch cross section, L2, is determined by the line width L1, the thickness of the first InP layer (13), H1, and the inclination θ. That is, the bottom width L2 corresponds to “L1−2×H1/tan θ” (L2=L1−2×H1/tan θ). Accordingly, L2 of a submicron unit can be appropriately defined by adjusting L1, H1, and θ.
- Subsequently, a contact metal (51) is deposited over the entire upper surface of the structure obtained at the step of FIG. 4, using an electron-beam evaporator or a thermal evaporator, as shown in FIG. 5. At this time, the contact metal (51) has a V-shaped structure at a portion thereof deposited at the region where the first InP layer (13) is etched. The V-shaped structure of the contact metal (51) has an inclination corresponding to the inclination formed by the anisotropic etching of the first InP layer (13).
- Thereafter, the portion of the contact metal (51) arranged on the photoresist (21) is lifted off along with the photoresist (21), as shown in FIG. 6.
- Following the lift-off process, the first InGaAs layer (12) and first InP layer (13) are selectively etched, thereby forming a gate (61) made of the remaining contact metal (51), as shown in FIG. 7. Using the gate (61) as a mask, the second InGaAs layer (14) and second InP layer (15) arranged beneath the gate (61) are then sequentially etched in accordance with an anisotropic wet etch process. For the etching of the first and second InGaAs layer (12 and 14), H3PO4:H2O2:H2O is used as an etchant whereas HCl:H3PO4 is used as an etchant for the first and second InP layers (13 and 15). After the completion of the etching steps, an inclined structure made of the second InP layer (15) is obtained which has an inclination resulting from a variation in etch selectivity exhibited in the second InP layer (15). The bottom width of the inclined structure, L3, is also determined by the line width L1, the inclination θ, and the thickness of the second InP layer (15), H2. That is, the bottom width L3 corresponds to “L2+2×H2/tan θ” (L3=L2+2×H2/tan θ). Since H2 is less than H1, L3 is more than L2 even though it is less than L1. Of course, the inclination θ associated with L3 corresponds to the inclination θ associated with L2.
- Thus, the gate (61) has a self-aligned structure in that its region includes the region defined by L3.
- Finally, a contact metal (91) is deposited over the structure obtained after the process of FIG. 8, for a self-alignment of the gate, as shown in FIG. 9.
- As apparent from the above description, in accordance with the present invention, the fabrication of a submicron gate is carried out using the existing exposure process such as an anisotropic wet etch process without use of any separate equipment. Accordingly, it is possible to simplify the fabrication of the submicron gate, thereby achieving a reduction in the manufacturing costs.
- In the formation of a base electrode involved in the fabrication of an HBT device, the present invention also provides an effect of reducing the distance between a base and an emitter as much as possible, thereby achieving a reduction in base resistance, in that it enables a self-alignment using a V-shaped submicron gate.
- Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (11)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000016066A KR100332834B1 (en) | 2000-03-29 | 2000-03-29 | A fabrication method of sub-micron gate using anisotropic etching |
KR00-16066 | 2000-03-29 | ||
KR16066 | 2000-03-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010026985A1 true US20010026985A1 (en) | 2001-10-04 |
US6372594B2 US6372594B2 (en) | 2002-04-16 |
Family
ID=19659620
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/749,785 Expired - Fee Related US6372594B2 (en) | 2000-03-29 | 2000-12-28 | Fabrication method of submicron gate using anisotropic etching |
Country Status (3)
Country | Link |
---|---|
US (1) | US6372594B2 (en) |
JP (1) | JP3333997B2 (en) |
KR (1) | KR100332834B1 (en) |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080169512A1 (en) * | 2004-08-10 | 2008-07-17 | Doyle Brian S | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US20090061572A1 (en) * | 2003-06-27 | 2009-03-05 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7736956B2 (en) | 2005-08-17 | 2010-06-15 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7781771B2 (en) | 2004-03-31 | 2010-08-24 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7858481B2 (en) * | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7879675B2 (en) | 2005-03-14 | 2011-02-01 | Intel Corporation | Field effect transistor with metal source/drain regions |
US7898041B2 (en) | 2005-06-30 | 2011-03-01 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7902014B2 (en) | 2005-09-28 | 2011-03-08 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US7989280B2 (en) | 2005-11-30 | 2011-08-02 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8067818B2 (en) | 2004-10-25 | 2011-11-29 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8071983B2 (en) | 2005-06-21 | 2011-12-06 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US8084818B2 (en) | 2004-06-30 | 2011-12-27 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US8183646B2 (en) | 2005-02-23 | 2012-05-22 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8268709B2 (en) | 2004-09-29 | 2012-09-18 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8405164B2 (en) | 2003-06-27 | 2013-03-26 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
US8617945B2 (en) | 2006-08-02 | 2013-12-31 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8912099B2 (en) * | 2012-11-13 | 2014-12-16 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100456037B1 (en) * | 2001-10-24 | 2004-11-15 | 한국과학기술원 | Method for fabricating Heterojunction Bipolar Transistor using lateral-reverse selective etching of collector |
US20040018738A1 (en) * | 2002-07-22 | 2004-01-29 | Wei Liu | Method for fabricating a notch gate structure of a field effect transistor |
KR100447980B1 (en) * | 2002-12-10 | 2004-09-10 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
KR102220032B1 (en) * | 2018-08-20 | 2021-02-25 | 한국과학기술원 | Two-terminal biristor with poly-crystalline silicon emitter electrode and method for manufacturing thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2228617A (en) * | 1989-02-27 | 1990-08-29 | Philips Electronic Associated | A method of manufacturing a semiconductor device having a mesa structure |
JP2618539B2 (en) * | 1991-03-04 | 1997-06-11 | シャープ株式会社 | Method for manufacturing semiconductor device |
EP0562272A3 (en) * | 1992-03-23 | 1994-05-25 | Texas Instruments Inc | Microwave heterojunction bipolar transistors with emitters designed for high power applications and method for fabricating same |
JP2000021895A (en) * | 1998-07-02 | 2000-01-21 | Sharp Corp | Semiconductor device and its manufacture |
-
2000
- 2000-03-29 KR KR1020000016066A patent/KR100332834B1/en not_active IP Right Cessation
- 2000-12-08 JP JP2000374444A patent/JP3333997B2/en not_active Expired - Fee Related
- 2000-12-28 US US09/749,785 patent/US6372594B2/en not_active Expired - Fee Related
Cited By (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090061572A1 (en) * | 2003-06-27 | 2009-03-05 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7820513B2 (en) | 2003-06-27 | 2010-10-26 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US8405164B2 (en) | 2003-06-27 | 2013-03-26 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
US20110020987A1 (en) * | 2003-06-27 | 2011-01-27 | Hareland Scott A | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US8273626B2 (en) | 2003-06-27 | 2012-09-25 | Intel Corporationn | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7781771B2 (en) | 2004-03-31 | 2010-08-24 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US8084818B2 (en) | 2004-06-30 | 2011-12-27 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7960794B2 (en) | 2004-08-10 | 2011-06-14 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US20080169512A1 (en) * | 2004-08-10 | 2008-07-17 | Doyle Brian S | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US8399922B2 (en) | 2004-09-29 | 2013-03-19 | Intel Corporation | Independently accessed double-gate and tri-gate transistors |
US8268709B2 (en) | 2004-09-29 | 2012-09-18 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US8502351B2 (en) | 2004-10-25 | 2013-08-06 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8749026B2 (en) | 2004-10-25 | 2014-06-10 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8067818B2 (en) | 2004-10-25 | 2011-11-29 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US10236356B2 (en) | 2004-10-25 | 2019-03-19 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US9741809B2 (en) | 2004-10-25 | 2017-08-22 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US9190518B2 (en) | 2004-10-25 | 2015-11-17 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8816394B2 (en) | 2005-02-23 | 2014-08-26 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9748391B2 (en) | 2005-02-23 | 2017-08-29 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US10121897B2 (en) | 2005-02-23 | 2018-11-06 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9614083B2 (en) | 2005-02-23 | 2017-04-04 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8368135B2 (en) | 2005-02-23 | 2013-02-05 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9368583B2 (en) | 2005-02-23 | 2016-06-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8183646B2 (en) | 2005-02-23 | 2012-05-22 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9048314B2 (en) | 2005-02-23 | 2015-06-02 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8664694B2 (en) | 2005-02-23 | 2014-03-04 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US7879675B2 (en) | 2005-03-14 | 2011-02-01 | Intel Corporation | Field effect transistor with metal source/drain regions |
US7858481B2 (en) * | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US10937907B2 (en) | 2005-06-15 | 2021-03-02 | Intel Corporation | Method for fabricating transistor with thinned channel |
US10367093B2 (en) | 2005-06-15 | 2019-07-30 | Intel Corporation | Method for fabricating transistor with thinned channel |
US9806195B2 (en) | 2005-06-15 | 2017-10-31 | Intel Corporation | Method for fabricating transistor with thinned channel |
US20110062520A1 (en) * | 2005-06-15 | 2011-03-17 | Brask Justin K | Method for fabricating transistor with thinned channel |
US9337307B2 (en) * | 2005-06-15 | 2016-05-10 | Intel Corporation | Method for fabricating transistor with thinned channel |
US8933458B2 (en) | 2005-06-21 | 2015-01-13 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US9385180B2 (en) | 2005-06-21 | 2016-07-05 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US8581258B2 (en) | 2005-06-21 | 2013-11-12 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US8071983B2 (en) | 2005-06-21 | 2011-12-06 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US9761724B2 (en) | 2005-06-21 | 2017-09-12 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US7898041B2 (en) | 2005-06-30 | 2011-03-01 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7736956B2 (en) | 2005-08-17 | 2010-06-15 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7902014B2 (en) | 2005-09-28 | 2011-03-08 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US8294180B2 (en) | 2005-09-28 | 2012-10-23 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US7989280B2 (en) | 2005-11-30 | 2011-08-02 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8617945B2 (en) | 2006-08-02 | 2013-12-31 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US9450092B2 (en) | 2008-06-23 | 2016-09-20 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9806193B2 (en) | 2008-06-23 | 2017-10-31 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8741733B2 (en) | 2008-06-23 | 2014-06-03 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9224754B2 (en) | 2008-06-23 | 2015-12-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8912099B2 (en) * | 2012-11-13 | 2014-12-16 | Mitsubishi Electric Corporation | Method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP3333997B2 (en) | 2002-10-15 |
KR100332834B1 (en) | 2002-04-15 |
JP2001284365A (en) | 2001-10-12 |
KR20010093444A (en) | 2001-10-29 |
US6372594B2 (en) | 2002-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6372594B2 (en) | Fabrication method of submicron gate using anisotropic etching | |
US7419862B2 (en) | Method of fabricating pseudomorphic high electron mobility transistor | |
JPH04223342A (en) | Gate electrode of semiconductor device and manufacture thereof | |
JPH03292744A (en) | Compound semiconductor device and manufacture thereof | |
KR100456037B1 (en) | Method for fabricating Heterojunction Bipolar Transistor using lateral-reverse selective etching of collector | |
KR100681842B1 (en) | T-type gate electrode and method for fabricating the same | |
US6051506A (en) | Method of fabrication ultra-frequency semiconductor device | |
KR100457926B1 (en) | Fabrication method of submicron emitter using anisotropic etching characteristics | |
JP2555979B2 (en) | Method for manufacturing semiconductor device | |
KR100342443B1 (en) | The method for manufacturing submicron T-gate of field effect transistor | |
JP2790104B2 (en) | Method for manufacturing field effect transistor | |
JPWO2003067664A1 (en) | Field effect transistor and manufacturing method thereof | |
JPS63273363A (en) | Manufacture of semiconductor device | |
JP4606710B2 (en) | Field effect transistor | |
JPH05129345A (en) | Manufacturing method of microwave integrated circuit | |
KR100366422B1 (en) | Metal Transistor Manufacturing Method | |
KR100488475B1 (en) | Manufacturing method of ultra high frequency semiconductor device | |
JP3018662B2 (en) | Method for manufacturing field effect transistor | |
KR100864181B1 (en) | T-type gate electrode for HEMT and method for fabricating the same | |
JPH07183312A (en) | Forming method of gate electrode for field-effect transistor | |
JP3178395B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2910913B2 (en) | Field effect transistor and method of manufacturing the same | |
JP2002009275A (en) | Field effect compound semiconductor device | |
JPH04274332A (en) | Manufacture of semiconductor device | |
JP2000124226A (en) | Heterojunction bipolar transistor and method for formation thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JEON, SOO KUN;KIM, MOON JUNG;YANG, KYOUNG HOON;AND OTHERS;REEL/FRAME:011421/0476 Effective date: 20001220 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140416 |