US20010033013A1 - Repairable multi-chip package - Google Patents
Repairable multi-chip package Download PDFInfo
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- US20010033013A1 US20010033013A1 US09/822,480 US82248001A US2001033013A1 US 20010033013 A1 US20010033013 A1 US 20010033013A1 US 82248001 A US82248001 A US 82248001A US 2001033013 A1 US2001033013 A1 US 2001033013A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Definitions
- the present invention relates to a semiconductor device package. More particularly, the present invention relates to a repairable multi-chip package including a plurality of two-dimensionally mounted chips.
- a multi-chip package for memory cards such as smart media is generally assembled by mounting two or more memory chips within a single package.
- this kind of multi-chip package has the drawback in that it has a low test yield after the assembly process.
- a multi-chip package has a comparatively low test yield.
- the multi-chip package is considered a failure. Because of this, the multi-chip package has a higher failure rate than other packages. Preferably, when the assembled multi-chip package is measured as a failure, only the failed chips should be removed. However, after the assembly process, since the multi-chip package is sealed with the molding resin such as EMC (Epoxy Molding Compound). As a result, in order to remove the failed memory chips, the multi-chip package would have to be disassembled in a way that would destroy them.
- EMC Application Molding Compound
- the first method is to broaden the bus width of data, as it is used in the memory module.
- the second method is retain a given bus width of data, but to broaden the address. As shown in the example below, a multi-chip package 100 in FIG. 1 uses the second method.
- FIG. 1 shows a conventional multi-chip package 100 , in which two semiconductor chips 10 and 20 are mounted on an upper surface 34 of a substrate 30 .
- the multi-chip package 100 is generally employed on a memory card such as a smart media.
- the chips 10 and 20 are arranged to be coplanar on the upper surface 34 of the substrate 30 and are referred to as “a first chip” 10 and “a second chip” 20 , respectively.
- the first and second chips 10 and 20 are mounted on the substrate 30 and are molded by a liquid molding resin, thereby forming a molding part 50 .
- the first and second chips 10 and 20 are electrically connected to the substrate 30 by bonding wires 60 .
- the first and second chips 10 and 20 are memory chips with the same capacitance.
- a plurality of electrode terminals are formed on both edges of the active surface of each chip 10 and 20 .
- the electrode terminals of the first chip 10 comprise a first power terminal 12 , a first ground terminal 13 , a second power terminal 14 , a most significant bit (MSB) terminal 15 , a second ground terminal 16 , and a dual terminal 17 .
- the first power terminal 12 and the first ground terminal 13 are arranged on one edge of the active surface of the first chip 10
- the second power terminal 14 , the MSB terminal 15 , the second ground terminal 16 , and the dual terminal 17 are arranged on the opposite edge.
- the electrode terminals of the second chip 20 comprise a first power terminal 22 , a first ground terminal 23 , a second power terminal 24 , an MSB terminal 25 , a second ground terminal 26 , and a dual terminal 27 .
- the first power terminal 22 and the first ground terminal 23 are arranged on one edge of the active surface of the second chip 20
- the second power terminal 24 , the MSB terminal 25 , the second ground terminal 26 , and the dual terminal 27 are arranged on the opposite edge.
- the first chip 10 and the second chip 20 are designed so that both the first chip 10 and the second chip 20 are dually operated. However, only one chip from among the first and second chips 10 and 20 can be operated at a time.
- the substrate 30 comprises a substrate body 32 having an upper surface 34 and a lower surface (not shown), and a plurality of wiring patterns 40 .
- the first chip 10 and the second chip 20 are mounted on the upper surface 34 .
- the wiring patterns 40 are formed on the upper surface 34 , and are electrically interconnected to the first chip 10 and the second chip 20 .
- a plurality of external connection terminals (not shown), which are electrically interconnected to the wiring patterns 40 of the upper surface 34 , are formed on the lower surface of the substrate 30 .
- the wiring patterns 40 are dually patterned and simultaneously operate the first chip 10 and the second chip 20 .
- Ground patterns 42 are electrically connected to the first ground terminal 13 of the first chip 10 and to the first ground terminal 23 of the second chip 20 , respectively.
- Power patterns 41 electrically connect the first power terminal 12 of the first chip 10 and the first power terminal 22 of the second chip 20 to each other.
- a part of the power patterns 41 is formed on the upper surface 34 within the perimeter of the chips 10 and 20 .
- the portion of the power patterns 41 that is formed in this manner is the portion connected from the first power terminal 12 of the first chip 10 to the first power terminal 22 of the second chip 20 .
- Dual patterns 49 serve to transmit a signal for dual operation of the first and second chips 10 and 20 .
- the dual patterns 48 comprise first dual patterns 47 for connecting the dual terminal 17 and the second ground terminal 16 of the first chip 10 to each other, and second dual patterns 48 for connecting the dual terminal 27 and the second ground terminal 26 of the second chip 20 to each other. In this design, one end of the second dual patterns 48 is connected to the first dual patterns 47 .
- MSB patterns 45 are connected to the MSB terminal 15 for selecting the first chip 10 or the second chip 20 .
- the MSB patterns 45 comprise first MSB patterns 43 for being connected to the second power terminal 14 of the first chip 10 and a second MSB patterns 44 for being connected to the MSB terminal 15 of the first chip and to the second power terminal 24 of the second chip 20 .
- one end of the second MSB patterns 44 is connected to the first MSB patterns 43 within the perimeter of the molding part 50 , and the other end of the second MSB patterns 44 is exposed to the outside before the second power terminal 24 of the second chip 20 .
- Parts of the second MSB patterns 44 between these two ends are formed on the upper surface 34 within the perimeter of the chips 10 and 20 .
- the first chip 10 and the second chip 20 are sealed by the molding part 50 .
- most of the wiring patterns 40 are included within the molding part 50 .
- the various semiconductor multi-chip packages that are determined to be failures are disposed of.
- the failures of the packages are classified into two types. One case is a package on which the two chips are both defective (referred to as “fully-failed package”); the other case is a package on which only a single chip is defective (referred to as “partially-failed package”). However, if a package is proved to be a failure, it is disposed of whether it is a fully-failed package or a partially-failed package.
- an object of the present invention is to repair partially-failed multi-chip packages that have a mix of functional and non-functional chips and to use the repaired multi-chip packages as good packages having good chips.
- the present invention provides a repairable multi-chip package.
- the repairable multi-chip package comprises a substrate; a first chip formed over the substrate, having a plurality of first terminals; a second chip formed over the substrate, having a plurality of second terminals; a molding part comprising molding resin formed over the first chip and the second chip; and a plurality of wiring patterns formed in the substrate and having portions extending beyond the molding part, the wiring patterns being electrically connected to the first and second chips through the first and second terminals, respectively, wherein the plurality of wiring patterns are arranged such that if one of the first and second chips is non-functional and the other of the first and second chips is functional, the portions of the wiring patterns extending beyond the molding part can be selectively cut to allow the functional chip to operate.
- the plurality of first and second terminals each preferably comprise a first power terminal, a first ground terminal, a second power terminal, a most significant bit (MSB) terminal, a second ground terminal, and a dual terminal.
- the first power terminal and the first ground terminal of the first chip are preferably formed on a first edge of a first active surface of the first chip;
- the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are preferably formed on a second edge of the first active surface;
- the first power terminal and the first ground terminal of the second are preferably formed on a first edge of a second active surface of the second chip;
- the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are preferably formed on a second edge of the second active surface.
- the wiring patterns may further comprise a plurality of ground patterns for connecting the first and second chips to a ground voltage; a plurality of power patterns for connecting the first and second chip to a supply voltage; a plurality of dual patterns for transmitting a signal for the dual operation of the first and second chips to the first and second chips; and a plurality of most significant bit (MSB) patterns for selecting one of the first and second chips.
- a plurality of ground patterns for connecting the first and second chips to a ground voltage
- a plurality of power patterns for connecting the first and second chip to a supply voltage
- a plurality of dual patterns for transmitting a signal for the dual operation of the first and second chips to the first and second chips
- MSB most significant bit
- the plurality of ground patterns may comprise a first ground pattern connected to the first ground terminal of the first chip; and a second ground pattern connected to the second ground terminal of the second chip.
- the plurality of power patterns may comprise a first power pattern connected to the first power terminal of the first chip and extending beyond the molding part; and a second power pattern connected to the first power terminal of the second chip, and to the first power pattern beyond the molding part.
- the second power pattern is preferably formed inside of the plurality of ground patterns to prevent interference between the second power pattern and the first ground pattern.
- the plurality of dual patterns may comprise a first dual pattern connected to the dual terminal and the second ground terminal of the first chip and extending beyond the molding part; a second dual pattern connected to the dual terminal and the second ground terminal of the second chip and extending beyond the molding part; and a third dual pattern connecting the first and second dual patterns together.
- the plurality of dual patterns may further comprise a fourth dual pattern connected to the second ground terminal of the first chip; and a fifth dual pattern connected to the second ground terminal of the second chip. In this case, the third dual pattern connects the first, second, fourth, and fifth dual patterns together.
- the plurality of MSB patterns may comprise a plurality of first MSB patterns connected to the MSB terminal and the second ground terminal of the first chip and extending beyond the molding part; a second MSB pattern formed beyond the molding part and connected to the first MSB patterns; and a third MSB pattern connected to the second power terminal of the second chip, and to the second MSB pattern between two of the first MSB patterns.
- a portion of the third MSB pattern is preferably formed within the perimeter of the first and second chips.
- the wiring patterns are preferably formed such that if the first chip is a functioning chip and the second chip is a non-functioning chip, the second chip can be isolated by cutting the second power pattern, the third MSB pattern, the first dual pattern, and the second dual pattern, all beyond the molding part.
- the wiring patterns are also preferably formed such that if the first chip is a nonfunctioning chip and the second chip is a functioning chip, the first chip can be isolated by cutting the first power pattern, the first MSB patterns, the first dual pattern, and the second dual pattern, all beyond the molding part.
- FIG. 1 is a plan view showing a conventional multi-chip package including two semiconductor chips
- FIG. 2 is a plan view showing a substrate for a multi-chip package in accordance with a preferred embodiment of the present invention
- FIG. 3 is a plan view showing a multi-chip package including two semiconductor chips mounted on the substrate of FIG. 2;
- FIG. 4 is a plan view showing a multi-chip package, wherein only a first chip is operated by repairing the multi-chip package of FIG. 3;
- FIG. 5 is a plan view showing a multi-chip package, wherein only a second chip is operated by repairing the multi-chip package of FIG. 3.
- FIG. 2 shows a substrate 130 for a multi-chip package in accordance with a preferred embodiment of the present invention.
- FIG. 3 is a plan view of a multi-chip package 200 comprising two semiconductor chips 110 and 120 mounted on the substrate 130 of FIG. 2.
- the multi-chip package 200 is preferably employed on a memory card such as a smart media.
- the first chip 110 and the second chip 120 are mounted on an upper surface 134 of the substrate 130 and are sealed with a liquid molding resin, thereby forming a molding part 150 .
- the first chip 110 and the second chip 120 are preferably electrically interconnected to the substrate 130 by bonding wires 160 .
- a plurality of external connection terminals (not shown) are formed on a lower surface of the substrate 130 .
- the multi-chip package 200 comprises wiring patterns 140 , which allow a partially-failed package having one failed chip to operate as a multi-chip package having the capacity of only a single good chip.
- the wiring patterns 140 of the multi-chip package 200 are designed so that the multi-chip package 200 with one failed chip may still be operated by blocking the failed chip and only using the remaining good chip.
- This embodiment can repair the wiring patterns 140 to successfully operate the remaining good chip since the wiring patterns 140 are formed outside of the perimeter of the molding part 150 . Their detailed descriptions will be provided below.
- the first chip 110 and the second chip 120 are preferably memory chips with the same capacitance.
- a plurality of electrode terminals are formed both edges of the active surface of each chip 110 and 120 .
- the electrode terminals of the first chip 110 comprise a first power terminal 112 , a first ground terminal 113 , a second power terminal 114 , a most significant bit (MSB) terminal 115 , a second ground terminal 116 , and a dual terminal 117 .
- the first power terminal 112 and the first ground terminal 113 are preferably arranged on one edge of the active surface of the first chip 110
- the second power terminal 114 , the MSB terminal 115 , and the dual terminal 117 are preferably arranged on the opposite edge.
- the electrode terminals of the second chip 120 comprise a first power terminal 122 , a first ground terminal 123 , a second power terminal 124 , an MSB terminal 125 , a second ground terminal 126 , and a dual terminal 127 .
- the first power terminal 122 and the first ground terminal 123 are arranged on one edge of the active surface of the second chip 120
- the second power terminal 124 , the MSB terminal 125 , and the dual terminal 127 are arranged on the opposite edge.
- the electrode terminals of the first and second chips 110 and 120 further comprise data terminals and address terminals.
- the first chip 110 and the second chip 120 are preferably designed so that the two chips 110 and 120 are dually operated. However, in this embodiment, only one chip of two chips 110 and 120 can be independently operated.
- the substrate 130 comprises a substrate body 132 having an upper surface 134 and a lower surface,(not shown), and the wiring patterns.
- the first chip 110 and the second chip 120 are mounted on the upper surface 134 .
- the wiring patterns 140 are formed on the upper surface 134 , and are electrically interconnected to the first chip 110 and the second chip 120 .
- a plurality of external connection terminals (not shown) are formed on the lower surface, and are electrically interconnected to the wiring patterns 140 on the upper surface 134 through via holes (not shown).
- the wiring patterns 140 are patterned so that the first chip 110 and the second chip 120 are dually and simultaneously operated, and so that, even though the multi-chip package may be determined to be a partially-failed package comprising one failed chip, the multi-chip package will still be able to function.
- Data patterns (not shown) and address patterns (not shown) are formed on the upper surface 134 so that all the data terminals and all of the address terminals are commonly owned.
- Ground patterns 142 are electrically connected to the first ground terminal 113 of the first chip 110 and to the first ground terminal 123 of the second chip 120 .
- Power patterns 141 electrically connect the first power terminal 112 of the first chip 110 and the first power terminal 122 of the second chip 120 to each other.
- the power patterns 141 are mostly exposed from the molding part 150 , and thereby a repairing process is more easily accomplished on these patterns.
- the power patterns 141 preferably comprise a first power pattern 141 a and a second power pattern 141 b .
- one end of the first power pattern 141 a is connected to the first power terminal 112 of the first chip 110 and one end of the second power patterns 141 b is connected to the first power terminal 122 of the second chip 120 .
- the other end of the first power patterns 141 a and the other end of the second power patterns 141 b are connected to each other and extend from the molding part 150 .
- a part of the second power pattern 141 b that connects the first power terminal 112 of the first chip 110 to the first power terminal 122 of the second chip 120 is formed inside of the ground pattern 142 .
- the second power pattern 141 b starts close to the ground patterns 142 , is bent toward the first chip 110 , turns around the first ground terminal 113 of the first chip 110 , and forms an end before the first power terminal 122 of the second chip 120 .
- the end of the second power patterns 141 b is electrically connected to the first power terminal 122 of the second chip 120 by the bonding wire 160 .
- Dual patterns 149 serve to transmit a signal for dual operation of the first and second chips 110 and 120 and extend from the molding part 150 . As a result, the repairing process is more easily accomplished.
- the dual patterns 149 comprise first dual pattern 147 a , a second dual patterns 147 b , a third dual pattern 148 , a fourth dual pattern 147 c , and a fifth dual pattern 147 d .
- the first and fourth dual patterns 147 a and 147 c connect to the dual terminal 117 and the second ground terminal 116 of the first chip 110 to each other; and the second and third dual patterns 147 b and 147 d connect the dual terminal 127 and the second ground terminal 126 of the second chip 120 to each other.
- the first, second, fourth, and fifth dual patterns 147 a - 147 d extend beyond the molding part 150 and are connected to each other by the third dual pattern 148 .
- MSB patterns 146 which serve to select one of the first and second chips 110 and 120 , also extend away from the molding part 150 , thus allowing their rewiring process to be more easily accomplished.
- the MSB patterns 146 comprise first MSB patterns 143 , a second MSB pattern 145 , and a third MSB pattern 144 .
- One end of each of the first MSB patterns 143 are respectively connected to the MSB terminal 115 and to the second power terminal 114 of the first chip 110 by the bonding wires 160 .
- each of the first MSB patterns 143 extend beyond the molding part 150 .
- the second MSB pattern 145 is connected to the extended ends of the first MSB patterns 143 .
- One end of the third MSB pattern 144 is connected to the second MSB pattern 145 between two first MSB patterns 143 , and the other end of the third MSB pattern 144 is connected to the second power terminal 124 of the second chip 120 .
- a portion of the third MSB pattern is formed within the perimeter of the first and second chips 110 and 120 .
- the third MSB pattern 144 starts between two first MSB patterns 143 , extends below the first chip 110 , is bent toward the second chip 120 , turns around the MSB terminal 115 , the second ground terminal 116 , and the dual terminal 117 of the first chip 110 , and forms its exposed end on the front of the second power terminal 124 of the second chip 120 .
- the exposed end of the third MSB pattern 144 is then electrically connected to the second power terminal 124 a bonding wire 160 .
- the second MSB pattern 145 is formed on the inside of the second dual patterns 148 .
- the wiring patterns 140 are designed to be suitable for a multi-chip package 200 on which two chips, i.e. the first and second chip 110 and 120 , are dually operated. Furthermore, the wiring patterns 140 can be used, even if the multi-chip package 200 is determined to be a partially-failed package having a failed chip by repairing the parts of the wiring patterns 140 extending from the molding part 150 .
- FIG. 4 shows a multi-chip package 200 a , wherein only the first chip 110 is operated by repairing the multi-chip package 200 of FIG. 3
- FIG. 5 shows a multi-chip package 200 b , wherein only the second chip 120 is operated by repairing the multi-chip package 200 of FIG. 3.
- the power patterns, the dual patterns, and MSB patterns may be redistributed so that only one of two chips (i.e., a good chip) is operated.
- Each chip can be independently operated by cutting a connection parts of the wiring patterns, which connect the dual terminals to the MSB terminals.
- only one chip selected from the first and second chips is operated by selectively cutting either one of two power patterns for providing power to the first chip or to the second chip. In this way, a redistribution process for providing power to only the functional chip is carried out.
- the wiring patterns 140 are redistributed so that the multi-chip package 200 a is worked by operating only the first chip 110 .
- a part of the second power pattern 141 b is cut by a cutting means such as laser or blade, so that power is provided to the first power terminal 112 of the first chip 110 but is blocked from going to the first power terminal 122 of the second chip 120 .
- a reference numeral “A 1 ” represents the cutting part of the second power pattern 141 b , which cutting part A 1 is exposed from the molding part 150 .
- the third MSB pattern 144 for connecting the second MSB pattern 145 to the second power terminal 124 of the second chip 120 is also cut.
- a reference numeral “B 1 ” represents the cutting part of the third MSB pattern 144 .
- the cutting part B 1 of the third MSB pattern 144 is close to the second MSB pattern 145 and is also exposed from the molding part 150 . By cutting the third MSB pattern 144 , the power supply is blocked to the second power terminal 124 of the second chip 120 .
- the first dual pattern 147 a connected to the dual terminal 117 of the first chip 110 and the second dual patterns 147 b connected to the dual terminal 127 of the second chip 120 are also cut.
- a reference numeral “C 1 ” represents the cutting part of the first and second dual patterns 147 a and 147 b .
- the cutting parts C 1 of the first and second dual patterns 147 a and 147 b are close to the third dual patterns 148 and exposed from the molding part 150 .
- the wiring patterns 140 are redistributed so that the multi-chip package 200 a is operated using only the second chip 120 .
- a part of the first power pattern 141 a is cut so that power is provided to the first power terminal 122 of the second chip 120 but is blocked from going to the first power terminal 112 of the first chip.
- a reference numeral “A 2 ” represents the cutting part of the first power pattern 141 a , which cutting part A 2 is exposed from the molding part 150 .
- Two first MSB patterns 143 each connected to the second power terminal 114 and to the MSB terminal 115 , respectively of the first chip 110 are cut.
- a reference numeral “B 2 ” represents the cutting parts of the first MSB patterns 143 , which cutting parts B 2 are exposed from the molding part 150 .
- the first dual pattern 147 a connected to the dual terminal 117 of the first multi-chip and the second dual pattern 147 b connected to the dual terminal 127 of the second chip 120 are cut also.
- a reference numeral “C 2 ” represents the cutting part of the first and second dual patterns 147 a and 147 b .
- the wiring patterns are formed on the upper surface of the substrate body so that two chips are dually operated. Since parts of the wiring patterns to be redistributed extend from beneath the molding part, a partially-failed package is easily repaired by the redistribution process and may therefore be reused.
- the preferred embodiments of the present invention employ a multi-chip package for a memory card
- a multi-chip package using other connection methods such as solder balls as external connection terminals may also be employed.
- wiring patterns for redistributing the power patterns, the dual patterns, and the MSB patterns are formed on the lower surface around the edges. In this way, the redistribution process for selecting one chip (i.e., a good chip) from the first and second chips of the partially-failed package can be achieved.
Abstract
A repairable multi-chip package is provided. The repairable multi-chip package comprises a first chip, a second chip, a substrate, and a molding part formed by molding the first chip and the second chip with a molding resin. The substrate comprises a substrate body and wiring patterns, the substrate body has an upper surface on which the first chip and the second chip are mounted and a lower surface. The wiring patterns are formed on the upper surface of the substrate and are electrically interconnected to the first and second chips. The wiring pattern comprises ground patterns, power patterns, dual patterns, and most significant bit (MSB) patterns. By redistributing exposed parts of the power patterns, the dual patterns, and the MSB patterns, a multi-chip package that is determined to be a partially-failed package may be repaired making the device useable.
Description
- This application relies for priority upon Korean Patent Application No. 2000-20982, filed on Apr. 20, 2000, the contents of which are herein incorporated by reference in their entirety.
- The present invention relates to a semiconductor device package. More particularly, the present invention relates to a repairable multi-chip package including a plurality of two-dimensionally mounted chips.
- Recently, increases in memory density, i.e., memory storage capacity, have been continually required to keep up with rapid developments in modern digital technology. However, the current rate of increase for memory density does not presently satisfy this pressing demand. In order to improve the memory density, a multi-chip package design including a plurality of bare semiconductor integrated chips has been widely employed in application for DRAMs, SRAMs, Flash memories, and the like.
- A multi-chip package for memory cards such as smart media is generally assembled by mounting two or more memory chips within a single package. However, this kind of multi-chip package has the drawback in that it has a low test yield after the assembly process. In other words, compared to a semiconductor package that has only a single memory chip, a multi-chip package has a comparatively low test yield.
- One of the reasons for this is that in a multi-chip package, even if there is only one failed chip, or several failed chips among a plurality of chips, the multi-chip package is considered a failure. Because of this, the multi-chip package has a higher failure rate than other packages. Preferably, when the assembled multi-chip package is measured as a failure, only the failed chips should be removed. However, after the assembly process, since the multi-chip package is sealed with the molding resin such as EMC (Epoxy Molding Compound). As a result, in order to remove the failed memory chips, the multi-chip package would have to be disassembled in a way that would destroy them.
- In the multi-chip package having at least two chips, there are two methods of increasing the memory capacity. The first method is to broaden the bus width of data, as it is used in the memory module. The second method is retain a given bus width of data, but to broaden the address. As shown in the example below, a
multi-chip package 100 in FIG. 1 uses the second method. - FIG. 1 shows a conventional
multi-chip package 100, in which twosemiconductor chips upper surface 34 of asubstrate 30. As shown in FIG. 1, themulti-chip package 100 is generally employed on a memory card such as a smart media. Thechips upper surface 34 of thesubstrate 30 and are referred to as “a first chip” 10 and “a second chip” 20, respectively. The first andsecond chips substrate 30 and are molded by a liquid molding resin, thereby forming amolding part 50. The first andsecond chips substrate 30 bybonding wires 60. - In this design the first and
second chips chip first chip 10 comprise afirst power terminal 12, afirst ground terminal 13, asecond power terminal 14, a most significant bit (MSB)terminal 15, asecond ground terminal 16, and adual terminal 17. Thefirst power terminal 12 and thefirst ground terminal 13 are arranged on one edge of the active surface of thefirst chip 10, and thesecond power terminal 14, theMSB terminal 15, thesecond ground terminal 16, and thedual terminal 17 are arranged on the opposite edge. - Similarly, the electrode terminals of the
second chip 20 comprise afirst power terminal 22, afirst ground terminal 23, asecond power terminal 24, anMSB terminal 25, asecond ground terminal 26, and adual terminal 27. Thefirst power terminal 22 and thefirst ground terminal 23 are arranged on one edge of the active surface of thesecond chip 20, and thesecond power terminal 24, the MSBterminal 25, thesecond ground terminal 26, and thedual terminal 27 are arranged on the opposite edge. - The
first chip 10 and thesecond chip 20 are designed so that both thefirst chip 10 and thesecond chip 20 are dually operated. However, only one chip from among the first andsecond chips - The
substrate 30 comprises asubstrate body 32 having anupper surface 34 and a lower surface (not shown), and a plurality ofwiring patterns 40. Thefirst chip 10 and thesecond chip 20 are mounted on theupper surface 34. Thewiring patterns 40 are formed on theupper surface 34, and are electrically interconnected to thefirst chip 10 and thesecond chip 20. A plurality of external connection terminals (not shown), which are electrically interconnected to thewiring patterns 40 of theupper surface 34, are formed on the lower surface of thesubstrate 30. - The
wiring patterns 40 are dually patterned and simultaneously operate thefirst chip 10 and thesecond chip 20.Ground patterns 42 are electrically connected to thefirst ground terminal 13 of thefirst chip 10 and to thefirst ground terminal 23 of thesecond chip 20, respectively.Power patterns 41 electrically connect thefirst power terminal 12 of thefirst chip 10 and thefirst power terminal 22 of thesecond chip 20 to each other. In order to prevent interference between theground patterns 42 and thepower patterns 41, a part of thepower patterns 41 is formed on theupper surface 34 within the perimeter of thechips power patterns 41 that is formed in this manner is the portion connected from thefirst power terminal 12 of thefirst chip 10 to thefirst power terminal 22 of thesecond chip 20. -
Dual patterns 49 serve to transmit a signal for dual operation of the first andsecond chips dual patterns 48 comprise firstdual patterns 47 for connecting thedual terminal 17 and thesecond ground terminal 16 of thefirst chip 10 to each other, and seconddual patterns 48 for connecting thedual terminal 27 and thesecond ground terminal 26 of thesecond chip 20 to each other. In this design, one end of the seconddual patterns 48 is connected to the firstdual patterns 47. - Most significant bit (MSB)
patterns 45 are connected to theMSB terminal 15 for selecting thefirst chip 10 or thesecond chip 20. TheMSB patterns 45 comprisefirst MSB patterns 43 for being connected to thesecond power terminal 14 of thefirst chip 10 and asecond MSB patterns 44 for being connected to theMSB terminal 15 of the first chip and to thesecond power terminal 24 of thesecond chip 20. In this design, one end of thesecond MSB patterns 44 is connected to thefirst MSB patterns 43 within the perimeter of themolding part 50, and the other end of thesecond MSB patterns 44 is exposed to the outside before thesecond power terminal 24 of thesecond chip 20. Parts of thesecond MSB patterns 44 between these two ends are formed on theupper surface 34 within the perimeter of thechips - After mounting the first and
second chips upper surface 34 of thesubstrate body 30 and electrically connecting eachchip substrate 30 by thebonding wires 60, thefirst chip 10 and thesecond chip 20 are sealed by themolding part 50. As a result, most of thewiring patterns 40 are included within themolding part 50. - During various test processes after the assembly process, the various semiconductor multi-chip packages that are determined to be failures are disposed of. The failures of the packages are classified into two types. One case is a package on which the two chips are both defective (referred to as “fully-failed package”); the other case is a package on which only a single chip is defective (referred to as “partially-failed package”). However, if a package is proved to be a failure, it is disposed of whether it is a fully-failed package or a partially-failed package.
- In the case of partially-failed packages, since most of the wiring patterns are sealed by the molding part, it is difficult to select only a good chip by repairing the wiring patterns. As a result, packages with functional chips are discarded, reducing the yield of the manufacturing process.
- Accordingly, an object of the present invention is to repair partially-failed multi-chip packages that have a mix of functional and non-functional chips and to use the repaired multi-chip packages as good packages having good chips.
- In order to achieve the foregoing and other objects, the present invention provides a repairable multi-chip package. The repairable multi-chip package comprises a substrate; a first chip formed over the substrate, having a plurality of first terminals; a second chip formed over the substrate, having a plurality of second terminals; a molding part comprising molding resin formed over the first chip and the second chip; and a plurality of wiring patterns formed in the substrate and having portions extending beyond the molding part, the wiring patterns being electrically connected to the first and second chips through the first and second terminals, respectively, wherein the plurality of wiring patterns are arranged such that if one of the first and second chips is non-functional and the other of the first and second chips is functional, the portions of the wiring patterns extending beyond the molding part can be selectively cut to allow the functional chip to operate.
- The plurality of first and second terminals each preferably comprise a first power terminal, a first ground terminal, a second power terminal, a most significant bit (MSB) terminal, a second ground terminal, and a dual terminal. The first power terminal and the first ground terminal of the first chip are preferably formed on a first edge of a first active surface of the first chip; the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are preferably formed on a second edge of the first active surface; the first power terminal and the first ground terminal of the second are preferably formed on a first edge of a second active surface of the second chip; and the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are preferably formed on a second edge of the second active surface.
- The wiring patterns may further comprise a plurality of ground patterns for connecting the first and second chips to a ground voltage; a plurality of power patterns for connecting the first and second chip to a supply voltage; a plurality of dual patterns for transmitting a signal for the dual operation of the first and second chips to the first and second chips; and a plurality of most significant bit (MSB) patterns for selecting one of the first and second chips.
- The plurality of ground patterns may comprise a first ground pattern connected to the first ground terminal of the first chip; and a second ground pattern connected to the second ground terminal of the second chip.
- The plurality of power patterns may comprise a first power pattern connected to the first power terminal of the first chip and extending beyond the molding part; and a second power pattern connected to the first power terminal of the second chip, and to the first power pattern beyond the molding part.
- The second power pattern is preferably formed inside of the plurality of ground patterns to prevent interference between the second power pattern and the first ground pattern.
- The plurality of dual patterns may comprise a first dual pattern connected to the dual terminal and the second ground terminal of the first chip and extending beyond the molding part; a second dual pattern connected to the dual terminal and the second ground terminal of the second chip and extending beyond the molding part; and a third dual pattern connecting the first and second dual patterns together. The plurality of dual patterns may further comprise a fourth dual pattern connected to the second ground terminal of the first chip; and a fifth dual pattern connected to the second ground terminal of the second chip. In this case, the third dual pattern connects the first, second, fourth, and fifth dual patterns together.
- The plurality of MSB patterns may comprise a plurality of first MSB patterns connected to the MSB terminal and the second ground terminal of the first chip and extending beyond the molding part; a second MSB pattern formed beyond the molding part and connected to the first MSB patterns; and a third MSB pattern connected to the second power terminal of the second chip, and to the second MSB pattern between two of the first MSB patterns. A portion of the third MSB pattern is preferably formed within the perimeter of the first and second chips.
- The wiring patterns are preferably formed such that if the first chip is a functioning chip and the second chip is a non-functioning chip, the second chip can be isolated by cutting the second power pattern, the third MSB pattern, the first dual pattern, and the second dual pattern, all beyond the molding part.
- The wiring patterns are also preferably formed such that if the first chip is a nonfunctioning chip and the second chip is a functioning chip, the first chip can be isolated by cutting the first power pattern, the first MSB patterns, the first dual pattern, and the second dual pattern, all beyond the molding part.
- The various features and advantages of the present invention will be readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and, in which:
- FIG. 1 is a plan view showing a conventional multi-chip package including two semiconductor chips;
- FIG. 2 is a plan view showing a substrate for a multi-chip package in accordance with a preferred embodiment of the present invention;
- FIG. 3 is a plan view showing a multi-chip package including two semiconductor chips mounted on the substrate of FIG. 2;
- FIG. 4 is a plan view showing a multi-chip package, wherein only a first chip is operated by repairing the multi-chip package of FIG. 3; and
- FIG. 5 is a plan view showing a multi-chip package, wherein only a second chip is operated by repairing the multi-chip package of FIG. 3.
- A preferred embodiment of the present invention will be described below with reference to the accompanying drawings.
- FIG. 2 shows a
substrate 130 for a multi-chip package in accordance with a preferred embodiment of the present invention. FIG. 3 is a plan view of amulti-chip package 200 comprising twosemiconductor chips substrate 130 of FIG. 2. With reference to FIG. 2 and FIG. 3, themulti-chip package 200 is preferably employed on a memory card such as a smart media. In this embodiment, thefirst chip 110 and thesecond chip 120 are mounted on anupper surface 134 of thesubstrate 130 and are sealed with a liquid molding resin, thereby forming amolding part 150. Thefirst chip 110 and thesecond chip 120 are preferably electrically interconnected to thesubstrate 130 by bondingwires 160. A plurality of external connection terminals (not shown) are formed on a lower surface of thesubstrate 130. - The
multi-chip package 200 compriseswiring patterns 140, which allow a partially-failed package having one failed chip to operate as a multi-chip package having the capacity of only a single good chip. In other words, thewiring patterns 140 of themulti-chip package 200 are designed so that themulti-chip package 200 with one failed chip may still be operated by blocking the failed chip and only using the remaining good chip. This embodiment can repair thewiring patterns 140 to successfully operate the remaining good chip since thewiring patterns 140 are formed outside of the perimeter of themolding part 150. Their detailed descriptions will be provided below. - The
first chip 110 and thesecond chip 120 are preferably memory chips with the same capacitance. A plurality of electrode terminals are formed both edges of the active surface of eachchip first chip 110 comprise afirst power terminal 112, afirst ground terminal 113, asecond power terminal 114, a most significant bit (MSB)terminal 115, asecond ground terminal 116, and adual terminal 117. Thefirst power terminal 112 and thefirst ground terminal 113 are preferably arranged on one edge of the active surface of thefirst chip 110, and thesecond power terminal 114, theMSB terminal 115, and thedual terminal 117 are preferably arranged on the opposite edge. - Similarly, the electrode terminals of the
second chip 120 comprise afirst power terminal 122, afirst ground terminal 123, asecond power terminal 124, anMSB terminal 125, asecond ground terminal 126, and adual terminal 127. Thefirst power terminal 122 and thefirst ground terminal 123 are arranged on one edge of the active surface of thesecond chip 120, and thesecond power terminal 124, theMSB terminal 125, and thedual terminal 127 are arranged on the opposite edge. The electrode terminals of the first andsecond chips - The
first chip 110 and thesecond chip 120 are preferably designed so that the twochips chips - The
substrate 130 comprises asubstrate body 132 having anupper surface 134 and a lower surface,(not shown), and the wiring patterns. Thefirst chip 110 and thesecond chip 120 are mounted on theupper surface 134. Thewiring patterns 140 are formed on theupper surface 134, and are electrically interconnected to thefirst chip 110 and thesecond chip 120. A plurality of external connection terminals (not shown) are formed on the lower surface, and are electrically interconnected to thewiring patterns 140 on theupper surface 134 through via holes (not shown). - The
wiring patterns 140 are patterned so that thefirst chip 110 and thesecond chip 120 are dually and simultaneously operated, and so that, even though the multi-chip package may be determined to be a partially-failed package comprising one failed chip, the multi-chip package will still be able to function. Data patterns (not shown) and address patterns (not shown) are formed on theupper surface 134 so that all the data terminals and all of the address terminals are commonly owned. -
Ground patterns 142 are electrically connected to thefirst ground terminal 113 of thefirst chip 110 and to thefirst ground terminal 123 of thesecond chip 120.Power patterns 141 electrically connect thefirst power terminal 112 of thefirst chip 110 and thefirst power terminal 122 of thesecond chip 120 to each other. Thepower patterns 141 are mostly exposed from themolding part 150, and thereby a repairing process is more easily accomplished on these patterns. Thepower patterns 141 preferably comprise afirst power pattern 141 a and asecond power pattern 141 b. In this embodiment, one end of thefirst power pattern 141 a is connected to thefirst power terminal 112 of thefirst chip 110 and one end of thesecond power patterns 141 b is connected to thefirst power terminal 122 of thesecond chip 120. The other end of thefirst power patterns 141 a and the other end of thesecond power patterns 141 b are connected to each other and extend from themolding part 150. - In order to prevent interference between the
second power patterns 141 b and theground patterns 142, a part of thesecond power pattern 141 b that connects thefirst power terminal 112 of thefirst chip 110 to thefirst power terminal 122 of thesecond chip 120 is formed inside of theground pattern 142. As shown in FIGS. 2 and 3, thesecond power pattern 141 b starts close to theground patterns 142, is bent toward thefirst chip 110, turns around thefirst ground terminal 113 of thefirst chip 110, and forms an end before thefirst power terminal 122 of thesecond chip 120. The end of thesecond power patterns 141 b is electrically connected to thefirst power terminal 122 of thesecond chip 120 by thebonding wire 160. -
Dual patterns 149 serve to transmit a signal for dual operation of the first andsecond chips molding part 150. As a result, the repairing process is more easily accomplished. Thedual patterns 149 comprise firstdual pattern 147 a, a seconddual patterns 147 b, a thirddual pattern 148, a fourthdual pattern 147 c, and a fifthdual pattern 147 d. The first and fourthdual patterns dual terminal 117 and thesecond ground terminal 116 of thefirst chip 110 to each other; and the second and thirddual patterns dual terminal 127 and thesecond ground terminal 126 of thesecond chip 120 to each other. The first, second, fourth, and fifth dual patterns 147 a-147 d extend beyond themolding part 150 and are connected to each other by the thirddual pattern 148. - Most significant bit (MSB)
patterns 146, which serve to select one of the first andsecond chips molding part 150, thus allowing their rewiring process to be more easily accomplished. TheMSB patterns 146 comprisefirst MSB patterns 143, asecond MSB pattern 145, and athird MSB pattern 144. One end of each of thefirst MSB patterns 143 are respectively connected to theMSB terminal 115 and to thesecond power terminal 114 of thefirst chip 110 by thebonding wires 160. - The other ends of each of the
first MSB patterns 143 extend beyond themolding part 150. Thesecond MSB pattern 145 is connected to the extended ends of thefirst MSB patterns 143. One end of thethird MSB pattern 144 is connected to thesecond MSB pattern 145 between twofirst MSB patterns 143, and the other end of thethird MSB pattern 144 is connected to thesecond power terminal 124 of thesecond chip 120. A portion of the third MSB pattern is formed within the perimeter of the first andsecond chips - In other words, the
third MSB pattern 144 starts between twofirst MSB patterns 143, extends below thefirst chip 110, is bent toward thesecond chip 120, turns around theMSB terminal 115, thesecond ground terminal 116, and thedual terminal 117 of thefirst chip 110, and forms its exposed end on the front of thesecond power terminal 124 of thesecond chip 120. The exposed end of thethird MSB pattern 144 is then electrically connected to the second power terminal 124 abonding wire 160. In order to prevent the interference between the seconddual patterns 148 and thesecond MSB pattern 145, thesecond MSB pattern 145 is formed on the inside of the seconddual patterns 148. - The
wiring patterns 140 are designed to be suitable for amulti-chip package 200 on which two chips, i.e. the first andsecond chip wiring patterns 140 can be used, even if themulti-chip package 200 is determined to be a partially-failed package having a failed chip by repairing the parts of thewiring patterns 140 extending from themolding part 150. For example, FIG. 4 shows amulti-chip package 200 a, wherein only thefirst chip 110 is operated by repairing themulti-chip package 200 of FIG. 3, and FIG. 5 shows amulti-chip package 200 b, wherein only thesecond chip 120 is operated by repairing themulti-chip package 200 of FIG. 3. - In the preferred embodiments of the present invention, the power patterns, the dual patterns, and MSB patterns may be redistributed so that only one of two chips (i.e., a good chip) is operated. Each chip can be independently operated by cutting a connection parts of the wiring patterns, which connect the dual terminals to the MSB terminals. In these examples, only one chip selected from the first and second chips is operated by selectively cutting either one of two power patterns for providing power to the first chip or to the second chip. In this way, a redistribution process for providing power to only the functional chip is carried out.
- As shown in FIG. 4, the
wiring patterns 140 are redistributed so that themulti-chip package 200 a is worked by operating only thefirst chip 110. A part of thesecond power pattern 141 b is cut by a cutting means such as laser or blade, so that power is provided to thefirst power terminal 112 of thefirst chip 110 but is blocked from going to thefirst power terminal 122 of thesecond chip 120. In FIG. 4, a reference numeral “A1” represents the cutting part of thesecond power pattern 141 b, which cutting part A1 is exposed from themolding part 150. - The
third MSB pattern 144 for connecting thesecond MSB pattern 145 to thesecond power terminal 124 of thesecond chip 120 is also cut. A reference numeral “B1” represents the cutting part of thethird MSB pattern 144. The cutting part B1 of thethird MSB pattern 144 is close to thesecond MSB pattern 145 and is also exposed from themolding part 150. By cutting thethird MSB pattern 144, the power supply is blocked to thesecond power terminal 124 of thesecond chip 120. - The first
dual pattern 147 a connected to thedual terminal 117 of thefirst chip 110 and the seconddual patterns 147 b connected to thedual terminal 127 of thesecond chip 120 are also cut. A reference numeral “C1” represents the cutting part of the first and seconddual patterns dual patterns dual patterns 148 and exposed from themolding part 150. By cutting the first and seconddual patterns multi-chip package 200 a is operated using only thefirst chip 110. - It is unimportant which among the step of cutting the
second power patterns 141 b, cutting thethird MSB patterns 144, and cutting the first and seconddual patterns - As shown in FIG. 5, the
wiring patterns 140 are redistributed so that themulti-chip package 200 a is operated using only thesecond chip 120. A part of thefirst power pattern 141 a is cut so that power is provided to thefirst power terminal 122 of thesecond chip 120 but is blocked from going to thefirst power terminal 112 of the first chip. In FIG. 5, a reference numeral “A2” represents the cutting part of thefirst power pattern 141 a, which cutting part A2 is exposed from themolding part 150. - Two
first MSB patterns 143, each connected to thesecond power terminal 114 and to theMSB terminal 115, respectively of thefirst chip 110 are cut. A reference numeral “B2” represents the cutting parts of thefirst MSB patterns 143, which cutting parts B2 are exposed from themolding part 150. By cutting thefirst MSB patterns 143, power supply through thesecond power terminal 114 of thefirst chip 110 is blocked. - As in the embodiment of FIG. 4, the first
dual pattern 147 a connected to thedual terminal 117 of the first multi-chip and the seconddual pattern 147 b connected to thedual terminal 127 of thesecond chip 120 are cut also. A reference numeral “C2” represents the cutting part of the first and seconddual patterns dual patterns multi-chip package 200 a is operates only thesecond chip 120. - It is unimportant which among the step of cutting the
first power patterns 141 a, cutting thefirst MSB patterns 143, and cutting the first and seconddual patterns - In accordance with preferred embodiments of the present invention, the wiring patterns are formed on the upper surface of the substrate body so that two chips are dually operated. Since parts of the wiring patterns to be redistributed extend from beneath the molding part, a partially-failed package is easily repaired by the redistribution process and may therefore be reused.
- Although the preferred embodiments of the present invention employ a multi-chip package for a memory card, a multi-chip package using other connection methods such as solder balls as external connection terminals may also be employed. In this multi-chip package having solder balls, wiring patterns for redistributing the power patterns, the dual patterns, and the MSB patterns are formed on the lower surface around the edges. In this way, the redistribution process for selecting one chip (i.e., a good chip) from the first and second chips of the partially-failed package can be achieved.
- Furthermore, although the disclosed embodiments show designs with two chips on a substrate, embodiments using greater numbers of chips are well within the scope of this invention.
- Although the preferred embodiments of the present invention have been described in detail above, it should be understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the art will still fall within the spirit and scope of the present invention as defined in the appended claims.
Claims (13)
1. A repairable multi-chip package comprising:
a substrate;
a first chip formed over the substrate, having a plurality of first terminals;
a second chip formed over the substrate, having a plurality of second terminals;
a molding part comprising molding resin formed over the first chip and the second chip; and
a plurality of wiring patterns formed in the substrate and having portions extending beyond the molding part, the wiring patterns being electrically connected to the first and second chips through the first and second terminals, respectively,
wherein the plurality of wiring patterns are arranged such that if one of the first and second chips is non-functional and the other of the first and second chips is functional, the portions of the wiring patterns extending beyond the molding part can be by selectively cut to allow the functional chip to operate.
2. A repairable multi-chip package, as recited in , wherein the plurality of first and second terminals each comprise a first power terminal, a first ground terminal, a second power terminal, a most significant bit (MSB) terminal, a second ground terminal, and a dual terminal.
claim 1
3. A repairable multi-chip package, as recited in ,
claim 2
wherein the first power terminal and the first ground terminal of the first chip are formed on a first edge of a first active surface of the first chip,
wherein the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are formed on a second edge of the first active surface,
wherein the first power terminal and the first ground terminal of the second are formed on a first edge of a second active surface of the second chip, and
wherein the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are formed on a second edge of the second active surface.
4. A repairable multi-chip package, as recited in , wherein the wiring patterns further comprise:
claim 2
a plurality of ground patterns for connecting the first and second chips to a ground voltage;
a plurality of power patterns for connecting the first and second chip to a supply voltage;
a plurality of dual patterns for transmitting a signal for the dual operation of the first and second chips to the first and second chips; and
a plurality of most significant bit (MSB) patterns for selecting one of the first and second chips.
5. A repairable multi-chip package, as recited in , wherein the plurality of ground patterns comprise:
claim 4
a first ground pattern connected to the first ground terminal of the first chip; and
a second ground pattern connected to the second ground terminal of the second chip.
6. A repairable multi-chip package, as recited in , wherein the plurality of power patterns comprise:
claim 5
a first power pattern connected to the first power terminal of the first chip and extending beyond the molding part; and
a second power pattern connected to the first power terminal of the second chip, and to the first power pattern beyond the molding part.
7. A repairable multi-chip package, as recited in , wherein the second power pattern is formed inside of the plurality of ground patterns to prevent interference between the second power pattern and the first ground pattern.
claim 6
8. A repairable multi-chip package, as recited in , wherein the plurality of dual patterns comprise:
claim 6
a first dual pattern connected to the dual terminal and the second ground terminal of the first chip and extending beyond the molding part;
a second dual pattern connected to the dual terminal and the second ground terminal of the second chip and extending beyond the molding part; and
a third dual pattern connecting the first and second dual patterns together.
9. A repairable multi-chip package, as recited in , wherein the plurality of dual patterns further comprises:
claim 8
a fourth dual pattern connected to the second ground terminal of the first chip; and
a fifth dual pattern connected to the second ground terminal of the second chip,
wherein the third dual pattern connects the first, second, fourth, and fifth dual patterns together.
10. A repairable multi-chip package, as recited in , wherein the plurality of MSB patterns comprise:
claim 9
a plurality of first MSB patterns connected to the MSB terminal and the second ground terminal of the first chip and extending beyond the molding part;
a second MSB pattern formed beyond the molding part and connected to the first MSB patterns; and
a third MSB pattern connected to the second power terminal of the second chip, and to the second MSB pattern between two of the first MSB patterns.
11. The repairable multi-chip package of , wherein a portion of the third MSB pattern is formed within the perimeter of the first and second chips.
claim 10
12. The repairable multi-chip package of , wherein the wiring patterns are formed such that if the first chip is a functioning chip and the second chip is a non-functioning chip, the second chip can be isolated by cutting the second power pattern, the third MSB pattern, the first dual pattern, and the second dual pattern, all beyond the molding part.
claim 10
13. The repairable multi-chip package of , wherein the wiring patterns are formed such that if the first chip is a non-functioning chip and the second chip is a functioning chip, the first chip can be isolated by cutting the first power pattern, the first MSB patterns, the first dual pattern, and the second dual pattern, all beyond the molding, part.
claim 10
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR2000-20982 | 2000-04-20 | ||
KR1020000020982A KR100336281B1 (en) | 2000-04-20 | 2000-04-20 | Repairable multi chip package |
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US20010033013A1 true US20010033013A1 (en) | 2001-10-25 |
US6388312B2 US6388312B2 (en) | 2002-05-14 |
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Also Published As
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US6388312B2 (en) | 2002-05-14 |
KR20010097153A (en) | 2001-11-08 |
JP2001358284A (en) | 2001-12-26 |
JP4204764B2 (en) | 2009-01-07 |
KR100336281B1 (en) | 2002-05-13 |
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