US20010036704A1 - Trench semiconductor device manufacture with a thicker upper insulating layer - Google Patents

Trench semiconductor device manufacture with a thicker upper insulating layer Download PDF

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US20010036704A1
US20010036704A1 US09/840,816 US84081601A US2001036704A1 US 20010036704 A1 US20010036704 A1 US 20010036704A1 US 84081601 A US84081601 A US 84081601A US 2001036704 A1 US2001036704 A1 US 2001036704A1
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trench
insulating layer
electrode
layer
filler material
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Raymond Hueting
Cornelis Timmering
Henricus Maas
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Nexperia BV
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Koninklijke Philips Electronics NV
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/781—Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole

Definitions

  • This invention relates to methods of manufacturing semiconductor devices that have an electrode in an insulated trench, for example as a trench-gate of a power MOSFET or other field-effect device.
  • the invention relates particularly to process steps for lining the trench walls with a lower insulating layer in a lower part of the trench and with a thicker upper insulating layer in an upper part of the trench.
  • WO 99/43029 describes a trench-gate MOS transistor having a lower insulating layer lining a lower part of the trench and a thicker upper insulating layer lining an upper part of the trench. Source-drain regions are present adjacent to the thicker upper insulating layer. Embodiments of the transistor are disclosed that are suitable for EEPROM devices. In an EEPROM embodiment, the trench-gate extends into (but not through) a channel-accommodating region, and the source and drain regions are located at the same surface of the body, but at opposite sides of the trench-gate. The whole contents of WO 99/43029 are hereby incorporated herein as reference material.
  • WO 99/43029 describes and claims a process for forming the insulated trench by process steps that include:
  • This process requires a photolithographic alignment of a mask defining the narrow deep trench in relation to the wide shallow trench.
  • a lateral displacement error in this alignment renders the upper insulating layer thicker on one side of the trench than on the other side.
  • the insulated trench is formed by process steps that include:
  • the filler material and the further layer of different material may be selectively etchable with respect to each other, and one or other may be oxidation-resistant, and/or an electrode material of the device, and/or an insulating material of the device.
  • the filler material may be used in both the lower and upper parts of the trench, or in just one part of the trench.
  • the filler material and/or the further layer may be retained in the manufactured device or removed.
  • the bottom of the trench may be free of the lower insulating layer, so that the electrode may contact a region of the body at the bottom of the trench.
  • the trench may provide an insulated via for the electrode from the surface of the body to a buried region of the body.
  • this electrode may be, for example, a collector connection or a drain connection.
  • the invention is particularly useful for providing compact insulated trench-gate structures in field-effect devices.
  • the trench may be etched into a channel-accommodating region of the device.
  • the lower insulating layer may be provided on the bottom of the trench as well as on the lower part of its side walls. Source and/or drain regions may be formed in the body adjacent to the thicker upper insulating layer.
  • This trench-gate field-effect structure may be used for an EEPROM, for example as in WO 99/43029.
  • the invention is of particular utility for a power MOSFET comprising a pattern of transistor cells bounded by the trench-gate. It is particularly useful to provide the thicker insulating layer between the transistor drain and the gate.
  • the field-effect device may be an inverted transistor having drain regions adjacent to the thicker upper insulating layer.
  • the trench may extend through the thickness of the channel-accommodating region to reach an underlying source region adjacent to the lower insulating layer.
  • FIG. 1 is a cross-sectional view of an active central part of a trench-gate power MOSFET manufactured by a method in accordance with the invention
  • FIGS. 2A to 2 G are cross-sectional views of a trench-gate area of such a MOSFET at successive stages in its manufacture by process steps in accordance with one embodiment of the invention, with a sacrificial (silicon nitride) filler material;
  • FIGS. 3A to 3 D are similar cross-sectional views of a trench-gate area of the MOSFET at successive stages in its manufacture by process steps in accordance with another embodiment of the invention, with an electrode (field plate) filler material;
  • FIGS. 4A to 4 G are similar cross-sectional views of a trench-gate area of the MOSFET at successive stages in its manufacture by process steps in accordance with a further embodiment of the invention, with a further layer that may be kept in the device;
  • FIGS. 5A to 5 H are similar cross-sectional views of a trench-gate area of the MOSFET at successive stages in its manufacture by process steps in accordance with yet another embodiment of the invention, with a sacrificial further layer;
  • FIG. 6 is a cross-sectional view of a trench-gate area of a different trench-gate MOS transistor (an EEPROM-type MOST) manufactured by a method in accordance with the invention.
  • FIG. 7 is a cross-sectional view of a trench-electrode area of a further semiconductor device (bipolar transistor) manufactured by a method in accordance with the invention.
  • FIG. 1 illustrates an exemplary embodiment of a cellular trench-gate field-effect power transistor manufactured in accordance with the invention.
  • the transistor comprises a semiconductor body 10 having a top major surface 10 a from which a trench 20 with a trench-gate structure 11 , 21 , 22 extends into the body 10 .
  • the transistor is of the MOSFET type comprising a gate electrode 11 on a gate dielectric layer 21 .
  • the layer 21 lines a lower part of the trench 20 , including its bottom 20 b.
  • This insulated trench-gate 11 extends through a channel-accommodating portion 15 a of a body region 15 of a first conductivity type (p-type in this embodiment), between drain and source regions 14 and 13 of an opposite second conductivity type (n-type in this embodiment).
  • the application of a voltage signal to the gate electrode 11 in the on-state of the device serves in known manner for inducing a conduction channel 12 in the region portion 15 a and for controlling current flow in this conduction channel 12 between the source and drain regions 13 and 14 .
  • the transistor is of an inverted configuration, in which the drain region 14 is adjacent to the top surface 10 a .
  • the trench 20 extends through the regions 14 and 15 into an underlying portion 13 a of the source region 13 .
  • the drain region 14 is contacted at the top major surface 10 a by a drain electrode 34 .
  • the drain electrode 34 extends over the trench-gate 11 from which it is insulated by an intermediate insulating layer 32 .
  • a drain drift region 14 a of lower doping concentration (n ⁇ ) than the drain region 14 (n+) is present between the drain region 14 and the underlying body region 15 .
  • the adjacent upper part of the trench 20 is lined with an upper dielectric layer 22 that is thicker than the gate dielectric 21 in the lower part of the trench 20 .
  • the upper part of the gate electrode 11 on this thicker dielectric 22 acts as a field plate.
  • FIG. 1 shows a discrete vertical device structure in which the source region 13 is a substrate of high conductivity (n+in this example), that is contacted by the source electrode 33 at the bottom major surface 10 b of the body 10 .
  • the transistor of FIG. 1 typically comprises tens of thousands of parallel device cells in the semiconductor body 10 adjacent to the body surface 10 a. The number of cells is dependent on the desired current-carrying capability of the device.
  • Trench-gate transistors manufactured in accordance with the invention may have any one of a variety of known cell geometries, for example an hexagonal close-packed geometry, or a square geometry, or an elongate stripe geometry.
  • the device has a plurality of the body regions 15 which are located side-by-side in the semiconductor body 10 , and the trench-gate structure 11 , 21 , 22 comprises grid portions which extend between the channel-accommodating portions 15 a of the neighbouring side-by-side body regions 15 , as illustrated in FIG. 1.
  • the source region 13 is common to all the cells.
  • the active cellular area of the device may be bounded around the periphery of the body 10 by various known peripheral termination schemes. Such schemes normally include the formation of a thick field-oxide layer at the peripheral area of the body surface 10 a , before the transistor cell fabrication steps.
  • the body 10 is of monocrystalline silicon
  • the trench-gate electrode 11 typically comprises doped polycrystalline silicon on a gate insulating layer 21 that comprises silicon dioxide
  • the electrodes 33 and 34 are of, for example, aluminium.
  • the doping concentration (p+) of the high-doped portion 15 b may be, for example, 10 18 to 10 19 boron atoms cm ⁇ 3
  • that (p) of the channel-accommodating portion 15 a may be, for example, 10 16 to 10 17 boron atoms cm ⁇ 3
  • that (n+) of the active source portion 13 a of the may be, for example, 10 19 to 10 21 phosphorus or arsenic atoms cm ⁇ 3
  • the dopant concentration (n+) of the source and drain regions may be, for example, 10 20 to 10 22 phosphorus or arsenic atoms cm ⁇ 3
  • the lower-doped drain drift region 14 a may have a doping concentration (n ⁇ )
  • the highly doped bottom portion 15 b of the body region 15 , the channel-accommodating portion 15 a of the body region 15 , the drain drift region 14 a and the drain region 14 may be formed as a stack of epitaxial layers on the substrate 13 .
  • the layer that forms the highly doped bottom portion 15 b of the body region 15 extends laterally to the trench-gate structure 11 , 12 where it is overdoped by the active portion 13 a of the source region 13 .
  • the insulated trench structure 20 , 21 , 22 is formed by process steps in accordance with the present invention. In overview, these steps include:
  • FIGS. 2A to 2 G FIGS. 3A to 3 D, FIGS. 4A to 4 G, and FIGS. 5A to 5 H.
  • This embodiment uses a sacrificial filler material 52 and employs an electrode material for the further layer 51 .
  • the electrode material for example, silicon
  • the electrode material 52 for example, silicon nitride
  • the trench 20 is etched in known manner into the surface 10 a of the silicon body 10 , for example at a window in an insulating layer 45 .
  • the thin gate dielectric layer 21 may then be formed in known manner (for example, by oxidation of the silicon trench walls, or by deposition of silicon dioxide) to line the walls and bottom of the trench 20 .
  • an electrode material for example, doped polycrystalline silicon
  • the layer 51 is typically more than 0.15 ⁇ m (micrometers) thick, depending on the desired drain voltage for the device.
  • the thickness of the layer 51 determines the width of the space 50 that is formed later (FIG. 2C) in this embodiment, and hence the thickness of the upper insulating layer 22 .
  • a sacrificial filler material 52 such as silicon nitride is then deposited over the layer 51 and is etched back so as to be left only in the trench 20 .
  • This filler material 52 extends in both the lower and upper parts of the trench 20 .
  • the resulting structure is illustrated in FIG. 2B.
  • the exposed polycrystalline silicon is then etched away, for a time sufficient to remove the further layer 51 from the upper part of the trench walls. As illustrated in FIG. 2C, the space 50 is formed between the upper part of the filler material 52 and the upper part of the trench walls.
  • Insulating material typically, silicon dioxide in the form of TEOS
  • TEOS silicon dioxide in the form of TEOS
  • the silicon dioxide is etched back (or chemically mechanically polished) to re-expose the silicon nitride filler material 52 . Thereafter, a selective etchant is used to etch away the filler material 52 from the upper insulating layer 22 of silicon dioxide and from the polycrystalline silicon layer 51 .
  • a selective etchant is used to etch away the filler material 52 from the upper insulating layer 22 of silicon dioxide and from the polycrystalline silicon layer 51 .
  • the resulting structure is illustrated in FIG. 2E.
  • Doped polycrystalline silicon 53 may then be deposited to form (with the existing polycrystalline silicon layer 51 ) the gate electrode 11 in the insulated trench 20 , 21 , 22 .
  • the remainder of the layer 51 is retained in the manufactured device as a lower part of the electrode 11 .
  • the polycrystalline silicon also deposits on the top of the body. The resulting structure is illustrated in FIG. 2F.
  • the upper insulating layer 22 of silicon dioxide may be formed by oxidation of the upper trench walls.
  • the silicon nitride material 52 can be used as an oxidation mask on the polycrystalline silicon layer 51 , although it is preferable for the thickness of the nitride material 52 to be reduced so as to reduce stress. In this case, because the layer 22 grows into the trench walls, the resulting oxide layer 22 is thicker than the width of the space 50 . Thereafter, the remaining silicon nitride material 52 is etched away from the silicon dioxide layer 22 with a selective etchant.
  • nitride instead of silicon nitride, other materials can be used for the sacrificial filler 52 in other variants of the process with a deposited layer 22 .
  • p+ (heavily boron doped) polycrystalline silicon may be used for the filler 52 of FIG. 2B.
  • Heavily boron-doped (p+) polycrystalline silicon etches much faster in KOH etchant than n+ polycrystalline silicon that can be used for the “further” layer 51 .
  • the FIG. 2C stage may therefore be obtained by etching with KOH.
  • PSG phosphosilicate glass
  • ozone-formed TEOS both of which have a fast etch rate and good etch selectivity with respect to silicon dioxide.
  • Either PSG or ozone-TEOS may be used for the sacrificial filler 52 .
  • This embodiment is similar to the first embodiment in that it employs an electrode material (for example, doped polycrystalline silicon) for the further layer 51 . It differs in also using an electrode material 52 ′ (for example, comprising a mixed germanium-silicon alloy) for the filler material. Both this filler material 52 ′ and the lower part of the further layer 51 are retained in the manufactured device as respective upper and lower parts of the electrode 11 . The resulting trench-gate structure is illustrated in FIG. 3D.
  • an electrode material for example, doped polycrystalline silicon
  • an electrode material 52 ′ for example, comprising a mixed germanium-silicon alloy
  • Electrode materials 51 and 52 ′ are selectively etchable with respect to each other, for example using KOH to etch the polycrystalline silicon. Similar process stages FIGS. 3A to 3 D may be followed as for FIGS. 2A to 2 D of the first embodiment.
  • a mixed germanium-silicon alloy is oxidation-resistant material.
  • the upper part of the trench walls can be oxidised to form the thicker upper insulating layer 22 of silicon dioxide when using a mixed germanium-silicon alloy for the filler material 52 ′.
  • the upper insulating layer 22 may alternatively be formed by deposition of silicon dioxide (TEOS).
  • TEOS silicon dioxide
  • an advantage of this second embodiment is a reduction in the number of process steps required to form the insulated trench 20 , 21 , 22 with its electrode 11 ( 51 , 52 ′).
  • This embodiment employs an insulating material and/or an oxidation resistant material (for example, silicon nitride) for the further layer 51 ′.
  • An electrode material for example, doped polycrystalline silicon
  • the further layer 51 ′ is selectively etchable with respect to the filler material 52 ′′.
  • the trench 20 is etched in known manner into the surface 10 a of the silicon body 10 .
  • the gate dielectric layer 21 may then be formed in known manner (for example, by oxidation of the silicon trench walls) to line the walls and bottom of the trench 20 . Only a thin layer 21 is formed in an embodiment in which the insulating further layer 51 ′ is retained in the manufactured device as part of the gate dielectric. In this case, the layer 21 is typically less than 50 nm (nanometer) thick.
  • the resulting structure is illustrated in FIG. 4A.
  • a material such as silicon nitride may be deposited to form the further layer 51 ′, as illustrated in FIG. 4B.
  • An electrode material 52 ′′ (such as doped polycrystalline silicon) may then be deposited over the layer 51 ′.
  • the deposited electrode material 52 ′′ is etched back so as to be left only in the lower part of the trench 20 , i.e. it is left only in the trench 20 at a required height that corresponds to a transition between the upper and lower parts of the trench 20 .
  • the resulting structure is illustrated in FIG. 4C.
  • the exposed silicon nitride 51 ′ is etched away so as to expose the upper part of the trench walls (or at least to expose the insulating layer 21 thereon).
  • This etching step is less critical than that for the layer 51 in FIGS. 2B and 3B, because it does not require any carefully timed etching along the length of a layer, parallel to the trench walls.
  • the resulting space 50 (adjacent to the upper part of the trench walls) that is exposed by the remaining nitride 51 ′ extends across the whole upper part of the trench 20 .
  • the upper part of the trench walls may be oxidised to form the thicker upper insulating layer 22 , while using the silicon nitride layer 51 ′ as an oxidation mask in the lower part of the trench.
  • TEOS deposition may be used to form the upper insulating layer 22 of silicon dioxide.
  • the silicon dioxide is then etched back with a directional etch to re-expose the electrode filler material 52 ′′, while leaving oxide spacers on the upper walls of the trench. This etch-back may also expose the top corner of the trench 20 .
  • the resulting structure is illustrated in FIG. 4E.
  • the process is such as to also expose the top corner of the trench 20 , then it is advantageous for the highly-doped n-type region 14 (n+) to be present already at the surface 10 a.
  • a further oxidation may then be performed to insulate this exposed top corner with a thick oxide, while growing only a thin oxide on the polycrystalline silicon 52 ′′. This is achievable because a high rate of oxide growth occurs on highly-doped n-type (n+) silicon.
  • the thin oxide may then be etched away from the polycrystalline silicon 52 ′′ while leaving a thick oxide on the n+ top corner of the trench 20 .
  • the resulting structure is illustrated in FIG. 4F.
  • electrode material 53 is deposited in the upper part of the trench 20 to provide the remainder of the electrode 11 with the electrode filler material 52 ′′.
  • An overlayer 32 of TEOS may then be deposited, or a thermal oxide overlayer 32 may be grown. The resulting structure is illustrated in FIG. 4G.
  • the filler material 52 ′′ need not be of electrode material and need not be retained in the manufactured device. It is possible to etch away the filler material 52 ′′ before the thick upper insulating layer 22 is formed by oxidising the upper part of the trench walls.
  • the layer 51 ′ is of silicon nitride, it may be retained in the manufactured device adjacent to the lower insulating layer 21 .
  • the resulting device has a compound gate dielectric 21 , 51 ′.
  • the further layer 51 ′ could even be of an electrode material (for example, a mixed germanium-silicon alloy) that is retained in the manufactured device as a lower part of the electrode 11 in the insulated trench 20 , 21 , 22 .
  • the layer 51 ′ may be etched away before depositing electrode material 53 in the insulated trench 20 , 21 , 22 . In this case, this later deposited electrode material 53 fills the insulated trench 20 , 21 , 22 and forms the whole of the electrode 11 .
  • the further layer 51 ′ and the filler material 52 ′′ may be of selectively-etchable oxidation-resistant materials.
  • One may be of, for example, a mixed silicon-germanium alloy, and the other of silicon nitride. Both may then be present as an oxidation mask in the lower part of the trench 20 , when the upper insulating layer 22 is formed by oxidation.
  • This embodiment uses a sacrificial layer 51 ′ and a sacrificial filler material 52 ′′.
  • the sacrificial layer 51 ′ comprises silicon nitride as an oxidation-resistant material
  • the sacrificial filler material 52 ′′ is polycrystalline silicon as being suitable for selective etching.
  • FIGS. 5A to 5 D are similar to those of FIGS. 4A to 4 D, except that the thickness of the insulating layer 21 is chosen to provide the whole of the gate dielectric 21 for the manufactured device.
  • the filler material 52 ′′ is etched away.
  • the silicon dioxide layer 21 is also etched away from the upper part of the trench where it is not masked by the silicon nitride layer 51 ′.
  • the resulting structure, as illustrated in FIG. 5E, has bare silicon walls to the upper part of the trench 20 .
  • the layer 51 ′ is then etched away from the lower part of the trench using a selective etchant that does not attack the oxide layer 22 . Thereafter, doped polycrystalline silicon or another electrode material 53 ′ is deposited to form the structure shown in FIG. 5G.
  • the electrode material 53 ′ is then etched back from off the top of the body 10 but is left in the insulated trench 20 , 21 , 22 to form the electrode 11 .
  • TEOS deposition can be carried out to provide the oxide layer 32 over the electrode 11 in the insulated trench 20 , 21 , 22 .
  • the resulting structure is illustrated in FIG. 5H.
  • Such processes for forming the insulated trench 20 , 21 , 22 in accordance with the present invention are particularly advantageous for providing a trench-gate 11 of an inverted power MOSFET device, such as that shown in FIG. 1.
  • the thin lower insulating layer 21 can provide the gate dielectric that couples the gate electrode 11 to the channel-accommodating region 15 a.
  • the upper part of the gate electrode 11 can function as a field plate across the thicker upper insulating layer 22 that separates it from most of the drain drift region 14 a, as well as from the high doped drain region 14 .
  • Quite high voltages for example, about 100 volts may be applied to the drain electrode 33 , with respect to the source and gate electrodes.
  • processes for forming an insulated trench 20 , 21 , 22 in accordance with the present invention are also advantageous in other device contexts.
  • FIG. 6 illustrates the provision of such an insulated trench 20 , 21 , 22 in an EEPROM-type MOS transistor.
  • both the source and drain regions 13 and 14 are present adjacent to the thick insulating layer 22 at the body surface 10 a .
  • the source and drain regions 13 and 14 are at opposite sides of the trench 20 .
  • the trench 20 is etched into (but not through) the channel-accommodating region 15 a of the device.
  • the lower insulating layer 21 provides the gate dielectric adjacent to the channel 12 that is formed around the bottom 20 b of the trench, as well as along the lower part of its side walls.
  • This trench-gate field-effect structure may be used for an EEPROM, for example as in WO 99/43029.
  • FIG. 7 illustrates a different situation, in which the bottom 20 b of the trench 20 is free of the lower insulating layer 21 .
  • the insulated trench 20 , 21 , 22 contains an electrode 41 that contacts a region 14 ′ of the body 10 at the bottom 20 b of the trench 20 .
  • the trench 20 provides an insulated via for the electrode 41 from the body surface 10 a to a buried region 10 14 ′ of the body 10 .
  • this electrode 41 may be, for example, a collector connection or a drain connection.
  • the trench 20 of the FIG. 7 device may be formed with an exposed thin insulating layer 21 both at the trench bottom 20 b and at its side walls. Then, the insulating layer 21 can be removed from the trench bottom 20 b by directional (i.e. anisotropic) etching before depositing the further layer 51 , 51 ′ or before depositing electrode material 53 ′ to fill the insulated trench 20 , 21 , 22 .
  • directional i.e. anisotropic
  • FIG. 7 has been chosen to show a bipolar transistor for the sake of variety.
  • This bipolar transistor has an emitter region 13 ′, a base region 15 a ′, a low-doped collector part 14 a ′ and a collector buried layer 14 ′.
  • Emitter, collector and base electrodes 33 ′, 34 ′, and 35 respectively contact the emitter region 13 ′, the collector connection 41 , and the base region 15 a ′ at windows in an insulating layer 40 on the body surface 10 a.
  • the thick upper insulating layer 22 separates the collector connection 41 from the base region 15 a.
  • the MOSFET device of FIG. 1 may comprise a network (or group) of trenches 20 that accommodate the gate 11 , and one or more separate trenches 20 ′ that accommodate a source electrode 41 ′.
  • This source electrode 41 ′ contacts the source region 13 at the un-insulated bottom 20 b′ of the trench 20 ′, in a similar manner to the electrode 41 of FIG. 7.

Abstract

In the manufacture of semiconductor devices that have an electrode (11,41) in an insulated trench (20), for example a trench-gate MOSFET, process steps are performed to line the trench walls with a lower insulating layer (21) in a lower part of the trench and with a thicker upper insulating layer (22) in an upper part of the trench. The steps include: (a) etching the trench (20); (b) providing the lower insulating layer (21) on the trench walls; (c) depositing on the lower insulating layer (21) a further layer (51) of a different material; (d) depositing on the further layer (51) a filler material (52) that is of a different material from the further layer (51); (e) etching away the further layer (51) from the upper part of the trench walls while using the filler material (52) as an etchant mask, so as to form a space (50) adjacent to the upper part of the trench walls while leaving the further layer (51) in the lower part of the trench; and (f) providing the thicker upper insulating layer (22) in the space (50) adjacent to the upper part of the trench walls.

Description

  • This invention relates to methods of manufacturing semiconductor devices that have an electrode in an insulated trench, for example as a trench-gate of a power MOSFET or other field-effect device. The invention relates particularly to process steps for lining the trench walls with a lower insulating layer in a lower part of the trench and with a thicker upper insulating layer in an upper part of the trench. [0001]
  • Published PCT patent application WO 99/43029 describes a trench-gate MOS transistor having a lower insulating layer lining a lower part of the trench and a thicker upper insulating layer lining an upper part of the trench. Source-drain regions are present adjacent to the thicker upper insulating layer. Embodiments of the transistor are disclosed that are suitable for EEPROM devices. In an EEPROM embodiment, the trench-gate extends into (but not through) a channel-accommodating region, and the source and drain regions are located at the same surface of the body, but at opposite sides of the trench-gate. The whole contents of WO 99/43029 are hereby incorporated herein as reference material. [0002]
  • WO 99/43029 describes and claims a process for forming the insulated trench by process steps that include: [0003]
  • etching a wide but shallow trench into the semiconductor body from one surface of the body, [0004]
  • filling the wide shallow trench with insulating material for forming the upper insulating layer on the trench walls, [0005]
  • etching a narrow but deep trench into the semiconductor body through the insulating filling of the wide shallow trench, [0006]
  • forming the lower insulating layer on the etched surfaces of the narrow deep trench below the wide shallow trench. [0007]
  • This process requires a photolithographic alignment of a mask defining the narrow deep trench in relation to the wide shallow trench. A lateral displacement error in this alignment renders the upper insulating layer thicker on one side of the trench than on the other side. [0008]
  • It is an aim of the present invention to provide an alternative adaptable process in which the definition of a thicker upper insulating layer in an upper part of the trench can be self-aligned with a lower insulating layer in a lower part of the trench. [0009]
  • According to the present invention, the insulated trench is formed by process steps that include: [0010]
  • (a) etching the trench into a semiconductor body from one surface of the body, [0011]
  • (b) providing the lower insulating layer on the trench walls, [0012]
  • (c) depositing on the lower insulating layer a further layer of a different material from that of the lower insulating layer, [0013]
  • (d) depositing on the further layer a filler material that is of a different material from the further layer, [0014]
  • (e) etching away the further layer from the upper part of the trench walls while using the filler material as an etchant mask, so as to form a space adjacent to the upper part of the trench walls while leaving the further layer in the lower part of the trench, [0015]
  • and (f) providing the thicker upper insulating layer in the space adjacent to the upper part of the trench walls. [0016]
  • Such a process approach not only permits the desired self-alignment but also is readily implemented in a variety of electrode and insulator technologies suitable for use in a wide variety of devices. Several particularly advantageous features and options available with the invention are set out in the appended Claims. [0017]
  • Thus, for example, the filler material and the further layer of different material may be selectively etchable with respect to each other, and one or other may be oxidation-resistant, and/or an electrode material of the device, and/or an insulating material of the device. The filler material may be used in both the lower and upper parts of the trench, or in just one part of the trench. The filler material and/or the further layer may be retained in the manufactured device or removed. [0018]
  • The bottom of the trench may be free of the lower insulating layer, so that the electrode may contact a region of the body at the bottom of the trench. Thus, the trench may provide an insulated via for the electrode from the surface of the body to a buried region of the body. In the case of a discrete device or integrated circuit comprising a transistor, this electrode may be, for example, a collector connection or a drain connection. [0019]
  • The invention is particularly useful for providing compact insulated trench-gate structures in field-effect devices. Thus, the trench may be etched into a channel-accommodating region of the device. The lower insulating layer may be provided on the bottom of the trench as well as on the lower part of its side walls. Source and/or drain regions may be formed in the body adjacent to the thicker upper insulating layer. [0020]
  • This trench-gate field-effect structure may be used for an EEPROM, for example as in WO 99/43029. However, the invention is of particular utility for a power MOSFET comprising a pattern of transistor cells bounded by the trench-gate. It is particularly useful to provide the thicker insulating layer between the transistor drain and the gate. Thus, the field-effect device may be an inverted transistor having drain regions adjacent to the thicker upper insulating layer. The trench may extend through the thickness of the channel-accommodating region to reach an underlying source region adjacent to the lower insulating layer.[0021]
  • These and other features of the present invention are illustrated in embodiments of the invention now described, by way of example, with reference to the accompanying drawings, in which: [0022]
  • FIG. 1 is a cross-sectional view of an active central part of a trench-gate power MOSFET manufactured by a method in accordance with the invention; [0023]
  • FIGS. 2A to [0024] 2G are cross-sectional views of a trench-gate area of such a MOSFET at successive stages in its manufacture by process steps in accordance with one embodiment of the invention, with a sacrificial (silicon nitride) filler material;
  • FIGS. 3A to [0025] 3D are similar cross-sectional views of a trench-gate area of the MOSFET at successive stages in its manufacture by process steps in accordance with another embodiment of the invention, with an electrode (field plate) filler material;
  • FIGS. 4A to [0026] 4G are similar cross-sectional views of a trench-gate area of the MOSFET at successive stages in its manufacture by process steps in accordance with a further embodiment of the invention, with a further layer that may be kept in the device;
  • FIGS. 5A to [0027] 5H are similar cross-sectional views of a trench-gate area of the MOSFET at successive stages in its manufacture by process steps in accordance with yet another embodiment of the invention, with a sacrificial further layer;
  • FIG. 6 is a cross-sectional view of a trench-gate area of a different trench-gate MOS transistor (an EEPROM-type MOST) manufactured by a method in accordance with the invention; and [0028]
  • FIG. 7 is a cross-sectional view of a trench-electrode area of a further semiconductor device (bipolar transistor) manufactured by a method in accordance with the invention.[0029]
  • It should be noted that all the Figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. [0030]
  • FIG. 1 illustrates an exemplary embodiment of a cellular trench-gate field-effect power transistor manufactured in accordance with the invention. The transistor comprises a [0031] semiconductor body 10 having a top major surface 10 a from which a trench 20 with a trench-gate structure 11,21,22 extends into the body 10. The transistor is of the MOSFET type comprising a gate electrode 11 on a gate dielectric layer 21. The layer 21 lines a lower part of the trench 20, including its bottom 20 b. This insulated trench-gate 11 extends through a channel-accommodating portion 15 a of a body region 15 of a first conductivity type (p-type in this embodiment), between drain and source regions 14 and 13 of an opposite second conductivity type (n-type in this embodiment). The application of a voltage signal to the gate electrode 11 in the on-state of the device serves in known manner for inducing a conduction channel 12 in the region portion 15 a and for controlling current flow in this conduction channel 12 between the source and drain regions 13 and 14.
  • The transistor is of an inverted configuration, in which the [0032] drain region 14 is adjacent to the top surface 10 a. Thus, the trench 20 extends through the regions 14 and 15 into an underlying portion 13 a of the source region 13. The drain region 14 is contacted at the top major surface 10 a by a drain electrode 34. The drain electrode 34 extends over the trench-gate 11 from which it is insulated by an intermediate insulating layer 32. A drain drift region 14 a of lower doping concentration (n−) than the drain region 14 (n+) is present between the drain region 14 and the underlying body region 15. The adjacent upper part of the trench 20 is lined with an upper dielectric layer 22 that is thicker than the gate dielectric 21 in the lower part of the trench 20. The upper part of the gate electrode 11 on this thicker dielectric 22 acts as a field plate.
  • In the inverted configuration of this transistor, a part of the body region [0033] 15 is electrically shorted to the underlying source region 13 by a buried electrical short 5 in the form of a leaky p-n junction. A highly doped bottom portion 15 b (p+) forms the leaky p-n junction 5 with the source region 13 at an area that is separated laterally from the trench-gate structure 11,12 by an active portion 13 a of the source region 13 adjacent to the trench-gate structure 11,12. This short 5 pins the potential of the body region 15 to that of the source region 13. By way of example, FIG. 1 shows a discrete vertical device structure in which the source region 13 is a substrate of high conductivity (n+in this example), that is contacted by the source electrode 33 at the bottom major surface 10 b of the body 10.
  • The transistor of FIG. 1 typically comprises tens of thousands of parallel device cells in the [0034] semiconductor body 10 adjacent to the body surface 10 a. The number of cells is dependent on the desired current-carrying capability of the device. Trench-gate transistors manufactured in accordance with the invention may have any one of a variety of known cell geometries, for example an hexagonal close-packed geometry, or a square geometry, or an elongate stripe geometry. In each case, the device has a plurality of the body regions 15 which are located side-by-side in the semiconductor body 10, and the trench-gate structure 11,21,22 comprises grid portions which extend between the channel-accommodating portions 15 a of the neighbouring side-by-side body regions 15, as illustrated in FIG. 1. The source region 13 is common to all the cells. The active cellular area of the device may be bounded around the periphery of the body 10 by various known peripheral termination schemes. Such schemes normally include the formation of a thick field-oxide layer at the peripheral area of the body surface 10 a, before the transistor cell fabrication steps.
  • Typically, the [0035] body 10 is of monocrystalline silicon, the trench-gate electrode 11 typically comprises doped polycrystalline silicon on a gate insulating layer 21 that comprises silicon dioxide, and the electrodes 33 and 34 are of, for example, aluminium. In a typical embodiment, the doping concentration (p+) of the high-doped portion 15 b may be, for example, 1018 to 1019 boron atoms cm−3, that (p) of the channel-accommodating portion 15 a may be, for example, 1016 to 1017 boron atoms cm−3, that (n+) of the active source portion 13 a of the may be, for example, 1019 to 1021 phosphorus or arsenic atoms cm−3, and the dopant concentration (n+) of the source and drain regions may be, for example, 1020 to 1022 phosphorus or arsenic atoms cm−3. The lower-doped drain drift region 14 a may have a doping concentration (n−) that is uniform or that reduces with depth, for example from about 3×1017 at the interface with drain region 14 to about 1016 at the interface with the body region 15.
  • In the case of the discrete vertical device structure illustrated in FIG. 1, the highly doped bottom portion [0036] 15 b of the body region 15, the channel-accommodating portion 15 a of the body region 15, the drain drift region 14 a and the drain region 14 may be formed as a stack of epitaxial layers on the substrate 13. In this case, the layer that forms the highly doped bottom portion 15 b of the body region 15 extends laterally to the trench-gate structure 11,12 where it is overdoped by the active portion 13 a of the source region 13.
  • The insulated [0037] trench structure 20,21,22 is formed by process steps in accordance with the present invention. In overview, these steps include:
  • (a) etching the [0038] trench 20 into the body 10 from the surface 10 a,
  • (b) providing the lower insulating [0039] layer 21 on the trench walls,
  • (c) depositing on the lower insulating layer [0040] 21 a further layer 51 of a different material from that of the lower insulating layer 21,
  • (d) depositing on the further layer [0041] 51 a filler material 52 that is of a different material from the further layer 51,
  • (e) etching away the [0042] further layer 51 from the upper part of the trench walls while using the filler material 52 as an etchant mask, so as to form a space 50 adjacent to the upper part of the trench walls while leaving the further layer 51 in the lower part of the trench,
  • and (f providing the thicker upper insulating [0043] layer 22 in the space 50 adjacent to the upper part of the trench walls.
  • Various specific embodiments with different material technologies will now be described with reference to FIGS. 2A to [0044] 2G, FIGS. 3A to 3D, FIGS. 4A to 4G, and FIGS. 5A to 5H.
    • FIRST EMBODIMENT FIGS. 2A to 2G
  • This embodiment uses a [0045] sacrificial filler material 52 and employs an electrode material for the further layer 51. The electrode material (for example, silicon) for the further layer 51 is selectively etchable with respect to the sacrificial filler material 52 (for example, silicon nitride).
  • The [0046] trench 20 is etched in known manner into the surface 10 a of the silicon body 10, for example at a window in an insulating layer 45. The thin gate dielectric layer 21 may then be formed in known manner (for example, by oxidation of the silicon trench walls, or by deposition of silicon dioxide) to line the walls and bottom of the trench 20.
  • Next, an electrode material (for example, doped polycrystalline silicon) is deposited to form the [0047] further layer 51. The resulting structure is illustrated in FIG. 2A. The layer 51 is typically more than 0.15 μm (micrometers) thick, depending on the desired drain voltage for the device. The thickness of the layer 51 determines the width of the space 50 that is formed later (FIG. 2C) in this embodiment, and hence the thickness of the upper insulating layer 22.
  • A [0048] sacrificial filler material 52 such as silicon nitride is then deposited over the layer 51 and is etched back so as to be left only in the trench 20. This filler material 52 extends in both the lower and upper parts of the trench 20. The resulting structure is illustrated in FIG. 2B.
  • The exposed polycrystalline silicon is then etched away, for a time sufficient to remove the [0049] further layer 51 from the upper part of the trench walls. As illustrated in FIG. 2C, the space 50 is formed between the upper part of the filler material 52 and the upper part of the trench walls.
  • Insulating material (typically, silicon dioxide in the form of TEOS) is then deposited to provide the thicker upper insulating [0050] layer 22 in the space 50 between the filler material 52 and the upper part of the trench walls. The silicon dioxide material 22 also deposits over the filler material 52. The resulting structure is illustrated in FIG. 2D.
  • The silicon dioxide is etched back (or chemically mechanically polished) to re-expose the silicon [0051] nitride filler material 52. Thereafter, a selective etchant is used to etch away the filler material 52 from the upper insulating layer 22 of silicon dioxide and from the polycrystalline silicon layer 51. The resulting structure is illustrated in FIG. 2E.
  • Doped [0052] polycrystalline silicon 53 may then be deposited to form (with the existing polycrystalline silicon layer 51) the gate electrode 11 in the insulated trench 20,21,22. Thus, in this embodiment, the remainder of the layer 51 is retained in the manufactured device as a lower part of the electrode 11. The polycrystalline silicon also deposits on the top of the body. The resulting structure is illustrated in FIG. 2F.
  • Thereafter, the excess polycrystalline silicon is etched away from the top of the body, and another [0053] TEOS oxide layer 32 may be deposited over the trench-gate structure 11,21,22. The resulting structure is illustrated in FIG. 2G.
  • In a modification of the FIGS. 2C to [0054] 2D stages of this embodiment, the upper insulating layer 22 of silicon dioxide may be formed by oxidation of the upper trench walls. During the oxidation, the silicon nitride material 52 can be used as an oxidation mask on the polycrystalline silicon layer 51, although it is preferable for the thickness of the nitride material 52 to be reduced so as to reduce stress. In this case, because the layer 22 grows into the trench walls, the resulting oxide layer 22 is thicker than the width of the space 50. Thereafter, the remaining silicon nitride material 52 is etched away from the silicon dioxide layer 22 with a selective etchant.
  • Instead of silicon nitride, other materials can be used for the [0055] sacrificial filler 52 in other variants of the process with a deposited layer 22. Thus, for example, p+ (heavily boron doped) polycrystalline silicon may be used for the filler 52 of FIG. 2B. Heavily boron-doped (p+) polycrystalline silicon etches much faster in KOH etchant than n+ polycrystalline silicon that can be used for the “further” layer 51. The FIG. 2C stage may therefore be obtained by etching with KOH. Other possibilities are, for example, PSG (phosphosilicate glass) and ozone-formed TEOS, both of which have a fast etch rate and good etch selectivity with respect to silicon dioxide. Either PSG or ozone-TEOS may be used for the sacrificial filler 52.
    • SECOND EMBODIMENT FIGS. 3A to 3D
  • This embodiment is similar to the first embodiment in that it employs an electrode material (for example, doped polycrystalline silicon) for the [0056] further layer 51. It differs in also using an electrode material 52′ (for example, comprising a mixed germanium-silicon alloy) for the filler material. Both this filler material 52′ and the lower part of the further layer 51 are retained in the manufactured device as respective upper and lower parts of the electrode 11. The resulting trench-gate structure is illustrated in FIG. 3D.
  • These [0057] electrode materials 51 and 52′ are selectively etchable with respect to each other, for example using KOH to etch the polycrystalline silicon. Similar process stages FIGS. 3A to 3D may be followed as for FIGS. 2A to 2D of the first embodiment. A mixed germanium-silicon alloy is oxidation-resistant material. Thus, the upper part of the trench walls can be oxidised to form the thicker upper insulating layer 22 of silicon dioxide when using a mixed germanium-silicon alloy for the filler material 52′. However, the upper insulating layer 22 may alternatively be formed by deposition of silicon dioxide (TEOS). As compared with the first embodiment, an advantage of this second embodiment is a reduction in the number of process steps required to form the insulated trench 20,21,22 with its electrode 11 (51,52′).
    • THIRD EMBODIMENT FIGS. 4A to 4G
  • This embodiment employs an insulating material and/or an oxidation resistant material (for example, silicon nitride) for the [0058] further layer 51′. An electrode material (for example, doped polycrystalline silicon) may be used for the filler material 52″. Whatever specific materials are used, the further layer 51′ is selectively etchable with respect to the filler material 52″.
  • The [0059] trench 20 is etched in known manner into the surface 10 a of the silicon body 10. The gate dielectric layer 21 may then be formed in known manner (for example, by oxidation of the silicon trench walls) to line the walls and bottom of the trench 20. Only a thin layer 21 is formed in an embodiment in which the insulating further layer 51′ is retained in the manufactured device as part of the gate dielectric. In this case, the layer 21 is typically less than 50nm (nanometer) thick. The resulting structure is illustrated in FIG. 4A.
  • Next, a material such as silicon nitride may be deposited to form the [0060] further layer 51′, as illustrated in FIG. 4B. An electrode material 52″ (such as doped polycrystalline silicon) may then be deposited over the layer 51′. The deposited electrode material 52″ is etched back so as to be left only in the lower part of the trench 20, i.e. it is left only in the trench 20 at a required height that corresponds to a transition between the upper and lower parts of the trench 20. The resulting structure is illustrated in FIG. 4C.
  • While using the [0061] filler material 52″ as an etchant mask, the exposed silicon nitride 51′ is etched away so as to expose the upper part of the trench walls (or at least to expose the insulating layer 21 thereon). This etching step is less critical than that for the layer 51 in FIGS. 2B and 3B, because it does not require any carefully timed etching along the length of a layer, parallel to the trench walls. As illustrated in FIG. 4D, the resulting space 50 (adjacent to the upper part of the trench walls) that is exposed by the remaining nitride 51′ extends across the whole upper part of the trench 20.
  • Next, the upper part of the trench walls may be oxidised to form the thicker upper insulating [0062] layer 22, while using the silicon nitride layer 51′ as an oxidation mask in the lower part of the trench. However, instead of thermal oxidation, TEOS deposition may be used to form the upper insulating layer 22 of silicon dioxide. The silicon dioxide is then etched back with a directional etch to re-expose the electrode filler material 52″, while leaving oxide spacers on the upper walls of the trench. This etch-back may also expose the top corner of the trench 20. The resulting structure is illustrated in FIG. 4E.
  • If the process is such as to also expose the top corner of the [0063] trench 20, then it is advantageous for the highly-doped n-type region 14 (n+) to be present already at the surface 10 a. A further oxidation may then be performed to insulate this exposed top corner with a thick oxide, while growing only a thin oxide on the polycrystalline silicon 52″. This is achievable because a high rate of oxide growth occurs on highly-doped n-type (n+) silicon. The thin oxide may then be etched away from the polycrystalline silicon 52″ while leaving a thick oxide on the n+ top corner of the trench 20. The resulting structure is illustrated in FIG. 4F.
  • Thereafter [0064] electrode material 53 is deposited in the upper part of the trench 20 to provide the remainder of the electrode 11 with the electrode filler material 52″. An overlayer 32 of TEOS may then be deposited, or a thermal oxide overlayer 32 may be grown. The resulting structure is illustrated in FIG. 4G.
  • Many modifications will be apparent. Thus, the [0065] filler material 52″ need not be of electrode material and need not be retained in the manufactured device. It is possible to etch away the filler material 52″ before the thick upper insulating layer 22 is formed by oxidising the upper part of the trench walls.
  • When the [0066] layer 51′ is of silicon nitride, it may be retained in the manufactured device adjacent to the lower insulating layer 21. The resulting device has a compound gate dielectric 21,51′. However, the further layer 51′ could even be of an electrode material (for example, a mixed germanium-silicon alloy) that is retained in the manufactured device as a lower part of the electrode 11 in the insulated trench 20,21,22. Alternatively, the layer 51′ may be etched away before depositing electrode material 53 in the insulated trench 20,21,22. In this case, this later deposited electrode material 53 fills the insulated trench 20,21,22 and forms the whole of the electrode 11.
  • The [0067] further layer 51′ and the filler material 52″ may be of selectively-etchable oxidation-resistant materials. One may be of, for example, a mixed silicon-germanium alloy, and the other of silicon nitride. Both may then be present as an oxidation mask in the lower part of the trench 20, when the upper insulating layer 22 is formed by oxidation.
    • FOURTH EMBODIMENT FIGS. 5A to 5H
  • This embodiment uses a [0068] sacrificial layer 51′ and a sacrificial filler material 52″. In the specific example now to be described, the sacrificial layer 51′ comprises silicon nitride as an oxidation-resistant material, and the sacrificial filler material 52″ is polycrystalline silicon as being suitable for selective etching.
  • The process stages of FIGS. 5A to [0069] 5D are similar to those of FIGS. 4A to 4D, except that the thickness of the insulating layer 21 is chosen to provide the whole of the gate dielectric 21 for the manufactured device.
  • Next, the [0070] filler material 52″ is etched away. The silicon dioxide layer 21 is also etched away from the upper part of the trench where it is not masked by the silicon nitride layer 51′. The resulting structure, as illustrated in FIG. 5E, has bare silicon walls to the upper part of the trench 20.
  • Using the [0071] silicon nitride layer 51′ as a mask, thermal oxidation of the bare silicon is then carried out to form the thick upper insulating layer 22, as shown in FIG. 5F.
  • The [0072] layer 51′ is then etched away from the lower part of the trench using a selective etchant that does not attack the oxide layer 22. Thereafter, doped polycrystalline silicon or another electrode material 53′ is deposited to form the structure shown in FIG. 5G.
  • The [0073] electrode material 53′ is then etched back from off the top of the body 10 but is left in the insulated trench 20,21,22 to form the electrode 11. TEOS deposition can be carried out to provide the oxide layer 32 over the electrode 11 in the insulated trench 20,21,22. The resulting structure is illustrated in FIG. 5H.
    • DIFFERENT DEVICE EMBODIMENTS FIGS. 1, 6, & 7
  • Such processes for forming the [0074] insulated trench 20,21,22 in accordance with the present invention are particularly advantageous for providing a trench-gate 11 of an inverted power MOSFET device, such as that shown in FIG. 1. Thus, the thin lower insulating layer 21 can provide the gate dielectric that couples the gate electrode 11 to the channel-accommodating region 15 a. The upper part of the gate electrode 11 can function as a field plate across the thicker upper insulating layer 22 that separates it from most of the drain drift region 14 a, as well as from the high doped drain region 14. Quite high voltages, for example, about 100 volts may be applied to the drain electrode 33, with respect to the source and gate electrodes. However, processes for forming an insulated trench 20,21,22 in accordance with the present invention are also advantageous in other device contexts.
  • Thus, for example, FIG. 6 illustrates the provision of such an [0075] insulated trench 20,21,22 in an EEPROM-type MOS transistor. In this case, both the source and drain regions 13 and 14 are present adjacent to the thick insulating layer 22 at the body surface 10 a. The source and drain regions 13 and 14 are at opposite sides of the trench 20. The trench 20 is etched into (but not through) the channel-accommodating region 15 a of the device. The lower insulating layer 21 provides the gate dielectric adjacent to the channel 12 that is formed around the bottom 20 b of the trench, as well as along the lower part of its side walls. This trench-gate field-effect structure may be used for an EEPROM, for example as in WO 99/43029.
  • FIG. 7 illustrates a different situation, in which the bottom [0076] 20 b of the trench 20 is free of the lower insulating layer 21. In this case, the insulated trench 20,21,22 contains an electrode 41 that contacts a region 14′ of the body 10 at the bottom 20 b of the trench 20. Thus, the trench 20 provides an insulated via for the electrode 41 from the body surface 10 a to a buried region 10 14′ of the body 10. In the case of a discrete device or integrated circuit comprising a transistor, this electrode 41 may be, for example, a collector connection or a drain connection.
  • The [0077] trench 20 of the FIG. 7 device may be formed with an exposed thin insulating layer 21 both at the trench bottom 20 b and at its side walls. Then, the insulating layer 21 can be removed from the trench bottom 20b by directional (i.e. anisotropic) etching before depositing the further layer 51,51′ or before depositing electrode material 53′ to fill the insulated trench 20,21,22.
  • As FIGS. 1 and 6 show field-effect transistors, FIG. 7 has been chosen to show a bipolar transistor for the sake of variety. This bipolar transistor has an [0078] emitter region 13′, a base region 15 a′, a low-doped collector part 14 a′ and a collector buried layer 14′. Emitter, collector and base electrodes 33′, 34′, and 35 respectively contact the emitter region 13′, the collector connection 41, and the base region 15 a′ at windows in an insulating layer 40 on the body surface 10a. The thick upper insulating layer 22 separates the collector connection 41 from the base region 15 a.
  • All the trench sections shown in FIG. 1 accommodate the [0079] insulated trench gate 11 and have the lower insulating layer 21 at the bottom 20 b of the trench. However, the MOSFET device of FIG. 1 may comprise a network (or group) of trenches 20 that accommodate the gate 11, and one or more separate trenches 20′ that accommodate a source electrode 41′. This source electrode 41′ contacts the source region 13 at the un-insulated bottom 20b′ of the trench 20′, in a similar manner to the electrode 41 of FIG. 7.
  • From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalents and other features which are already known in the design, manufacture and use of semiconductor devices, and which may be used instead of or in addition to features already described herein. [0080]
  • Although Claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present invention. [0081]
  • The Applicants hereby give notice that new Claims may be formulated to any such features and/or combinations of such features during the prosecution of the present Application or of any further Application derived therefrom. [0082]

Claims (17)

1. A method of manufacturing a semiconductor device having an electrode provided in an insulated trench, trench walls of which are lined with a lower insulating layer in a lower part of the trench and with a thicker upper insulating layer in an upper part of the trench, wherein the insulated trench is formed by process steps that include:
(a) etching the trench into a semiconductor body from one surface of the body,
(b) providing the lower insulating layer on the trench walls,
(c) depositing on the lower insulating layer a further layer of a different material from that of the lower insulating layer,
(d) depositing on the further layer a filler material that is of a different material from the further layer,
(e) etching away the further layer from the upper part of the trench walls while using the filler material as an etchant mask, so as to form a space adjacent to the upper part of the trench walls while leaving the further layer in the lower part of the trench,
and (f) providing the thicker upper insulating layer in the space adjacent to the upper part of the trench walls.
2. A method as claimed in
claim 1
, wherein the filler material extends in both the lower and upper parts of the trench so that the space formed in step (e) is present between an upper part of the filler material and the upper part of the trench walls, and the thicker upper insulating layer is formed by depositing insulating material in the space between the filler material and the upper part of the trench walls.
3. A method as claimed in
claim 2
, wherein which the filler material comprises silicon nitride, and silicon dioxide is deposited to provide the thicker upper insulating layer, after which a selective etchant is used to etch away the filler material from the upper insulating layer of silicon dioxide.
4. A method as claimed in
claim 1
, wherein the deposited filler material is etched back so as to be left in only the lower part of the trench so that the space formed in step (e) extends across the upper part of the trench, and the thicker upper insulating layer is formed by depositing insulating material in the upper part of the trench and etching back the deposited insulated material with a directional etch so as to be left as spacers on the upper part of the trench walls.
5. A method as claimed in
claim 1
, wherein the semiconductor body is of silicon, the filler material comprises oxidation-resistant material, and the upper part of the trench walls are oxidised to form the thicker upper insulating layer of silicon dioxide while using the filler material as an oxidation mask in the lower part of the trench.
6. A method as claimed in
claim 5
, wherein the filler material comprises silicon nitride that is etched away from the upper insulating layer of silicon dioxide with a selective etchant after forming the upper insulating layer by oxidation.
7. A method as claimed in
claim 2
 or
claim 4
 or
claim 5
, wherein the filler material comprises an electrode material that is retained in the manufactured device as a part of the electrode in the trench.
8. A method as claimed in
claim 7
, wherein the filler material comprises a mixed germanium-silicon alloy as its electrode material.
9. A method as claimed in any one of the preceding Claims, wherein the further layer comprises an electrode material that is retained in the manufactured device as a lower part of the electrode in the trench.
10. A method as claimed in
claim 9
, wherein the further layer comprises doped polycrystalline silicon as its electrode material.
11. A method as claimed in
claim 1
, wherein the semiconductor body is of silicon, the further layer comprises oxidation-resistant material, and the upper part of the trench walls are oxidised to form the thicker upper insulating layer while using the further layer as an oxidation mask in the lower part of the trench.
12. A method as claimed in
claim 11
, wherein the filler material is removed before oxidising the upper part of the trench walls to form the thicker upper insulating layer, and electrode material is deposited in at least the upper part of the trench after the oxidation.
13. A method as claimed in any one of claims 4 or 1 1 or 12, wherein the further layer is etched away from the lower part of the trench after forming the thicker upper insulating layer by oxidation, and thereafter electrode material is deposited to provide the electrode in the insulated trench.
14. A method as claimed in any one of claims 4 or 11 or 12, wherein the further layer is of electrode material that is retained in the manufactured device as a lower part of the electrode in the insulated trench.
15. A method as claimed in any one of claims 4 or 11 or 12, wherein the further layer is of silicon nitride that is retained in the manufactured device adjacent to the lower insulating layer.
16. A method as claimed in any one of the preceding Claims, wherein the electrode is a trench-gate of a field-effect device having a channel-accommodating region in the body, the trench is etched into the channel-accommodating region, the lower insulating layer is provided on the bottom of the trench as well as on the lower part of its side walls, and source and/or drain regions are formed in the body adjacent to the thicker upper insulating layer.
17. A method as claimed in
claim 16
, wherein the field-effect device is an inverted transistor having drain regions adjacent to the thicker upper insulating layer, and the trench extends through the thickness of the channel-accommodating region to reach an underlying source region adjacent to the lower insulating layer.
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030068863A1 (en) * 2001-10-04 2003-04-10 Blanchard Richard A. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6566201B1 (en) 2001-12-31 2003-05-20 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6576516B1 (en) 2001-12-31 2003-06-10 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
US20030122189A1 (en) * 2001-12-31 2003-07-03 Blanchard Richard A. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
US6649477B2 (en) * 2001-10-04 2003-11-18 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US6656797B2 (en) 2001-12-31 2003-12-02 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation
US6686244B2 (en) 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US20070259498A1 (en) * 2006-05-05 2007-11-08 San-Jung Chang Method of fabricating metal-oxide-semiconductor transistor
US20080142880A1 (en) * 2001-10-04 2008-06-19 Vishay General Semiconductor Llc Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
DE112005003584B4 (en) * 2005-05-24 2011-06-16 Vishay-Siliconix, Santa Clara A method of fabricating a trench metal oxide semiconductor field effect transistor
US20150084117A1 (en) * 2009-06-17 2015-03-26 Madhur Bobde Bottom source nmos triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (tvs)
US20150243561A1 (en) * 2014-02-24 2015-08-27 Infineon Technologies Ag Semiconductor Devices and Methods of Formation Thereof
US20230197771A1 (en) * 2021-12-16 2023-06-22 Nanya Technology Corporation Memory device having word lines with reduced leakage

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6635534B2 (en) * 2000-06-05 2003-10-21 Fairchild Semiconductor Corporation Method of manufacturing a trench MOSFET using selective growth epitaxy
US6583479B1 (en) * 2000-10-16 2003-06-24 Advanced Micro Devices, Inc. Sidewall NROM and method of manufacture thereof for non-volatile memory cells
US6674124B2 (en) * 2001-11-15 2004-01-06 General Semiconductor, Inc. Trench MOSFET having low gate charge
ITVA20020005A1 (en) * 2002-01-25 2003-07-25 St Microelectronics Srl PROCESS FLOW FOR THE CREATION OF A MOS TRANSITOR OF POWER TO TRENCH OF GATE WITH CHANNEL OF SCALED DIMENSIONS
WO2003078153A2 (en) * 2002-03-14 2003-09-25 General Dynamics Advanced Information Systems, Inc. Lamination of high-layer-count substrates
DE10219329B4 (en) * 2002-04-30 2014-01-23 Infineon Technologies Ag Semiconductor circuitry
KR100521369B1 (en) * 2002-12-18 2005-10-12 삼성전자주식회사 High speed and low power consumption semiconductor device and method for fabricating the same
US7279743B2 (en) 2003-12-02 2007-10-09 Vishay-Siliconix Closed cell trench metal-oxide-semiconductor field effect transistor
US8183629B2 (en) * 2004-05-13 2012-05-22 Vishay-Siliconix Stacked trench metal-oxide-semiconductor field effect transistor device
US6906380B1 (en) 2004-05-13 2005-06-14 Vishay-Siliconix Drain side gate trench metal-oxide-semiconductor field effect transistor
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US8471390B2 (en) 2006-05-12 2013-06-25 Vishay-Siliconix Power MOSFET contact metallization
US8368126B2 (en) * 2007-04-19 2013-02-05 Vishay-Siliconix Trench metal oxide semiconductor with recessed trench material and remote contacts
JP2009026809A (en) * 2007-07-17 2009-02-05 Toyota Motor Corp Semiconductor apparatus and manufacturing method thereof
JP5266738B2 (en) * 2007-12-05 2013-08-21 トヨタ自動車株式会社 Manufacturing method of trench gate type semiconductor device
KR100905789B1 (en) * 2008-01-02 2009-07-02 주식회사 하이닉스반도체 Method of manufacturing semiconductor device with vertical transistor
US9306056B2 (en) 2009-10-30 2016-04-05 Vishay-Siliconix Semiconductor device with trench-like feed-throughs
US8604525B2 (en) 2009-11-02 2013-12-10 Vishay-Siliconix Transistor structure with feed-through source-to-substrate contact
DE102010034116B3 (en) * 2010-08-12 2012-01-12 Infineon Technologies Austria Ag Method for producing an insulation layer between two electrodes
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US9559158B2 (en) 2015-01-12 2017-01-31 The Hong Kong University Of Science And Technology Method and apparatus for an integrated capacitor
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EP4290585A1 (en) 2022-06-08 2023-12-13 Nexperia B.V. Lateral oriented metal-oxide-semiconductor, mos device comprising a semiconductor body

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0294477A (en) * 1988-09-30 1990-04-05 Toshiba Corp Semiconductor device and manufacture thereof
US5242845A (en) * 1990-06-13 1993-09-07 Kabushiki Kaisha Toshiba Method of production of vertical MOS transistor
JP3008479B2 (en) * 1990-11-05 2000-02-14 日産自動車株式会社 Semiconductor device
US5345102A (en) * 1992-02-28 1994-09-06 Nec Corporation Bipolar transistor having collector electrode penetrating emitter and base regions
JP3338178B2 (en) * 1994-05-30 2002-10-28 株式会社東芝 Semiconductor device and method of manufacturing the same
KR0172262B1 (en) * 1995-12-30 1999-02-01 김주용 Method of fabricating semiconductor device
DE19638439C2 (en) * 1996-09-19 2000-06-15 Siemens Ag Vertical semiconductor device controllable by field effect and manufacturing process
EP1060518A1 (en) * 1998-02-20 2000-12-20 Infineon Technologies AG Trench-gate mos transistor, its use in an eeprom device and process for manufacturing the same

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8049271B2 (en) 2001-10-04 2011-11-01 Vishay General Semiconductor Llc Power semiconductor device having a voltage sustaining layer with a terraced trench formation of floating islands
US7304347B2 (en) 2001-10-04 2007-12-04 Vishay General Semiconductor Inc. Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US7736976B2 (en) 2001-10-04 2010-06-15 Vishay General Semiconductor Llc Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US20100207198A1 (en) * 2001-10-04 2010-08-19 Gs General Semiconductor Llc Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US20030068863A1 (en) * 2001-10-04 2003-04-10 Blanchard Richard A. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6649477B2 (en) * 2001-10-04 2003-11-18 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US20080142880A1 (en) * 2001-10-04 2008-06-19 Vishay General Semiconductor Llc Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
US20040110333A1 (en) * 2001-12-31 2004-06-10 Blanchard Richard A. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation
US20050042830A1 (en) * 2001-12-31 2005-02-24 Blanchard Richard A. High voltage power MOSFET having a voltage sustaining region that includes Doped Columns Formed by trench etching and diffusion from regions of oppositely doped polysilicon
US6710400B2 (en) * 2001-12-31 2004-03-23 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6656797B2 (en) 2001-12-31 2003-12-02 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation
US6750104B2 (en) 2001-12-31 2004-06-15 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
US20040164348A1 (en) * 2001-12-31 2004-08-26 Blanchard Richard A. High voltage power mosfet having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
US6794251B2 (en) 2001-12-31 2004-09-21 General Semiconductor, Inc. Method of making a power semiconductor device
US20040009643A1 (en) * 2001-12-31 2004-01-15 Blanchard Richard A. Method for fabricating a high voltage power mosfet having a voltage sustaining region that includes doped columns formed by rapid diffusion
US7019360B2 (en) 2001-12-31 2006-03-28 General Semiconductor, Inc. High voltage power mosfet having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
US20030203552A1 (en) * 2001-12-31 2003-10-30 Blanchard Richard A. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
US7091552B2 (en) 2001-12-31 2006-08-15 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation
US20030122189A1 (en) * 2001-12-31 2003-07-03 Blanchard Richard A. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
US7224027B2 (en) 2001-12-31 2007-05-29 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
US6576516B1 (en) 2001-12-31 2003-06-10 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
US6566201B1 (en) 2001-12-31 2003-05-20 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US7084455B2 (en) 2002-03-21 2006-08-01 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer
US7586148B2 (en) 2002-03-21 2009-09-08 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed by terraced trenches
US20060267083A1 (en) * 2002-03-21 2006-11-30 Blanchard Richard A Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US6686244B2 (en) 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
DE112005003584B4 (en) * 2005-05-24 2011-06-16 Vishay-Siliconix, Santa Clara A method of fabricating a trench metal oxide semiconductor field effect transistor
KR101047945B1 (en) * 2005-05-24 2011-07-12 비쉐이-실리코닉스 Trench Metal Oxide Semiconductor Field Effect Transistor
US7611949B2 (en) * 2006-05-05 2009-11-03 Promos Technologies, Inc. Method of fabricating metal-oxide-semiconductor transistor
US20070259498A1 (en) * 2006-05-05 2007-11-08 San-Jung Chang Method of fabricating metal-oxide-semiconductor transistor
US20150084117A1 (en) * 2009-06-17 2015-03-26 Madhur Bobde Bottom source nmos triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (tvs)
US10205017B2 (en) * 2009-06-17 2019-02-12 Alpha And Omega Semiconductor Incorporated Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)
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US6319777B1 (en) 2001-11-20
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