|Número de publicación||US20010049186 A1|
|Tipo de publicación||Solicitud|
|Número de solicitud||US 09/479,506|
|Fecha de publicación||6 Dic 2001|
|Fecha de presentación||7 Ene 2000|
|Fecha de prioridad||7 Dic 1999|
|También publicado como||CN1423832A, EP1236225A1, US6444555, WO2001043177A1|
|Número de publicación||09479506, 479506, US 2001/0049186 A1, US 2001/049186 A1, US 20010049186 A1, US 20010049186A1, US 2001049186 A1, US 2001049186A1, US-A1-20010049186, US-A1-2001049186, US2001/0049186A1, US2001/049186A1, US20010049186 A1, US20010049186A1, US2001049186 A1, US2001049186A1|
|Cesionario original||Effiong Ibok|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citada por (10), Clasificaciones (14), Eventos legales (5)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
 This application claims the benefit of U.S. Provisional Application No. 60/169,540, filed on Dec. 7, 1999 and entitled “METHOD FOR ESTABLISHING ULTRA-THIN GATE INSULATOR USING ANNEAL IN AMMONIA”.
 The present invention relates to the fabrication of semiconductor devices, and more particularly to establishing field effect transistor (FET) gate insulators.
 Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
 It can readily be appreciated that it is important to electrically isolate various components of an integrated circuit from each other, to ensure proper circuit operation. As one example, in a transistor, a gate is formed on a semiconductor substrate, with the gate being insulated from the substrate by a very thin dielectric layer, referred to as the “gate oxide” or “gate insulator”. As the scale of semiconductor devices decreases, the thickness of the gate insulator layer likewise decreases.
 As recognized herein, at very small scales, the gate insulator can be become so thin that otherwise relatively small encroachments into the gate insulator layer by sub-oxides from the substrate and from adjacent polysilicon connector electrodes can reduce the insulating ability of the gate insulator layer. This poses severe problems because under these circumstances, even very minor defects in the substrate can create electron leakage paths through the gate insulator, leading to catastrophic failure of the transistor.
 To circumvent this problem, alternatives to traditional gate oxide materials, such as high-k dielectric materials including nitrides and oxynitrides that can be made very thin and still retain good insulating properties, have been proposed. Unfortunately, it is thought that these materials can degrade the performance of the transistor. Nitride, in particular, has been considered undesirable because it promotes unwanted leakage of electrons through the gate insulator layer.
 Furthermore, as the gate insulator layer becomes very thin, e.g., on the order of nineteen Angstroms (19 Å), device integration becomes highly complicated. Specifically, it is necessary to etch portions of the polysilicon electrodes down to the substrate, but stopping the etch on a very thin, e.g., 19 Å gate insulator layer without pitting the substrate underneath becomes problematic. Accordingly, the present invention recognizes that it is desirable to provide a gate insulator layer that can be made very thin as appropriate for very small-scale transistors while retaining sufficient electrical insulation properties to adequately function as a gate insulator, and while retaining sufficient physical thickness to facilitate device integration, without degrading performance vis-a-vis oxide insulators.
 A method for making a semiconductor device includes providing a semiconductor substrate, and establishing an oxide base film on the substrate. The substrate is annealed, preferably in ammonia at temperatures up to eleven hundred degrees Celsius (1100° C.), after which FET gates are formed on portions of the film. The preferred base film defines a thickness of no more than twenty four Angstroms (24 Å). However, after annealing the electrical resistance of the base film is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of the film is advantageously reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
 Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
 For understanding of the present invention, reference is made to the accompanying drawing in the following DETAILED DESCRIPTION OF THE INVENTION. In the drawings:
FIG. 1 is a flow chart of the manufacturing process;
FIG. 2 is a side view of the device after forming the base film on the substrate;
FIG. 3 is a side view of the device after annealing the base film; and
FIG. 4 is a side view of the device after forming the FET gate stacks on the nitride film.
 The principles of the present invention are equally applicable to a wide range of semiconductor and integrated circuit design and manufacture regimens, including but not necessarily limited to the production of non-volatile memory devices. All such implementations are specifically contemplated by the principles of the present intention.
 Referring initially to FIGS. 1 and 2, at block 10 in FIG. 1 a semiconductor substrate 12 (FIG. 2) such as Silicon is provided, and then at block 14 a thin Oxide base film 16 is grown on the substrate 12 in accordance with oxide film formation principles known in the art, in direct contact with the substrate 12. The thickness “t” of the base film 16 is no more than twenty four Angstroms (24 Å).
 Moving to block 18 of FIG. 1 and referring to FIG. 3, the substrate 12 with film 16 is annealed in situ in ammonia (NH3) at a temperature of up to eleven hundred degrees Celsius (1100° C.) to establish a Nitrogen concentration in the base film 16. The Nitrogen is represented by the dots 19. In accordance with present principles, after annealing the electrical resistance of the base film 16 is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of the film 16 advantageously is reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
 Next, at block 20 in FIG. 2 and referring now to FIG. 4, a polysilicon-based field effect transistor (FET) stack 28 is formed on the film 16 in accordance with FET gate stack deposition and patterning principles known in the art. After forming and patterning the FET stacks 28, the process is completed by forming FET sources and drains 36, 38 using conventional principles, and contacts, interconnects, and FET to FET insulation are likewise conventionally undertaken.
 With the above disclosure in mind, the ammonia anneal of the base film reduces the equivalent electrical thickness of the base film. In other words, for a film that is sufficiently thick for the above-mentioned structural considerations, e.g., 24 Å thick, after annealing the film advantageously behaves electrically like a film that is only 20 Å thick. This in turn advantageously decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia.
 The present invention has been particularly shown and described with respect to certain preferred embodiments of features thereof. However, it should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims. In particular, the use of: alternate layer deposition or forming methodologies; etching technologies; masking methods; lithographic methods, passivation and nitridization techniques; as well as alternative semiconductor designs, as well as the application of the technology disclosed herein to alternate electronic components are all contemplated by the principles of the present invention. The invention disclosed herein may be practiced without any element which is not specifically disclosed herein. The use of the singular in the claims does not mean “only one”, but rather “one or more”, unless otherwise stated in the claims.
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
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|US7638396||20 Mar 2007||29 Dic 2009||Taiwan Semiconductor Manufacturing Co., Ltd.||Methods for fabricating a semiconductor device|
|US7645710||8 Mar 2007||12 Ene 2010||Applied Materials, Inc.||Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system|
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|US7902018||26 Sep 2007||8 Mar 2011||Applied Materials, Inc.||Fluorine plasma treatment of high-k gate stack for defect passivation|
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|Clasificación de EE.UU.||438/591, 257/E21.209|
|Clasificación internacional||H01L21/28, H01L29/51, H01L29/78, H01L21/318|
|Clasificación cooperativa||H01L29/518, H01L21/28202, H01L21/28273, H01L21/28185|
|Clasificación europea||H01L21/28F, H01L21/28E2C2C, H01L29/51N, H01L21/28E2C2N|
|7 Ene 2000||AS||Assignment|
|28 Feb 2006||FPAY||Fee payment|
Year of fee payment: 4
|18 Ago 2009||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC.,CAYMAN ISLANDS
Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023120/0426
Effective date: 20090630
|19 Feb 2010||FPAY||Fee payment|
Year of fee payment: 8
|6 Feb 2014||FPAY||Fee payment|
Year of fee payment: 12