US20010049186A1 - Method for establishing ultra-thin gate insulator using anneal in ammonia - Google Patents
Method for establishing ultra-thin gate insulator using anneal in ammonia Download PDFInfo
- Publication number
- US20010049186A1 US20010049186A1 US09/479,506 US47950600A US2001049186A1 US 20010049186 A1 US20010049186 A1 US 20010049186A1 US 47950600 A US47950600 A US 47950600A US 2001049186 A1 US2001049186 A1 US 2001049186A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- ammonia
- base film
- film
- gate insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims abstract description 15
- 229910021529 ammonia Inorganic materials 0.000 title claims abstract description 9
- 239000012212 insulator Substances 0.000 title abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 230000007423 decrease Effects 0.000 claims description 4
- 230000005641 tunneling Effects 0.000 claims description 4
- 230000000593 degrading effect Effects 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Definitions
- the present invention relates to the fabrication of semiconductor devices, and more particularly to establishing field effect transistor (FET) gate insulators.
- FET field effect transistor
- Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
- a gate is formed on a semiconductor substrate, with the gate being insulated from the substrate by a very thin dielectric layer, referred to as the “gate oxide” or “gate insulator”. As the scale of semiconductor devices decreases, the thickness of the gate insulator layer likewise decreases.
- the gate insulator can be become so thin that otherwise relatively small encroachments into the gate insulator layer by sub-oxides from the substrate and from adjacent polysilicon connector electrodes can reduce the insulating ability of the gate insulator layer. This poses severe problems because under these circumstances, even very minor defects in the substrate can create electron leakage paths through the gate insulator, leading to catastrophic failure of the transistor.
- the present invention recognizes that it is desirable to provide a gate insulator layer that can be made very thin as appropriate for very small-scale transistors while retaining sufficient electrical insulation properties to adequately function as a gate insulator, and while retaining sufficient physical thickness to facilitate device integration, without degrading performance vis-a-vis oxide insulators.
- a method for making a semiconductor device includes providing a semiconductor substrate, and establishing an oxide base film on the substrate.
- the substrate is annealed, preferably in ammonia at temperatures up to eleven hundred degrees Celsius (1100° C.), after which FET gates are formed on portions of the film.
- the preferred base film defines a thickness of no more than twenty four Angstroms (24 ⁇ ).
- the electrical resistance of the base film is reduced to that of a conventional oxide film having a thickness of only 20 ⁇ , such that the electrical resistance of the film is advantageously reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
- FIG. 1 is a flow chart of the manufacturing process
- FIG. 2 is a side view of the device after forming the base film on the substrate
- FIG. 3 is a side view of the device after annealing the base film.
- FIG. 4 is a side view of the device after forming the FET gate stacks on the nitride film.
- a semiconductor substrate 12 such as Silicon is provided, and then at block 14 a thin Oxide base film 16 is grown on the substrate 12 in accordance with oxide film formation principles known in the art, in direct contact with the substrate 12 .
- the thickness “t” of the base film 16 is no more than twenty four Angstroms (24 ⁇ ).
- the substrate 12 with film 16 is annealed in situ in ammonia (NH 3 ) at a temperature of up to eleven hundred degrees Celsius (1100° C.) to establish a Nitrogen concentration in the base film 16 .
- the Nitrogen is represented by the dots 19 .
- the electrical resistance of the base film 16 is reduced to that of a conventional oxide film having a thickness of only 20 ⁇ , such that the electrical resistance of the film 16 advantageously is reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
- a polysilicon-based field effect transistor (FET) stack 28 is formed on the film 16 in accordance with FET gate stack deposition and patterning principles known in the art. After forming and patterning the FET stacks 28 , the process is completed by forming FET sources and drains 36 , 38 using conventional principles, and contacts, interconnects, and FET to FET insulation are likewise conventionally undertaken.
- FET field effect transistor
- the ammonia anneal of the base film reduces the equivalent electrical thickness of the base film.
- the film advantageously behaves electrically like a film that is only 20 ⁇ thick. This in turn advantageously decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia.
Abstract
Description
- This application claims the benefit of U.S. Provisional Application No. 60/169,540, filed on Dec. 7, 1999 and entitled “METHOD FOR ESTABLISHING ULTRA-THIN GATE INSULATOR USING ANNEAL IN AMMONIA”.
- The present invention relates to the fabrication of semiconductor devices, and more particularly to establishing field effect transistor (FET) gate insulators.
- Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
- It can readily be appreciated that it is important to electrically isolate various components of an integrated circuit from each other, to ensure proper circuit operation. As one example, in a transistor, a gate is formed on a semiconductor substrate, with the gate being insulated from the substrate by a very thin dielectric layer, referred to as the “gate oxide” or “gate insulator”. As the scale of semiconductor devices decreases, the thickness of the gate insulator layer likewise decreases.
- As recognized herein, at very small scales, the gate insulator can be become so thin that otherwise relatively small encroachments into the gate insulator layer by sub-oxides from the substrate and from adjacent polysilicon connector electrodes can reduce the insulating ability of the gate insulator layer. This poses severe problems because under these circumstances, even very minor defects in the substrate can create electron leakage paths through the gate insulator, leading to catastrophic failure of the transistor.
- To circumvent this problem, alternatives to traditional gate oxide materials, such as high-k dielectric materials including nitrides and oxynitrides that can be made very thin and still retain good insulating properties, have been proposed. Unfortunately, it is thought that these materials can degrade the performance of the transistor. Nitride, in particular, has been considered undesirable because it promotes unwanted leakage of electrons through the gate insulator layer.
- Furthermore, as the gate insulator layer becomes very thin, e.g., on the order of nineteen Angstroms (19 Å), device integration becomes highly complicated. Specifically, it is necessary to etch portions of the polysilicon electrodes down to the substrate, but stopping the etch on a very thin, e.g., 19 Å gate insulator layer without pitting the substrate underneath becomes problematic. Accordingly, the present invention recognizes that it is desirable to provide a gate insulator layer that can be made very thin as appropriate for very small-scale transistors while retaining sufficient electrical insulation properties to adequately function as a gate insulator, and while retaining sufficient physical thickness to facilitate device integration, without degrading performance vis-a-vis oxide insulators.
- A method for making a semiconductor device includes providing a semiconductor substrate, and establishing an oxide base film on the substrate. The substrate is annealed, preferably in ammonia at temperatures up to eleven hundred degrees Celsius (1100° C.), after which FET gates are formed on portions of the film. The preferred base film defines a thickness of no more than twenty four Angstroms (24 Å). However, after annealing the electrical resistance of the base film is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of the film is advantageously reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
- Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
- For understanding of the present invention, reference is made to the accompanying drawing in the following DETAILED DESCRIPTION OF THE INVENTION. In the drawings:
- FIG. 1 is a flow chart of the manufacturing process;
- FIG. 2 is a side view of the device after forming the base film on the substrate;
- FIG. 3 is a side view of the device after annealing the base film; and
- FIG. 4 is a side view of the device after forming the FET gate stacks on the nitride film.
- The principles of the present invention are equally applicable to a wide range of semiconductor and integrated circuit design and manufacture regimens, including but not necessarily limited to the production of non-volatile memory devices. All such implementations are specifically contemplated by the principles of the present intention.
- Referring initially to FIGS. 1 and 2, at
block 10 in FIG. 1 a semiconductor substrate 12 (FIG. 2) such as Silicon is provided, and then at block 14 a thinOxide base film 16 is grown on thesubstrate 12 in accordance with oxide film formation principles known in the art, in direct contact with thesubstrate 12. The thickness “t” of thebase film 16 is no more than twenty four Angstroms (24 Å). - Moving to block18 of FIG. 1 and referring to FIG. 3, the
substrate 12 withfilm 16 is annealed in situ in ammonia (NH3) at a temperature of up to eleven hundred degrees Celsius (1100° C.) to establish a Nitrogen concentration in thebase film 16. The Nitrogen is represented by the dots 19. In accordance with present principles, after annealing the electrical resistance of thebase film 16 is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of thefilm 16 advantageously is reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance. - Next, at
block 20 in FIG. 2 and referring now to FIG. 4, a polysilicon-based field effect transistor (FET)stack 28 is formed on thefilm 16 in accordance with FET gate stack deposition and patterning principles known in the art. After forming and patterning the FET stacks 28, the process is completed by forming FET sources and drains 36, 38 using conventional principles, and contacts, interconnects, and FET to FET insulation are likewise conventionally undertaken. - With the above disclosure in mind, the ammonia anneal of the base film reduces the equivalent electrical thickness of the base film. In other words, for a film that is sufficiently thick for the above-mentioned structural considerations, e.g., 24 Å thick, after annealing the film advantageously behaves electrically like a film that is only 20 Å thick. This in turn advantageously decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia.
- The present invention has been particularly shown and described with respect to certain preferred embodiments of features thereof. However, it should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims. In particular, the use of: alternate layer deposition or forming methodologies; etching technologies; masking methods; lithographic methods, passivation and nitridization techniques; as well as alternative semiconductor designs, as well as the application of the technology disclosed herein to alternate electronic components are all contemplated by the principles of the present invention. The invention disclosed herein may be practiced without any element which is not specifically disclosed herein. The use of the singular in the claims does not mean “only one”, but rather “one or more”, unless otherwise stated in the claims.
Claims (6)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/479,506 US6444555B2 (en) | 1999-12-07 | 2000-01-07 | Method for establishing ultra-thin gate insulator using anneal in ammonia |
TW089125288A TW556273B (en) | 1999-12-07 | 2000-11-29 | Method for establishing ultra-thin gate insulator using anneal in ammonia |
KR1020027007313A KR100702694B1 (en) | 1999-12-07 | 2000-12-05 | A method for making a semiconductor device having an ultra-thin insulator for inhibiting tunneling effects |
CN00816802A CN1423832A (en) | 1999-12-07 | 2000-12-05 | Method for establishing ultra-thin gate insulator using anneal in ammonia |
JP2001543768A JP2003516633A (en) | 1999-12-07 | 2000-12-05 | A method for establishing ultra-thin gate insulators using annealing in ammonia |
EP00983955A EP1236225A1 (en) | 1999-12-07 | 2000-12-05 | Method for establishing ultra-thin gate insulator using anneal in ammonia |
PCT/US2000/033071 WO2001043177A1 (en) | 1999-12-07 | 2000-12-05 | Method for establishing ultra-thin gate insulator using anneal in ammonia |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16954099P | 1999-12-07 | 1999-12-07 | |
US09/479,506 US6444555B2 (en) | 1999-12-07 | 2000-01-07 | Method for establishing ultra-thin gate insulator using anneal in ammonia |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010049186A1 true US20010049186A1 (en) | 2001-12-06 |
US6444555B2 US6444555B2 (en) | 2002-09-03 |
Family
ID=26865152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/479,506 Expired - Lifetime US6444555B2 (en) | 1999-12-07 | 2000-01-07 | Method for establishing ultra-thin gate insulator using anneal in ammonia |
Country Status (7)
Country | Link |
---|---|
US (1) | US6444555B2 (en) |
EP (1) | EP1236225A1 (en) |
JP (1) | JP2003516633A (en) |
KR (1) | KR100702694B1 (en) |
CN (1) | CN1423832A (en) |
TW (1) | TW556273B (en) |
WO (1) | WO2001043177A1 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050130448A1 (en) * | 2003-12-15 | 2005-06-16 | Applied Materials, Inc. | Method of forming a silicon oxynitride layer |
US20060178018A1 (en) * | 2003-03-07 | 2006-08-10 | Applied Materials, Inc. | Silicon oxynitride gate dielectric formation using multiple annealing steps |
US20080230814A1 (en) * | 2007-03-20 | 2008-09-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for fabricating a semiconductor device |
US20090035928A1 (en) * | 2007-07-30 | 2009-02-05 | Hegde Rama I | Method of processing a high-k dielectric for cet scaling |
US7645710B2 (en) | 2006-03-09 | 2010-01-12 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
US7678710B2 (en) | 2006-03-09 | 2010-03-16 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
US7837838B2 (en) | 2006-03-09 | 2010-11-23 | Applied Materials, Inc. | Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus |
US7902018B2 (en) | 2006-09-26 | 2011-03-08 | Applied Materials, Inc. | Fluorine plasma treatment of high-k gate stack for defect passivation |
US7964514B2 (en) | 2006-03-02 | 2011-06-21 | Applied Materials, Inc. | Multiple nitrogen plasma treatments for thin SiON dielectrics |
US8119210B2 (en) | 2004-05-21 | 2012-02-21 | Applied Materials, Inc. | Formation of a silicon oxynitride layer on a high-k dielectric material |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AUPO864097A0 (en) * | 1997-08-19 | 1997-09-11 | Peplin Pty Ltd | Anti-cancer compounds |
US7138691B2 (en) * | 2004-01-22 | 2006-11-21 | International Business Machines Corporation | Selective nitridation of gate oxides |
US6921691B1 (en) * | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
US8178902B2 (en) * | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
US7592678B2 (en) * | 2004-06-17 | 2009-09-22 | Infineon Technologies Ag | CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof |
US7344934B2 (en) | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
US7381608B2 (en) * | 2004-12-07 | 2008-06-03 | Intel Corporation | Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode |
US7253050B2 (en) * | 2004-12-20 | 2007-08-07 | Infineon Technologies Ag | Transistor device and method of manufacture thereof |
US7160781B2 (en) * | 2005-03-21 | 2007-01-09 | Infineon Technologies Ag | Transistor device and methods of manufacture thereof |
US7361538B2 (en) * | 2005-04-14 | 2008-04-22 | Infineon Technologies Ag | Transistors and methods of manufacture thereof |
US8188551B2 (en) | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20070052036A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Transistors and methods of manufacture thereof |
US20070052037A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
US7462538B2 (en) * | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
US7495290B2 (en) * | 2005-12-14 | 2009-02-24 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US7510943B2 (en) * | 2005-12-16 | 2009-03-31 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
JP5104373B2 (en) * | 2008-02-14 | 2012-12-19 | 日本ゼオン株式会社 | Production method of retardation plate |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4490900A (en) | 1982-01-29 | 1985-01-01 | Seeq Technology, Inc. | Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein |
US5874766A (en) | 1988-12-20 | 1999-02-23 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having an oxynitride film |
US5017979A (en) | 1989-04-28 | 1991-05-21 | Nippondenso Co., Ltd. | EEPROM semiconductor memory device |
US5219773A (en) | 1990-06-26 | 1993-06-15 | Massachusetts Institute Of Technology | Method of making reoxidized nitrided oxide MOSFETs |
US5254489A (en) | 1990-10-18 | 1993-10-19 | Nec Corporation | Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation |
JPH07335641A (en) | 1994-06-03 | 1995-12-22 | Sony Corp | Forming method of silicon oxide film and oxide film of semiconductor device |
US5891809A (en) * | 1995-09-29 | 1999-04-06 | Intel Corporation | Manufacturable dielectric formed using multiple oxidation and anneal steps |
EP0847079A3 (en) | 1996-12-05 | 1999-11-03 | Texas Instruments Incorporated | Method of manufacturing an MIS electrode |
US5908313A (en) * | 1996-12-31 | 1999-06-01 | Intel Corporation | Method of forming a transistor |
US6048769A (en) * | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
US6133093A (en) * | 1998-01-30 | 2000-10-17 | Motorola, Inc. | Method for forming an integrated circuit |
US6124171A (en) * | 1998-09-24 | 2000-09-26 | Intel Corporation | Method of forming gate oxide having dual thickness by oxidation process |
-
2000
- 2000-01-07 US US09/479,506 patent/US6444555B2/en not_active Expired - Lifetime
- 2000-11-29 TW TW089125288A patent/TW556273B/en not_active IP Right Cessation
- 2000-12-05 JP JP2001543768A patent/JP2003516633A/en not_active Withdrawn
- 2000-12-05 KR KR1020027007313A patent/KR100702694B1/en not_active IP Right Cessation
- 2000-12-05 CN CN00816802A patent/CN1423832A/en active Pending
- 2000-12-05 EP EP00983955A patent/EP1236225A1/en not_active Withdrawn
- 2000-12-05 WO PCT/US2000/033071 patent/WO2001043177A1/en not_active Application Discontinuation
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060178018A1 (en) * | 2003-03-07 | 2006-08-10 | Applied Materials, Inc. | Silicon oxynitride gate dielectric formation using multiple annealing steps |
US7429540B2 (en) | 2003-03-07 | 2008-09-30 | Applied Materials, Inc. | Silicon oxynitride gate dielectric formation using multiple annealing steps |
US7569502B2 (en) * | 2003-12-15 | 2009-08-04 | Applied Materials, Inc. | Method of forming a silicon oxynitride layer |
WO2005062345A3 (en) * | 2003-12-15 | 2005-11-24 | Applied Materials Inc | A method of forming a silicon oxynitride layer |
US20070087583A1 (en) * | 2003-12-15 | 2007-04-19 | Applied Materials, Inc. | Method of forming a silicon oxynitride layer |
WO2005062345A2 (en) * | 2003-12-15 | 2005-07-07 | Applied Materials, Inc. | A method of forming a silicon oxynitride layer |
US20050130448A1 (en) * | 2003-12-15 | 2005-06-16 | Applied Materials, Inc. | Method of forming a silicon oxynitride layer |
US8119210B2 (en) | 2004-05-21 | 2012-02-21 | Applied Materials, Inc. | Formation of a silicon oxynitride layer on a high-k dielectric material |
US7964514B2 (en) | 2006-03-02 | 2011-06-21 | Applied Materials, Inc. | Multiple nitrogen plasma treatments for thin SiON dielectrics |
US7837838B2 (en) | 2006-03-09 | 2010-11-23 | Applied Materials, Inc. | Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus |
US7645710B2 (en) | 2006-03-09 | 2010-01-12 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
US7678710B2 (en) | 2006-03-09 | 2010-03-16 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
US7902018B2 (en) | 2006-09-26 | 2011-03-08 | Applied Materials, Inc. | Fluorine plasma treatment of high-k gate stack for defect passivation |
US7638396B2 (en) | 2007-03-20 | 2009-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for fabricating a semiconductor device |
US20080230814A1 (en) * | 2007-03-20 | 2008-09-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for fabricating a semiconductor device |
US20090035928A1 (en) * | 2007-07-30 | 2009-02-05 | Hegde Rama I | Method of processing a high-k dielectric for cet scaling |
Also Published As
Publication number | Publication date |
---|---|
KR20020059447A (en) | 2002-07-12 |
KR100702694B1 (en) | 2007-04-04 |
EP1236225A1 (en) | 2002-09-04 |
WO2001043177A1 (en) | 2001-06-14 |
TW556273B (en) | 2003-10-01 |
CN1423832A (en) | 2003-06-11 |
JP2003516633A (en) | 2003-05-13 |
US6444555B2 (en) | 2002-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6444555B2 (en) | Method for establishing ultra-thin gate insulator using anneal in ammonia | |
US6171900B1 (en) | CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET | |
US6906398B2 (en) | Semiconductor chip with gate dielectrics for high-performance and low-leakage applications | |
US20070212829A1 (en) | Method of manufacturing a semiconductor device | |
US6849513B2 (en) | Semiconductor device and production method thereof | |
US7507632B2 (en) | Semiconductor device and manufacturing method thereof | |
US6261934B1 (en) | Dry etch process for small-geometry metal gates over thin gate dielectric | |
US7985670B2 (en) | Method of forming U-shaped floating gate with a poly meta-stable polysilicon layer | |
US6090671A (en) | Reduction of gate-induced drain leakage in semiconductor devices | |
US6207542B1 (en) | Method for establishing ultra-thin gate insulator using oxidized nitride film | |
US20030017670A1 (en) | Method of manufacturing a semiconductor memory device with a gate dielectric stack | |
KR20060108653A (en) | Method for integrating a high-k gate dielectric in a transistor fabrication process | |
US20060292784A1 (en) | Methods of Forming Integrated Circuit Devices Including Memory Cell Gates and High Voltage Transistor Gates Using Plasma Re-Oxidation | |
US20190259848A1 (en) | Semiconductor device and fabrication method thereof | |
US6399519B1 (en) | Method for establishing ultra-thin gate insulator having annealed oxide and oxidized nitride | |
US6429109B1 (en) | Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate | |
KR100655441B1 (en) | Method of fabricating trap-type nonvolatile memory device | |
KR100543209B1 (en) | Method for fabrication of transistor having sonos structure | |
US20180286878A1 (en) | Electronic chip manufacturing method | |
KR20060101347A (en) | Semiconductor device with gate insulation layer and manufacturing method therof | |
KR20040059931A (en) | Method for fabricating dual gate oxide of semiconductor device | |
KR100541799B1 (en) | Capacitor Manufacturing Method for Semiconductor Devices | |
KR100586540B1 (en) | Method of forming capacitor of semiconductor device | |
KR100840640B1 (en) | Manufacturing Method of Semiconductor Device | |
KR20040028244A (en) | Fabricating method of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADVANCED MICRO DEVICES, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IBOK, EFFIONG;REEL/FRAME:010535/0987 Effective date: 19991207 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023119/0083 Effective date: 20090630 Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023120/0426 Effective date: 20090630 Owner name: GLOBALFOUNDRIES INC.,CAYMAN ISLANDS Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023120/0426 Effective date: 20090630 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |