US20010051433A1 - Use of csoh in a dielectric cmp slurry - Google Patents
Use of csoh in a dielectric cmp slurry Download PDFInfo
- Publication number
- US20010051433A1 US20010051433A1 US09/428,965 US42896599A US2001051433A1 US 20010051433 A1 US20010051433 A1 US 20010051433A1 US 42896599 A US42896599 A US 42896599A US 2001051433 A1 US2001051433 A1 US 2001051433A1
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- US
- United States
- Prior art keywords
- polishing composition
- chemical mechanical
- abrasive
- polishing
- mechanical polishing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002002 slurry Substances 0.000 title description 57
- 238000005498 polishing Methods 0.000 claims abstract description 150
- 239000000203 mixture Substances 0.000 claims abstract description 99
- HUCVOHYBFXVBRW-UHFFFAOYSA-M caesium hydroxide Inorganic materials [OH-].[Cs+] HUCVOHYBFXVBRW-UHFFFAOYSA-M 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000000126 substance Substances 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 21
- 229910021485 fumed silica Inorganic materials 0.000 claims description 16
- 150000001447 alkali salts Chemical class 0.000 claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims description 12
- 150000004706 metal oxides Chemical class 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000008119 colloidal silica Substances 0.000 claims description 5
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- MFGOFGRYDNHJTA-UHFFFAOYSA-N 2-amino-1-(2-fluorophenyl)ethanol Chemical compound NCC(O)C1=CC=CC=C1F MFGOFGRYDNHJTA-UHFFFAOYSA-N 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 47
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- 235000012431 wafers Nutrition 0.000 description 24
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- 230000007547 defect Effects 0.000 description 11
- 229910021529 ammonia Inorganic materials 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 8
- 239000003082 abrasive agent Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
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- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 238000007517 polishing process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 5
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical class [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000012876 topography Methods 0.000 description 5
- -1 Cesium ions Chemical class 0.000 description 4
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 229910052792 caesium Inorganic materials 0.000 description 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 3
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004615 ingredient Substances 0.000 description 3
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- 238000000206 photolithography Methods 0.000 description 3
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- 238000012360 testing method Methods 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- XJHCXCQVJFPJIK-UHFFFAOYSA-M caesium fluoride Chemical compound [F-].[Cs+] XJHCXCQVJFPJIK-UHFFFAOYSA-M 0.000 description 2
- NCMHKCKGHRPLCM-UHFFFAOYSA-N caesium(1+) Chemical compound [Cs+] NCMHKCKGHRPLCM-UHFFFAOYSA-N 0.000 description 2
- 159000000006 cesium salts Chemical class 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 229920000126 latex Polymers 0.000 description 2
- 239000004816 latex Substances 0.000 description 2
- 239000000395 magnesium oxide Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910001414 potassium ion Inorganic materials 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 229910017974 NH40H Inorganic materials 0.000 description 1
- 229920005830 Polyurethane Foam Polymers 0.000 description 1
- 229910007156 Si(OH)4 Inorganic materials 0.000 description 1
- 125000005210 alkyl ammonium group Chemical group 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- ZOAIGCHJWKDIPJ-UHFFFAOYSA-M caesium acetate Chemical compound [Cs+].CC([O-])=O ZOAIGCHJWKDIPJ-UHFFFAOYSA-M 0.000 description 1
- ZMCUDHNSHCRDBT-UHFFFAOYSA-M caesium bicarbonate Chemical class [Cs+].OC([O-])=O ZMCUDHNSHCRDBT-UHFFFAOYSA-M 0.000 description 1
- FJDQFPXHSGXQBY-UHFFFAOYSA-L caesium carbonate Chemical compound [Cs+].[Cs+].[O-]C([O-])=O FJDQFPXHSGXQBY-UHFFFAOYSA-L 0.000 description 1
- 229910000024 caesium carbonate Inorganic materials 0.000 description 1
- AIYUHDOJVYHVIT-UHFFFAOYSA-M caesium chloride Chemical compound [Cl-].[Cs+] AIYUHDOJVYHVIT-UHFFFAOYSA-M 0.000 description 1
- ATZQZZAXOPPAAQ-UHFFFAOYSA-M caesium formate Chemical compound [Cs+].[O-]C=O ATZQZZAXOPPAAQ-UHFFFAOYSA-M 0.000 description 1
- XQPRBTXUXXVTKB-UHFFFAOYSA-M caesium iodide Chemical compound [I-].[Cs+] XQPRBTXUXXVTKB-UHFFFAOYSA-M 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000008139 complexing agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
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- 230000001627 detrimental effect Effects 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 150000004679 hydroxides Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002356 laser light scattering Methods 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 235000005985 organic acids Nutrition 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 239000011496 polyurethane foam Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001698 pyrogenic effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K3/00—Materials not provided for elsewhere
- C09K3/14—Anti-slip materials; Abrasives
- C09K3/1454—Abrasive powders, suspensions and pastes for polishing
- C09K3/1463—Aqueous liquid suspensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Definitions
- This invention concerns chemical mechanical polishing compositions including an abrasive and cesium hydroxide. This invention also concerns methods for polishing dielectric layers associated with integrated circuits using cesium hydroxide containing polishing compositions.
- Integrated circuits are made up of millions of active devices formed in or on a silicon substrate.
- the active devices which are initially isolated from one another, are interconnected to form functional circuits and components.
- the devices are interconnected through the use of multilevel interconnections.
- Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third and subsequent level of metallization.
- Interlevel dielectrics ILDs
- ILDs Interlevel dielectrics
- SiO 2 doped and undoped silicon dioxide
- low-K dielectrics tantalum nitride are used to electrically isolate the different levels of metallization in a silicon substrate or well.
- metallized vias, metallized layer and interlevel dielectric layers are built-up to create an integrated circuit.
- the excess materials are removed and the substrate surfaces are planarized by using chemical mechanical polishing (CMP) techniques.
- CMP chemical mechanical polishing
- the substrate is placed in direct contact with a rotating polishing pad.
- a carrier applies pressure against the backside of the substrate.
- the pad and table are rotated while a downward force is maintained against the substrate back.
- An abrasive and chemically reactive solution is applied to the pad during polishing.
- the slurry initiates the polishing process by chemically reacting with the film being polished.
- the polishing process is facilitated by the rotational movement of the pad relative to the substrate as slurry is provided to the wafer/pad interface. Polishing is continued in this manner until the desired film on the insulator is removed.
- the polishing composition ingredients are an important factor in the success of the CMP step. By carefully selecting ingredients, the polishing composition can be tailored to provide effective polishing to the selected layer at desired polishing rates while minimizing surface imperfections, defects and corrosion and erosion of adjacent layers.
- dielectric layers typically including silicon dioxide are applied to the circuit. Once applied, the dielectric layer is generally non-planar and must be polished using a polishing composition to give a planar dielectric surface. It is important that the chosen polishing composition be capable of producing a planarized dielectric surface with few defects. Furthermore, it is important that the polishing composition chosen be capable of polishing the dielectric layer efficiently and repeatedly.
- ILD slurries are typically stabilized abrasive slurries including about 10-30 wt % abrasives.
- the stabilizing ion is typically potassium or ammonia where slurries typically have a pH greater than 8.
- the shortcomings of potassium slurries are ionic contamination from the potassium where the contaminating ions become mobile ions and will detrimentally impact device reliability by migrating to the gate area 20 and lowering the threshold voltage of the transistors.
- Ammonia slurries solve the mobile ion problem associated with potassium stabilized slurries.
- ammonia has a strong odor.
- ammonia slurries planarize less effectively, polish with a high level of defectivity and polish with low rates compared to potassium slurries.
- this invention is a chemical mechanical polishing composition
- a chemical mechanical polishing composition comprising fumed silica and from about 0.01 to about 5.0 wt % of at least one Cs+ basic salt.
- this invention is a chemical mechanical polishing composition
- a chemical mechanical polishing composition comprising water, from about 1 to about 50 wt % fumed silica, and from about 0.1 to about 2.0 wt % CsOH.
- the polishing composition planarizes a silicon containing substrate with an open field efficiency of at least 50% and with an array field efficiency of at least 85 %.
- this invention is a chemical mechanical polishing composition capable of polishing integrated circuits having gate widths less than about 0.25 microns comprising from about 1 to about 50 wt % of a metal oxide abrasive and from about 0.01 to about 5.0 wt % Cs+ basic salt.
- this invention is a method for planarizing an insulating layer with a polishing composition of this invention.
- the polishing is achieved by preparing a polishing composition comprising water and CsOH.
- the polishing composition is then applied to a surface of the substrate being planarized or to the polishing pad.
- the polishing pad is brought into contact with the surface of the silicon containing substrate layer being planarized, and the pad is moved in relation to the silicon containing substrate surface being planarized.
- An abrasive is used in conjunction with the polishing composition to facilitate polishing.
- the abrasive may be associated with the polishing pad or the abrasive may be added to the polishing composition to give a chemical mechanical polishing slurry before the slurry is applied to the substrate or to the polishing pad.
- FIG. 1 is a simplified side-cutaway view of a portion of a semiconductor wafer that suitable for planarizing using the compositions and methods of this invention
- FIG. 2 illustrates the wafer shown in FIG. 1 after polishing
- FIG. 3 is a simplified side-cutaway view of a portion of a semiconductor wafer suitable for shallow trench isolation planarization using the compositions and methods of this invention
- FIG. 4 is the wafer of FIG. 3 including defects that could result due to inefficient planarization
- FIG. 5 is a plot of polish time versus step height for CsOH (A & B), KOH, (C) and NH 4 OH (D) slurries tested according to the method described in Example 2.
- the term “polish time” in the plot refers to the time, in seconds, that the substrate is being polished.
- step height in the plot refers to the distance from the high points on the topography to the low points during the fabrication of integrated circuits. As devices are built a surface topography is produced and perpetuated through subsequent thin-film depositions. Step height is usually measured in Angstroms; and
- FIG. 6 is a plot of delta field versus step height for slurries tested according to the method of described in Example 2.
- the present invention relates to chemical mechanical polishing compositions including an abrasive and at least one Cs+ basic salt such as cesium hydroxide.
- This invention also concerns methods for polishing dielectric layers associated with integrated circuits using Cs+ 5 basic salt containing polishing compositions.
- Basic cesium salt stabilized slurries show an unexpected performance enhancement as compared to ammonia and potassium hydroxide stabilized slurries.
- Cesium ions have lower mobility than potassium and sodium ions.
- cesium ion containing polishing compositions polish at higher rates than ammonia slurries and do not have a foul odor like ammonia stabilizes slurries.
- cesium ion containing polishing compositions polish with lower defectivity as measured as light point defects, and most surprisingly, with improved planarization efficiency in comparison to potassium, sodium and ammonia stabilized slurries.
- An important parameter to determine if a semiconductor wafer has been sufficiently planarized is the number of defects remaining in the treated wafer surface following planarization.
- One type of defect is known in the industry as a “pit” or an undesirable depression in the wafer surface.
- Another defect is known in the industry as a “dig” or “skid” and represents a series of undesirable coarse scratches that are close together.
- Another type of defect is a residual slurry particle that cannot be clean off the substrate.
- the number and type of defects can be determined using art-recognized techniques, including laser light scattering. In general, it is desired to minimize the number of defects.
- the polishing compositions of this invention include at least one Cs+ basic salt.
- Cs+ basic salts include but are not limited to cesium formate, cesium acetate, cesium hydroxide, cesium carbonate, cesium bicarbonates, cesium fluoride, cesium chloride, cesium iodide, and mixtures thereof.
- a preferred Cs+ basic salt is cesium hydroxide (CsOH).
- Basic cesium salts such as cesium hydroxide is an important ingredient of the polishing compositions of this invention because cesium acts as a silica stabilizer. Furthermore, the cesium ions do not penetrate into the dielectric layer to the same depth as ammonium or potassium ions resulting in a dielectric layer with few contaminants and with uniform dielectric properties. The overall result is an unexpected improvement is ILD polishing efficiency, defectivity, and an improvement in dielectric layer purity.
- the polishing compositions of this invention are aqueous compositions of from about 0.01 to about 5.0 wt % basic cesium salt.
- the basic cesium salt will be present in aqueous polishing compositions of this invention in an amount ranging from about 0.1 to about 2.0 wt %.
- the pH of the polishing composition of this invention should be greater than about 7.0 and preferably greater than about 9.0.
- the polishing compositions of this invention may be combined with at least one abrasive prior to using the composition to polish a substrate layer such as an ILD layer.
- the abrasive may be added to the aqueous polishing composition to form an aqueous chemical mechanical polishing slurry.
- the abrasive may be incorporated into a polishing pad during or following the manufacture of the polishing pad.
- the aqueous polishing composition may be applied to a substrate being polished or it may be applied directly to the polishing pad such that the abrasive in the polishing pad and the aqueous polishing composition work in unison to polish the substrate.
- the abrasive used in conjunction with the chemical mechanical polishing compositions of this invention are typically metal oxide abrasives.
- Useful metal oxide abrasives may be selected from the group including alumina, titania, zirconia, germania, silica, ceria and mixtures thereof.
- the compositions of this invention are preferably used in conjunction with a fumed abrasive.
- the fumed abrasive can be any suitable fumed (pyrogenic) metal oxide.
- Suitable fumed metal oxides include, for example, fumed alumina, fumed silica, fumed titania, fumed ceria, fumed zirconia, and fumed magnesia.
- the fumed metal oxide of the composition of the present invention is fumed silica.
- the fumed abrasive and preferably fumed silica may be combined with a second abrasive particles are selected from metal oxides including alumina, silica, titania, ceria, zirconia, and magnesia.
- a second abrasive particles are selected from metal oxides including alumina, silica, titania, ceria, zirconia, and magnesia.
- colloidal abrasive particles condensation-polymerized abrasives
- the second abrasive useful in the compositions and methods of this invention is colloidal silica (condensation-polymerized silica) typically prepared by condensing Si(OH) 4 to form colloidal silica particles.
- Chemical mechanical polishing slurries of this invention will generally include from about 1.0 to about 50.0 weight percent or more of at least one metal oxide abrasive. It is more preferred, however, that the chemical mechanical polishing slurries of this invention include from about 1.0 to about 30.0 weight percent metal oxide abrasive, and most preferably from about 5.0 to about 25.0 wt % metal oxide abrasive. When a mixture of abrasives are used, it is preferred that the abrasives used in the compositions of this invention include from about 25 to about 60% fumed abrasive and from about 40 to about 75% colloidal abrasive with fumed silica and colloidal silica being preferred.
- additives may be incorporated alone or in combination into the polishing composition of this invention.
- a non-inclusive list of optional additives includes inorganic acids, organic acids, surfactants, alkyl ammonium salts or hydroxides, and dispersing agents, additional abrasives, oxidizing agents, complexing agents, film forming agents and so forth.
- Dielectric layers such as silicon dioxide, and tantalum nitride are polished with the above described compositions by subjecting the surface to mechanical rubbing (polishing) in the presence of the composition.
- the rubbing effects mechanical smoothing or wear of the surface which is aided by abrasives in the composition or in the polishing pad, and when present, promoted by the components added to the abrasive to give a chemical mechanical polishing slurry which chemically attacks and dissolves the components comprising the dielectric layer. Polishing may thus be achieved solely by a mechanical mechanism, or by a combination of chemical and mechanical mechanisms.
- the mechanical rubbing or polishing is conveniently effected by contacting the dielectric layer with a polishing pad under a predetermined compressive force with relative motion between the pad and the surface.
- the resulting dynamic friction between the pad and the surface causes the desired wear and smoothing of the disk surface.
- the relative motion is preferably achieved through rotation of either or both the disk surface and the pad.
- polishing pads that are used to polish glass or wafers in the electronics industry may be used. These pads are typically composed of a microporous polymer such as polyurethane foam, or sintered urethane resin optionally backed with a substrate such as felt, latex filled felt, dense polyurethane, or latex.
- the abrasive may be incorporated into the chemical mechanical polishing composition to form a chemical mechanical polishing slurry or it may be incorporated into the polishing pad.
- the chemical mechanical composition or slurry may be applied to the substrate surface being polished, to the polishing pad, or to both during the polishing process.
- the basic cesium salt containing polishing compositions to of this invention are able to polish insulating layers, and in particular silicon dioxide dielectric layers at high efficiencies.
- the polishing compositions of this invention are capable of polishing silicon containing substrate layer, and in particular, a silicon dioxide dielectric layer with an open field efficiency of at least 50%.
- the polishing compositions of this invention are capable of polishing silicon containing substrate layers, and in particular silicon dioxide containing dielectric layers with an array field efficiency of at least 85%.
- polishing compositions of this invention including basic cesium salts are the first polishing compositions that are known to be able to polishing integrated circuit layers with device geometries below about 0.25 microns.
- device geometries refers to average gate width.
- FIG. 1 is a simplified view of a representative semiconductor wafer suitable for use with the composition and process according to the invention.
- well-known features such as doped regions, active devices, epitaxial layers, carrier and field oxide layers.
- Previously deposited interconnect and previously deposited dielectric films have been omitted.
- Base 10 represents a semiconductor material such as, but not limited to single crystal silicon, gallium arsenide, and other semiconductor materials known in the art.
- Base 10 can also represent previous levels of interconnects or gate level dielectric layers.
- metal interconnects blocks 20 On the top surface of base 10 are numerous discrete metal interconnects blocks 20 (e.g., metal conductor blocks).
- Metal interconnect blocks 20 can be made, for example, from aluminum, copper, aluminum copper alloy, tungsten, polysilicon and the like.
- Metal interconnect blocks 20 are made by typical methods known in the art.
- An insulating layer 30 is applied over top of metal interconnect blocks 20 and exposed base portions 10 ′. Insulating layer 30 is typically a metal oxide such as silicon dioxide, BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), or combinations thereof.
- the resulting insulating layer 30 often has a top surface 32 that has topography and is not as “planar” and/or “uniform” as desired.
- planarization or “polishing”.
- FIG. 2 illustrates the wafer shown in FIG. 1 after polishing or planarization.
- the polished surface 34 of insulating layer 30 should be sufficiently planar such that when the subsequent photolithography process is used to create a new circuit design, the critical dimension features can be resolved.
- density will vary.
- the insulating layer sparse regions 36 will polish at a greater rater than the denser regions 38 .
- the sparse regions 36 are located above isolated metal block 40 and the denser regions over the densely packed metal interconnect blocks 20 , 20 ′, and 20 ′′.
- This planar non-uniformity with the die is referred to as WIDNU (within die non-uniformity).
- Shallow trench isolation is another process in which an insulating layer is planarized.
- Shallow Trench Isolation is a process step in IC manufacturing to isolate transistors and other devices in integrated circuits.
- STI has an advantage over other isolation schemes due to improved minimum isolation space, latchup and junction capacitance.
- FIG. 3 is a simplified view of a representative semiconductor wafer suitable for use with the composition and process according to the invention for direct STI polishing. In direct STI polishing, density effects are also important.
- Trenches are etched in semiconductor base 80 which is usually single crystal silicon.
- a hard mask silicon nitride 60 is deposited on the silicon prior to the etching of the trenches.
- the trenches are then filled with silicon dioxide insulating layer 70 .
- the buildup includes denser and sparse areas.
- the goal in STI is to polish until the silicon nitride is fully exposed and only silicon oxide remains in the trenches.
- potential detrimental effects of WIDNU are shown where instead of “stopping” on the silicon nitride 60 the silicon nitride is removed to expose bare silicon 62 . This catastrophic failure usually occurs by the wear of the corner of the isolated feature 64 .
- One method to reduce the density effects in STI polishing are to use a slurry that has a high selectivity to the field area. Topography is removed at a high rate leaving a “planar” surface with a high degree of WIDNU. Subsequent polishing breaks through to the silicon nitride 90 uniformly and minimizes silicon nitride thinning.
- compositions and methods of this invention are useful for achieving the stringent planarization specifications of present day IC wafers.
- This Example evaluated the ability of polishing compositions including various hydroxide compositions to polish silicon containing substrates at high efficiencies and low defectivity.
- polishing slurry compositions are reported in Table 1, below.
- Each polishing composition included CAB-O-SPERSE® SC-E fumed silica manufactured by Cabot Corporation.
- the slurries were stabilized with CsOH or KOH by adding a sufficient amount of each base to each slurry to increase the slurry pH to 10.8.
- the polishing compositions were used to planarize a test wafer.
- the test wafers were test patterns of a MIT designed mask where aluminum lines were created on a silicon substrate.
- the wafers had approximately 9000 angstroms of step height.
- the patterns were a 250 micron line pitch with systematically varying densities ranging from 100 to 8% where 100% means 100% stack area and 25% means that the lines are thick enough that 25 % is stack area and 75 % is field area.
- Each wafer was planarized using an IPEC 472 polishing machine.
- the wafers were polished using a down force of 7.5 psi, a back pressure of 3 psi, a platen speed of 37 rpm, a carrier speed of 24 rpm, and a slurry flow rate of 220 ml/min.
- the wafers were polished for 60, 90, 120 and 150 seconds. Polishing data (step height, stack thickness, field thickness) was collected for each wafer at the fixed polishing intervals (60, 90, 120, and 150 seconds).
- Step height can be measured directly by a Tencor P20 profilometer or step height can be measured by Tencor Surfscan UV 1050 and calculated by the following equation.
- Step height initial step height ⁇ stack (initial stack thickness ⁇ polished stack thickness)+ ⁇ field (initial field thickness ⁇ polished field thickness)
- the curve is fit to the data by interpolating the data along the fitted polishing curve to determine the time at which 95% planarization is achieved (i.e. step height is reduced to 450 ⁇ ).
- the procedure for calculating the open field efficiency and the array field efficiency are the same.
- the field thickness measurement is at the 8% density region.
- the field thickness measurement is at the 52% density region.
- polishing results indicate that polishing compositions with cesium hydroxide polish silicon containing substrates at a much higher open field and array filed efficiency that polishing compositions including potassium hydroxide. Specifically, polishing compositions including cesium hydroxide polish silicon containing substrates with a lower filed loss, an improved open field efficiency and an improved array field efficiency.
- Open field and array field efficiencies are dependent upon polishing parameters, polishing machine, and other consumables and slurries.
- the term “open field efficiency” and “array field efficiency” refer to the polishing efficiencies determined using an IPEC 472 polishing machine operating at the polishing parameters described above and calculated as described above.
- the planarization rate of polishing slurries including CsOH, KOH, and NH 4 0H were evaluated.
- Each slurry tested included 12 wt % of CAB-O-SPERSE® SC-E fumed silica manufactured by Cabot Corp.
- the slurries were stabilized with CsOH, KOH, or NH 4 OH by adding a sufficient amount of each base to each slurry to increase the slurry pH to 10.8.
- Each slurry was used to polish a wafer described in Example 1 according to the method described in Example 1.
- planarization results are represented graphically in FIGS. 5 and 6.
- the planarization rate of CsOH and KOH slurries are superior to slurries including NH 4 OH.
- slurries including CsOH planarize silicon substrates more efficiently than slurries including KOH or NH 4 OH.
- the greater efficiency is seen in the delta field improvement over the same step height for CsOH slurries in comparison to KOH and NH 4 OH slurries.
- This Example evaluated the planarization rate of commercially available polishing slurries. Two slurries were tested. The first slurry D7000, a 10.5 wt % fumed silica dispersion stabilized with KOH. The second slurry was Klebsol 30N50, an 30 wt % ammonia stabilized colloidal silica manufactured by Clariant. Each slurry was used to polish a wafer described in Example 1 according to the polishing method described in Example 1.
Abstract
Description
- (1) Field of the Invention
- This invention concerns chemical mechanical polishing compositions including an abrasive and cesium hydroxide. This invention also concerns methods for polishing dielectric layers associated with integrated circuits using cesium hydroxide containing polishing compositions.
- (2) Description of the Art
- Integrated circuits are made up of millions of active devices formed in or on a silicon substrate. The active devices, which are initially isolated from one another, are interconnected to form functional circuits and components. The devices are interconnected through the use of multilevel interconnections. Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third and subsequent level of metallization. Interlevel dielectrics (ILDs) such as doped and undoped silicon dioxide (SiO2), or low-K dielectrics tantalum nitride are used to electrically isolate the different levels of metallization in a silicon substrate or well.
- In typical semiconductor manufacturing processes, metallized vias, metallized layer and interlevel dielectric layers are built-up to create an integrated circuit. As the layers are being built-up, the excess materials are removed and the substrate surfaces are planarized by using chemical mechanical polishing (CMP) techniques. In a typical chemical mechanical polishing process, the substrate is placed in direct contact with a rotating polishing pad. A carrier applies pressure against the backside of the substrate. During the polishing process, the pad and table are rotated while a downward force is maintained against the substrate back. An abrasive and chemically reactive solution is applied to the pad during polishing. The slurry initiates the polishing process by chemically reacting with the film being polished. The polishing process is facilitated by the rotational movement of the pad relative to the substrate as slurry is provided to the wafer/pad interface. Polishing is continued in this manner until the desired film on the insulator is removed.
- The polishing composition ingredients are an important factor in the success of the CMP step. By carefully selecting ingredients, the polishing composition can be tailored to provide effective polishing to the selected layer at desired polishing rates while minimizing surface imperfections, defects and corrosion and erosion of adjacent layers. During the manufacture of integrated circuits, dielectric layers, typically including silicon dioxide are applied to the circuit. Once applied, the dielectric layer is generally non-planar and must be polished using a polishing composition to give a planar dielectric surface. It is important that the chosen polishing composition be capable of producing a planarized dielectric surface with few defects. Furthermore, it is important that the polishing composition chosen be capable of polishing the dielectric layer efficiently and repeatedly. Current ILD slurries are typically stabilized abrasive slurries including about 10-30 wt % abrasives. The stabilizing ion is typically potassium or ammonia where slurries typically have a pH greater than 8. The shortcomings of potassium slurries are ionic contamination from the potassium where the contaminating ions become mobile ions and will detrimentally impact device reliability by migrating to the
gate area 20 and lowering the threshold voltage of the transistors. In addition, there is a level of defectivity that is characteristic of silica dispersed with potassium. - Ammonia slurries solve the mobile ion problem associated with potassium stabilized slurries. However, ammonia has a strong odor. In addition, ammonia slurries planarize less effectively, polish with a high level of defectivity and polish with low rates compared to potassium slurries.
- As a result, there remains a need for improved polishing compositions that are capable of polishing dielectric layers efficiently to give polished dielectric layers that are essentially planar and that exhibit few defects.
- In one embodiment, this invention is a chemical mechanical polishing composition comprising fumed silica and from about 0.01 to about 5.0 wt % of at least one Cs+ basic salt.
- In another embodiment, this invention is a chemical mechanical polishing composition comprising water, from about 1 to about 50 wt % fumed silica, and from about 0.1 to about 2.0 wt % CsOH. The polishing composition planarizes a silicon containing substrate with an open field efficiency of at least 50% and with an array field efficiency of at least 85 %.
- In yet another embodiment, this invention is a chemical mechanical polishing composition capable of polishing integrated circuits having gate widths less than about 0.25 microns comprising from about 1 to about 50 wt % of a metal oxide abrasive and from about 0.01 to about 5.0 wt % Cs+ basic salt.
- In still another embodiment, this invention is a method for planarizing an insulating layer with a polishing composition of this invention. The polishing is achieved by preparing a polishing composition comprising water and CsOH. The polishing composition is then applied to a surface of the substrate being planarized or to the polishing pad. The polishing pad is brought into contact with the surface of the silicon containing substrate layer being planarized, and the pad is moved in relation to the silicon containing substrate surface being planarized. An abrasive is used in conjunction with the polishing composition to facilitate polishing. The abrasive may be associated with the polishing pad or the abrasive may be added to the polishing composition to give a chemical mechanical polishing slurry before the slurry is applied to the substrate or to the polishing pad.
- FIG. 1 is a simplified side-cutaway view of a portion of a semiconductor wafer that suitable for planarizing using the compositions and methods of this invention;
- FIG. 2 illustrates the wafer shown in FIG. 1 after polishing;
- FIG. 3 is a simplified side-cutaway view of a portion of a semiconductor wafer suitable for shallow trench isolation planarization using the compositions and methods of this invention;
- FIG. 4 is the wafer of FIG. 3 including defects that could result due to inefficient planarization;
- FIG. 5 is a plot of polish time versus step height for CsOH (A & B), KOH, (C) and NH4OH (D) slurries tested according to the method described in Example 2. The term “polish time” in the plot refers to the time, in seconds, that the substrate is being polished. The term “step height” in the plot refers to the distance from the high points on the topography to the low points during the fabrication of integrated circuits. As devices are built a surface topography is produced and perpetuated through subsequent thin-film depositions. Step height is usually measured in Angstroms; and
- FIG. 6 is a plot of delta field versus step height for slurries tested according to the method of described in Example 2.
- The present invention relates to chemical mechanical polishing compositions including an abrasive and at least one Cs+ basic salt such as cesium hydroxide. This invention also concerns methods for polishing dielectric layers associated with integrated circuits using Cs+ 5 basic salt containing polishing compositions.
- Basic cesium salt stabilized slurries show an unexpected performance enhancement as compared to ammonia and potassium hydroxide stabilized slurries. Cesium ions have lower mobility than potassium and sodium ions. Furthermore, cesium ion containing polishing compositions polish at higher rates than ammonia slurries and do not have a foul odor like ammonia stabilizes slurries. Also, cesium ion containing polishing compositions polish with lower defectivity as measured as light point defects, and most surprisingly, with improved planarization efficiency in comparison to potassium, sodium and ammonia stabilized slurries.
- An important parameter to determine if a semiconductor wafer has been sufficiently planarized is the number of defects remaining in the treated wafer surface following planarization. One type of defect is known in the industry as a “pit” or an undesirable depression in the wafer surface. Another defect is known in the industry as a “dig” or “skid” and represents a series of undesirable coarse scratches that are close together. Another type of defect is a residual slurry particle that cannot be clean off the substrate. The number and type of defects can be determined using art-recognized techniques, including laser light scattering. In general, it is desired to minimize the number of defects.
- The polishing compositions of this invention include at least one Cs+ basic salt. Examples of Cs+ basic salts include but are not limited to cesium formate, cesium acetate, cesium hydroxide, cesium carbonate, cesium bicarbonates, cesium fluoride, cesium chloride, cesium iodide, and mixtures thereof. A preferred Cs+ basic salt is cesium hydroxide (CsOH).
- Basic cesium salts such as cesium hydroxide is an important ingredient of the polishing compositions of this invention because cesium acts as a silica stabilizer. Furthermore, the cesium ions do not penetrate into the dielectric layer to the same depth as ammonium or potassium ions resulting in a dielectric layer with few contaminants and with uniform dielectric properties. The overall result is an unexpected improvement is ILD polishing efficiency, defectivity, and an improvement in dielectric layer purity.
- The polishing compositions of this invention are aqueous compositions of from about 0.01 to about 5.0 wt % basic cesium salt. Preferably, the basic cesium salt will be present in aqueous polishing compositions of this invention in an amount ranging from about 0.1 to about 2.0 wt %.
- For best results, the pH of the polishing composition of this invention should be greater than about 7.0 and preferably greater than about 9.0.
- The polishing compositions of this invention may be combined with at least one abrasive prior to using the composition to polish a substrate layer such as an ILD layer. The abrasive may be added to the aqueous polishing composition to form an aqueous chemical mechanical polishing slurry. Alternatively, the abrasive may be incorporated into a polishing pad during or following the manufacture of the polishing pad. When the abrasive is associated with the polishing pad, the aqueous polishing composition may be applied to a substrate being polished or it may be applied directly to the polishing pad such that the abrasive in the polishing pad and the aqueous polishing composition work in unison to polish the substrate.
- The abrasive used in conjunction with the chemical mechanical polishing compositions of this invention are typically metal oxide abrasives. Useful metal oxide abrasives may be selected from the group including alumina, titania, zirconia, germania, silica, ceria and mixtures thereof. The compositions of this invention are preferably used in conjunction with a fumed abrasive.
- The fumed abrasive can be any suitable fumed (pyrogenic) metal oxide. Suitable fumed metal oxides include, for example, fumed alumina, fumed silica, fumed titania, fumed ceria, fumed zirconia, and fumed magnesia. Preferably, the fumed metal oxide of the composition of the present invention is fumed silica.
- The fumed abrasive and preferably fumed silica may be combined with a second abrasive particles are selected from metal oxides including alumina, silica, titania, ceria, zirconia, and magnesia. Also suitable for use in the composition are colloidal abrasive particles (condensation-polymerized abrasives) prepared in accordance with U.S. Pat. No. 5,230,833 (Romberger et al.) and various commercially available products, such as the Akzo-
Nobel Bindzil 50/80 product and the Nalco 1050, 2327, and 2329 products as well as other similar products. Preferably, the second abrasive useful in the compositions and methods of this invention is colloidal silica (condensation-polymerized silica) typically prepared by condensing Si(OH)4 to form colloidal silica particles. - Chemical mechanical polishing slurries of this invention will generally include from about 1.0 to about 50.0 weight percent or more of at least one metal oxide abrasive. It is more preferred, however, that the chemical mechanical polishing slurries of this invention include from about 1.0 to about 30.0 weight percent metal oxide abrasive, and most preferably from about 5.0 to about 25.0 wt % metal oxide abrasive. When a mixture of abrasives are used, it is preferred that the abrasives used in the compositions of this invention include from about 25 to about 60% fumed abrasive and from about 40 to about 75% colloidal abrasive with fumed silica and colloidal silica being preferred.
- Other well known additives may be incorporated alone or in combination into the polishing composition of this invention. A non-inclusive list of optional additives includes inorganic acids, organic acids, surfactants, alkyl ammonium salts or hydroxides, and dispersing agents, additional abrasives, oxidizing agents, complexing agents, film forming agents and so forth.
- Dielectric layers such as silicon dioxide, and tantalum nitride are polished with the above described compositions by subjecting the surface to mechanical rubbing (polishing) in the presence of the composition. The rubbing effects mechanical smoothing or wear of the surface which is aided by abrasives in the composition or in the polishing pad, and when present, promoted by the components added to the abrasive to give a chemical mechanical polishing slurry which chemically attacks and dissolves the components comprising the dielectric layer. Polishing may thus be achieved solely by a mechanical mechanism, or by a combination of chemical and mechanical mechanisms.
- The mechanical rubbing or polishing is conveniently effected by contacting the dielectric layer with a polishing pad under a predetermined compressive force with relative motion between the pad and the surface. The resulting dynamic friction between the pad and the surface causes the desired wear and smoothing of the disk surface. The relative motion is preferably achieved through rotation of either or both the disk surface and the pad. Commercially available polishing pads that are used to polish glass or wafers in the electronics industry may be used. These pads are typically composed of a microporous polymer such as polyurethane foam, or sintered urethane resin optionally backed with a substrate such as felt, latex filled felt, dense polyurethane, or latex.
- As mentioned above, the abrasive may be incorporated into the chemical mechanical polishing composition to form a chemical mechanical polishing slurry or it may be incorporated into the polishing pad. In either instance, the chemical mechanical composition or slurry may be applied to the substrate surface being polished, to the polishing pad, or to both during the polishing process.
- We have surprisingly found that the basic cesium salt containing polishing compositions to of this invention are able to polish insulating layers, and in particular silicon dioxide dielectric layers at high efficiencies. Specifically, the polishing compositions of this invention are capable of polishing silicon containing substrate layer, and in particular, a silicon dioxide dielectric layer with an open field efficiency of at least 50%. In addition, the polishing compositions of this invention are capable of polishing silicon containing substrate layers, and in particular silicon dioxide containing dielectric layers with an array field efficiency of at least 85%.
- We have also learned that the polishing compositions of this invention including basic cesium salts are the first polishing compositions that are known to be able to polishing integrated circuit layers with device geometries below about 0.25 microns. The term device geometries refers to average gate width.
- FIG. 1 is a simplified view of a representative semiconductor wafer suitable for use with the composition and process according to the invention. For the sake of clarity, well-known features such as doped regions, active devices, epitaxial layers, carrier and field oxide layers. Previously deposited interconnect and previously deposited dielectric films have been omitted.
Base 10 represents a semiconductor material such as, but not limited to single crystal silicon, gallium arsenide, and other semiconductor materials known in the art.Base 10 can also represent previous levels of interconnects or gate level dielectric layers. - On the top surface of
base 10 are numerous discrete metal interconnects blocks 20 (e.g., metal conductor blocks). Metal interconnect blocks 20 can be made, for example, from aluminum, copper, aluminum copper alloy, tungsten, polysilicon and the like. Metal interconnect blocks 20 are made by typical methods known in the art. An insulatinglayer 30 is applied over top of metal interconnect blocks 20 and exposedbase portions 10′. Insulatinglayer 30 is typically a metal oxide such as silicon dioxide, BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), or combinations thereof. The resulting insulatinglayer 30 often has atop surface 32 that has topography and is not as “planar” and/or “uniform” as desired. - Before an additional layer of circuitry can be applied via and patterned photolithography, it is usually necessary to polish
top surface 32 of the insulatinglayer 30 to achieve the desired degree of planarity and/or uniformity. The particular degree of planarity required will depend on many factors, including the individual wafer and the application for which it is intended, as well as the nature of any subsequent processing steps to which the wafer may be subjected. For the sake of simplicity, throughout the remainder of this application this process will be referred to as “planarization” or “polishing”. - FIG. 2 illustrates the wafer shown in FIG. 1 after polishing or planarization. As a result of planarization, the
polished surface 34 of insulatinglayer 30 should be sufficiently planar such that when the subsequent photolithography process is used to create a new circuit design, the critical dimension features can be resolved. It should be noted that within a die metal block or device (array) density will vary. Typically, the insulating layersparse regions 36 will polish at a greater rater than thedenser regions 38. In FIGS. 1 and 2 thesparse regions 36 are located aboveisolated metal block 40 and the denser regions over the densely packed metal interconnect blocks 20, 20′, and 20″. This planar non-uniformity with the die is referred to as WIDNU (within die non-uniformity). - The magnitude of this type of non-uniformity that can be tolerated in state of the art devices has decreased dramatically as device features (i.e., gate width) shrink below about 0.25 microns. One method of minimizing non-uniformity is to develop slurries and processes that will remove topography, including insulating layers very efficiently but with minimal field loss i.e., loss of insulating layer in sparse regions. Thus a slurry and polishing process that polishes sparse regions slowly will allow the more stringent WIDNU tolerances to be achieved. Two factors drive these more stringent WIDNU tolerances. Both factors are related to smaller and faster computer chips. The first factor is depth of focus considerations during the photolithography step. As the devices shrink to 0.25 micron and below the stepper apertures are smaller making the depths of focus tolerance shallower and making insulating layer thickness uniformly via a global planarity more important. In addition, what limits the performance speed in some state-of-art chips is RC time delays in the backend interconnects. To control RC time delays and to maintain attainable clock speeds constant across the die, improved uniformity of the dielectric insulating layers is required.
- Shallow trench isolation is another process in which an insulating layer is planarized. Shallow Trench Isolation (STI) is a process step in IC manufacturing to isolate transistors and other devices in integrated circuits. STI has an advantage over other isolation schemes due to improved minimum isolation space, latchup and junction capacitance. FIG. 3 is a simplified view of a representative semiconductor wafer suitable for use with the composition and process according to the invention for direct STI polishing. In direct STI polishing, density effects are also important. Trenches are etched in
semiconductor base 80 which is usually single crystal silicon. A hardmask silicon nitride 60 is deposited on the silicon prior to the etching of the trenches. The trenches are then filled with silicondioxide insulating layer 70. Once again the buildup includes denser and sparse areas. Unlike interlayer dielectric polishing the goal in STI is to polish until the silicon nitride is fully exposed and only silicon oxide remains in the trenches. In FIG. 4 potential detrimental effects of WIDNU are shown where instead of “stopping” on thesilicon nitride 60 the silicon nitride is removed to exposebare silicon 62. This catastrophic failure usually occurs by the wear of the corner of theisolated feature 64. One method to reduce the density effects in STI polishing are to use a slurry that has a high selectivity to the field area. Topography is removed at a high rate leaving a “planar” surface with a high degree of WIDNU. Subsequent polishing breaks through to the silicon nitride 90 uniformly and minimizes silicon nitride thinning. - As shown in the Examples below, the compositions and methods of this invention are useful for achieving the stringent planarization specifications of present day IC wafers.
- This Example evaluated the ability of polishing compositions including various hydroxide compositions to polish silicon containing substrates at high efficiencies and low defectivity.
- The polishing slurry compositions are reported in Table 1, below. Each polishing composition included CAB-O-SPERSE® SC-E fumed silica manufactured by Cabot Corporation. The slurries were stabilized with CsOH or KOH by adding a sufficient amount of each base to each slurry to increase the slurry pH to 10.8. The polishing compositions were used to planarize a test wafer. The test wafers were test patterns of a MIT designed mask where aluminum lines were created on a silicon substrate. The wafers had approximately 9000 angstroms of step height. The patterns were a 250 micron line pitch with systematically varying densities ranging from 100 to 8% where 100% means 100% stack area and 25% means that the lines are thick enough that 25 % is stack area and 75 % is field area.
- Field measurements were taken from two areas of each wafer—the open field and the array field—and the measurements were used in the efficiency calculations. Array field measurements were taken in close proximity to the stack area. Because wide open (or sparse) areas are typically more problematic in real polishing we also evaluated slurry polishing efficiency by measuring the field in the largest open field area or the 8% area and calculating the open field efficiency from the measurement.
- Each wafer was planarized using an IPEC 472 polishing machine. The wafers were polished using a down force of 7.5 psi, a back pressure of 3 psi, a platen speed of 37 rpm, a carrier speed of 24 rpm, and a slurry flow rate of 220 ml/min. The wafers were polished for 60, 90, 120 and 150 seconds. Polishing data (step height, stack thickness, field thickness) was collected for each wafer at the fixed polishing intervals (60, 90, 120, and 150 seconds).
- There are two ways to measure step height. Step height can be measured directly by a Tencor P20 profilometer or step height can be measured by Tencor Surfscan UV 1050 and calculated by the following equation.
- Step height=initial step height−Δstack (initial stack thickness−polished stack thickness)+Δfield (initial field thickness−polished field thickness)
- A plot was created for each slurry showing step height vs. time. The curve is fit to the data by interpolating the data along the fitted polishing curve to determine the time at which 95% planarization is achieved (i.e. step height is reduced to 450 Å). Planarization efficiency (sp) is calculated at each of the polishing intervals using the following formula:
- The calculated planarization efficiency was then plotted vs. time, and a curve is fit to the data. Taking the efficiency curve and identifying the time at which 95% planarization is achieved, the efficiency at the time required to reach 95% planarization is calculated.
- The procedure for calculating the open field efficiency and the array field efficiency are the same. For open field efficiency, the field thickness measurement is at the 8% density region. For array field efficiency, the field thickness measurement is at the 52% density region.
- The polishing results, array field efficiencies and open filed efficiencies are reported in Table 1, below.
TABLE 1 Open Improvement Open Slurry Field In Field Field Array Field Composition Loss (Å) Loss (%) Efficiency Efficiency 10 wt % Silica; 4351 19% Reduction 55.5% 88.0% CsOH 13 wt % Silica; 4831 10% Reduction 52.7% 84.0% CsOH 12.5 wt % Silica; 5374 49.7% 81.1% KOH - The polishing results indicate that polishing compositions with cesium hydroxide polish silicon containing substrates at a much higher open field and array filed efficiency that polishing compositions including potassium hydroxide. Specifically, polishing compositions including cesium hydroxide polish silicon containing substrates with a lower filed loss, an improved open field efficiency and an improved array field efficiency.
- Open field and array field efficiencies are dependent upon polishing parameters, polishing machine, and other consumables and slurries. For purposes of this application, the term “open field efficiency” and “array field efficiency” refer to the polishing efficiencies determined using an IPEC 472 polishing machine operating at the polishing parameters described above and calculated as described above.
- In this Example, the planarization rate of polishing slurries including CsOH, KOH, and NH40H were evaluated. Each slurry tested included 12 wt % of CAB-O-SPERSE® SC-E fumed silica manufactured by Cabot Corp. The slurries were stabilized with CsOH, KOH, or NH4OH by adding a sufficient amount of each base to each slurry to increase the slurry pH to 10.8. Each slurry was used to polish a wafer described in Example 1 according to the method described in Example 1.
- The planarization results are represented graphically in FIGS.5 and 6. According to FIG. 5, the planarization rate of CsOH and KOH slurries are superior to slurries including NH4OH. According to FIG. 6, slurries including CsOH planarize silicon substrates more efficiently than slurries including KOH or NH4OH. The greater efficiency is seen in the delta field improvement over the same step height for CsOH slurries in comparison to KOH and NH4OH slurries.
- This Example evaluated the planarization rate of commercially available polishing slurries. Two slurries were tested. The first slurry D7000, a 10.5 wt % fumed silica dispersion stabilized with KOH. The second slurry was Klebsol 30N50, an 30 wt % ammonia stabilized colloidal silica manufactured by Clariant. Each slurry was used to polish a wafer described in Example 1 according to the polishing method described in Example 1.
- The planarization results are reported in Table 2, below.
TABLE 2 Open Slurry Field Improvement In Open Field Array Field Composition Loss (Å) Field Loss (%) Efficiency Efficiency D7000 5015 12.4% reduction 52.4% 82.7% 30N50 5726 47.6 81.4%
Claims (26)
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US09/428,965 US6350393B2 (en) | 1999-11-04 | 1999-11-04 | Use of CsOH in a dielectric CMP slurry |
DE60009546T DE60009546T2 (en) | 1999-11-04 | 2000-10-31 | USE OF CÄSIUM HYDROXYDE FOR DIELECTRIC AIR INSULATION |
JP2001535478A JP2003514061A (en) | 1999-11-04 | 2000-10-31 | Use of CsOH in dielectric CMP slurry |
KR1020027005704A KR20020077343A (en) | 1999-11-04 | 2000-10-31 | Use of Cesium Hydroxide in a Dielectric CMP Slurry |
PCT/US2000/041707 WO2001032793A2 (en) | 1999-11-04 | 2000-10-31 | Use of cesium hydroxide in a dielectric cmp slurry |
AT00991904T ATE263224T1 (en) | 1999-11-04 | 2000-10-31 | USE OF CESIUM HYDROXYDE FOR DIELECTRIC SLURRY |
EP00991904A EP1234010B1 (en) | 1999-11-04 | 2000-10-31 | Use of cesium hydroxide in a dielectric cmp slurry |
AU36390/01A AU3639001A (en) | 1999-11-04 | 2000-10-31 | Use of csoh in a dielectric cmp slurry |
CNB008151466A CN1220742C (en) | 1999-11-04 | 2000-10-31 | Use of CsOH in dielectric CMP slurry |
TW089123290A TW554022B (en) | 1999-11-04 | 2000-12-05 | Chemical mechanical polishing composition and method for planarizing a silicon containing substrate with a polishing pad |
HK03100847.2A HK1048826A1 (en) | 1999-11-04 | 2003-02-06 | Use of cesium hydroxide in a dielectric cmp slurry |
JP2012096848A JP2012156550A (en) | 1999-11-04 | 2012-04-20 | USE OF CsOH IN DIELECTRIC CMP SLURRY |
JP2015094245A JP6030703B2 (en) | 1999-11-04 | 2015-05-01 | Use of CsOH in dielectric CMP slurry |
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EP (1) | EP1234010B1 (en) |
JP (3) | JP2003514061A (en) |
KR (1) | KR20020077343A (en) |
CN (1) | CN1220742C (en) |
AT (1) | ATE263224T1 (en) |
AU (1) | AU3639001A (en) |
DE (1) | DE60009546T2 (en) |
HK (1) | HK1048826A1 (en) |
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WO (1) | WO2001032793A2 (en) |
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US20070131160A1 (en) * | 2005-12-02 | 2007-06-14 | Slack Glen A | Doped aluminum nitride crystals and methods of making them |
US20070134827A1 (en) * | 2005-11-28 | 2007-06-14 | Bondokov Robert T | Large aluminum nitride crystals with reduced defects and methods of making them |
US20070163677A1 (en) * | 2003-04-10 | 2007-07-19 | Yair Ein-Eli | Copper cmp slurry composition |
US20090050050A1 (en) * | 2007-05-24 | 2009-02-26 | Crystal Is, Inc. | Deep-eutectic melt growth of nitride crystals |
US20090283028A1 (en) * | 2001-12-24 | 2009-11-19 | Crystal Is, Inc. | Nitride semiconductor heterostructures and related methods |
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US8080833B2 (en) | 2007-01-26 | 2011-12-20 | Crystal Is, Inc. | Thick pseudomorphic nitride epitaxial layers |
US8123859B2 (en) | 2001-12-24 | 2012-02-28 | Crystal Is, Inc. | Method and apparatus for producing large, single-crystals of aluminum nitride |
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US8962359B2 (en) | 2011-07-19 | 2015-02-24 | Crystal Is, Inc. | Photon extraction from nitride ultraviolet light-emitting devices |
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US9034103B2 (en) | 2006-03-30 | 2015-05-19 | Crystal Is, Inc. | Aluminum nitride bulk crystals having high transparency to ultraviolet light and methods of forming them |
US9039914B2 (en) | 2012-05-23 | 2015-05-26 | Cabot Microelectronics Corporation | Polishing composition for nickel-phosphorous-coated memory disks |
US9299880B2 (en) | 2013-03-15 | 2016-03-29 | Crystal Is, Inc. | Pseudomorphic electronic and optoelectronic devices having planar contacts |
US9437430B2 (en) | 2007-01-26 | 2016-09-06 | Crystal Is, Inc. | Thick pseudomorphic nitride epitaxial layers |
US9447521B2 (en) | 2001-12-24 | 2016-09-20 | Crystal Is, Inc. | Method and apparatus for producing large, single-crystals of aluminum nitride |
US9771666B2 (en) | 2007-01-17 | 2017-09-26 | Crystal Is, Inc. | Defect reduction in seeded aluminum nitride crystal growth |
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- 2000-10-31 KR KR1020027005704A patent/KR20020077343A/en not_active Application Discontinuation
- 2000-10-31 JP JP2001535478A patent/JP2003514061A/en not_active Withdrawn
- 2000-10-31 AT AT00991904T patent/ATE263224T1/en not_active IP Right Cessation
- 2000-10-31 DE DE60009546T patent/DE60009546T2/en not_active Expired - Lifetime
- 2000-10-31 CN CNB008151466A patent/CN1220742C/en not_active Expired - Fee Related
- 2000-10-31 WO PCT/US2000/041707 patent/WO2001032793A2/en active IP Right Grant
- 2000-10-31 EP EP00991904A patent/EP1234010B1/en not_active Expired - Lifetime
- 2000-10-31 AU AU36390/01A patent/AU3639001A/en not_active Abandoned
- 2000-12-05 TW TW089123290A patent/TW554022B/en not_active IP Right Cessation
-
2003
- 2003-02-06 HK HK03100847.2A patent/HK1048826A1/en unknown
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2012
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2015
- 2015-05-01 JP JP2015094245A patent/JP6030703B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
CN1220742C (en) | 2005-09-28 |
CN1387556A (en) | 2002-12-25 |
DE60009546T2 (en) | 2005-02-03 |
EP1234010B1 (en) | 2004-03-31 |
WO2001032793A3 (en) | 2001-08-02 |
ATE263224T1 (en) | 2004-04-15 |
TW554022B (en) | 2003-09-21 |
JP2012156550A (en) | 2012-08-16 |
EP1234010A2 (en) | 2002-08-28 |
DE60009546D1 (en) | 2004-05-06 |
AU3639001A (en) | 2001-05-14 |
WO2001032793A8 (en) | 2001-10-04 |
HK1048826A1 (en) | 2003-04-17 |
JP6030703B2 (en) | 2016-11-24 |
US6350393B2 (en) | 2002-02-26 |
WO2001032793A2 (en) | 2001-05-10 |
JP2015147938A (en) | 2015-08-20 |
KR20020077343A (en) | 2002-10-11 |
JP2003514061A (en) | 2003-04-15 |
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