US20010052621A1 - PD-SOI substrate with suppressed floating body effect and method for its fabrication - Google Patents
PD-SOI substrate with suppressed floating body effect and method for its fabrication Download PDFInfo
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- US20010052621A1 US20010052621A1 US09/930,451 US93045101A US2001052621A1 US 20010052621 A1 US20010052621 A1 US 20010052621A1 US 93045101 A US93045101 A US 93045101A US 2001052621 A1 US2001052621 A1 US 2001052621A1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Definitions
- the present invention relates to the field of semiconductor integrated circuits and, in particular, to partially-depleted Silicon on Insulator (PD-SOI) substrates and devices.
- PD-SOI partially-depleted Silicon on Insulator
- Silicon on Insulator (SOI) technology employs a layer of semiconductor material formed over an insulating layer on a supporting bulk wafer.
- the structure can be formed by different well-known techniques in the art, for example, separation by implanted oxygen (SIMOX), bonding and etching back (BESOI), and zone melting and recrystallization (ZMR), among others.
- the structure comprises a film of monocrystalline silicon formed on a buried layer of silicon oxide which is formed on a monocrystalline silicon substrate.
- an epitaxial (epi) silicon layer is used as a top silicon layer, which is generally formed by one of two methods: (1) bonding followed by etch back; or (2) epitaxial layer transfer (ELTRAN) process.
- FIGS. 1 - 4 One technique for the formation of a SOI substrate by a conventional bonding and etching back method of the prior art is illustrated in FIGS. 1 - 4 .
- the process starts with the preparation of a silicon substrate 10 (FIG. 1).
- the silicon substrate 10 is thermally oxidized to grow a layer of silicon oxide 12 (FIG. 1), with a thickness of about 1 micron.
- an n-type single crystalline silicon substrate 14 is opposed to the silicon oxide layer 12 , as shown in FIG. 2.
- the silicon substrate 10 with the oxide layer 12 , is then contacted with the crystalline silicon substrate 14 , and the resultant structure is heated to a temperature of about 1000° C., so that the n-type crystalline silicon of the crystalline silicon substrate 14 adheres to the silicon oxide layer 12 , as shown in FIG. 3.
- the n-type crystalline silicon substrate 14 is polished and its thickness is decreased to approximately 1.5 microns.
- a SOI substrate 15 (FIG. 4) is formed of the silicon substrate 10 , the silicon oxide layer 12 , and the n-type crystalline silicon substrate 14 .
- Field effect transistors such as MOSFETs, which are fabricated in the upper silicon layer of a SOI structure, such as the SOI substrate 15 of FIG. 4, have multiple advantages over the transistors fabricated on the conventional bulk silicon substrates. These advantages include, among others, resistance to short-channel effect, increased current drive, higher packing density, and reduced parasitic capacitance.
- SOI technology still has some drawbacks, which reduce the benefits of using it for high-performance and high-density ultra large scale integrated (ULSI) circuits.
- ULSI ultra large scale integrated
- One drawback of the SOI technology is the conductivity of the top Si layer and its inherent floating body effect, which has particular significance for partially-depleted (PD) or non-fully depleted SOI devices.
- the floating body effect in such devices occurs as a result of the buried oxide that isolates the channel region of such device and allows charge carriers to build up in the channel region.
- charge carriers holes in an nMOSFET and electrons in a pMOSFET
- charge carriers generated by impact ionization near the drain/source region, accumulate near the source/drain region of the transistor.
- When sufficient carriers accumulate they are stored in the floating body, which is formed right below the channel region, and alter the floating body potential.
- kinks in the I/V curve occur, the threshold voltage is lowered, and the overall electrical performance of the device may be severely degraded.
- the present invention provides a simple method for forming a partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up to mitigate the floating body effect, which can be further used for the fabrication of SOI devices with reduced threshold voltage and leakage.
- SOI Silicon-on-Insulator
- the method of the present invention employs a thin Si/Ge epitaxial layer grown between two adjacent epitaxial silicon layers of the partially-depleted SOI substrate.
- the thin Si/Ge epitaxial layer, grown during the epitaxial growth of silicon introduces misfit dislocations, which are formed as a result of the lattice mismatch between the silicon and germanium atoms, and which act as both recombination sites and proximity gettering sites.
- the newly-formed dislocations lie close to the buried oxide and remove the accumulated charges, so that the performance of the partially-depleted (PD) SOI device remains largely unaffected by charge build up.
- FIG. 1 is a cross-sectional view of a SOI substrate at an initial stage of processing and in accordance with a method of the prior art.
- FIG. 2 is a cross-sectional view of the SOI substrate of FIG. 1 at a stage of processing subsequent to that shown in FIG. 1.
- FIG. 3 is a cross-sectional view of the SOI substrate of FIG. 1 at a stage of processing subsequent to that shown in FIG. 2.
- FIG. 4 is a cross-sectional view of the SOI substrate of FIG. 1 at a stage of processing subsequent to that shown in FIG. 3.
- FIG. 5 is a cross-sectional view of a partially-depleted SOI substrate at an initial stage of processing and in accordance with a first embodiment of the present invention.
- FIG. 6 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 5.
- FIG. 7 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 6.
- FIG. 8 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 7.
- FIG. 9 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 8.
- FIG. 10 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 9.
- FIG. 11 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 10.
- FIG. 12 is a cross-sectional view of a portion of a MOSFET having a partially-depleted SOI substrate according to the present invention.
- FIG. 13 is a cross-sectional view of the MOSFET structure of FIG. 12 at a stage of processing subsequent to that shown in FIG. 12.
- FIG. 14 is an illustration of a computer system having a memory cell access transistor constructed on a partially-depleted SOI substrate according to the present invention.
- FIG. 15 a cross-sectional view of a partially-depleted SOI substrate at an initial stage of processing and in accordance with a second embodiment of the present invention.
- the present invention provides a method for forming a partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and reduced floating body effect.
- the method of the present invention employs a thin Si/Ge epitaxial layer formed between two adjacent epitaxial silicon layers of a partially-depleted SOI device.
- the thin Si/Ge epitaxial layer grown during the epitaxial growth of silicon, introduces misfit dislocations, which are formed as a result of the lattice mismatch between the silicon and germanium atoms and which act as both recombination sites and proximity gettering sites.
- FIGS. 5 - 11 illustrate a method for the fabrication of a partially-depleted SOI substrate 100 (FIG. 11) according to the present invention, in which the floating body effect is suppressed.
- a first silicon substrate 50 is oxidized to thermally grow an insulating layer 52 , for example, a silicon oxide insulating layer 52 .
- the thermal oxidation of the first silicon substrate 50 could take place, for example, in an oxygen (O 2 ) or water (H 2 O) vapor ambient, at temperatures of about 750-1000° C., depending on the desired oxidation rate.
- the silicon oxide insulating layer 52 may be formed, for example, of silicon dioxide (SiO 2 ), up to a thickness of approximately 1 micron. However, as well-known in the art, the thickness of the silicon oxide insulating layer 52 may vary greatly, depending on the processing requirements and desired device characteristics.
- thermally grown insulating layer 52 will be made in this application as to the silicon dioxide layer 52 , it must be understood that the present invention has applicability to other types of thermally grown insulating oxides.
- the present invention is not limited to silicon oxides, and other oxides, such as a oxynitrides and saphire-intermediate oxides grown by chemical vapor deposition (CVD), may be used also in accordance with the characteristics of the particular SOI device.
- CVD chemical vapor deposition
- the present invention is explained with reference to a silicon substrate, such as the first silicon substrate 50 (FIG. 5), it must be understood that the substrate need not be silicon-based.
- the invention has equal applicability to other semiconductor substrates, such as, for example, silicon-germanium, germanium, silicon-on-saphire, or gallium-arsenide substrates.
- a first epitaxial silicon layer 62 is formed according to well-known methods of the art.
- the first epitaxial silicon layer 62 could be formed by a process such as liquid phase epitaxy (LPE), ultra high vacuum (UHV) chemical vapor deposition (CVD), vapor phase epitaxy (VPE), or metal organic vapor phase epitaxy (MOVPE), among others.
- LPE liquid phase epitaxy
- UHV ultra high vacuum
- CVD chemical vapor deposition
- VPE vapor phase epitaxy
- MOVPE metal organic vapor phase epitaxy
- the first epitaxial silicon layer 62 (FIG. 6) is grown by epitaxy in a reaction chamber at high temperatures, of about 900-1200° C., and by employing a silicon gas source that introduces a gaseous species containing silicon (Si) into the reaction chamber.
- the silicon gas source may be silane (SiH 4 ), higher order silanes, such as disilane (Si 2 H 6 ), as well as other gaseous sources of silicon, such as dichlorsilane (SiH 2 Cl 2 ), trichlorsilane (SiHCl 3 ), or tetrachlorsilane (SiCl 4 ).
- the first epitaxial silicon layer 62 is grown over the second silicon substrate 60 to a thickness of about 500-3,000 Angstroms, and preferably of about 1,500 Angstroms.
- a silicon (Si) and germanium (Ge) gas source is next used to introduce a gaseous species containing silicon and germanium in the same reaction chamber, for a further deposition of a thin Si/Ge epitaxial layer 63 , shown in FIG. 7.
- the silicon gas source may be, for example, a silane (SiH 4 ) source or any other silicon gas source employed in the formation of the first epitaxially grown layer 62 (FIG. 6).
- the germanium gas source may be, for example, a germane (GeH 4 ) source, or any other gaseous source containing germanium.
- the combination of the two gaseous sources allows deposition of the thin Si/Ge epitaxial layer 63 (FIG. 7) to a thickness of about 100-300 Angstroms, more preferably of about 200 Angstroms, at a deposition temperature of about 900-1200° C.
- the thin Si/Ge epitaxial layer 63 has a germanium composition of approximately 0.5-6% of the total composition, more preferably of about 2%.
- the thickness of the Si/Ge epitaxial layer 63 is proportional to, and depends upon, the deposition time.
- the presence of the thin Si/Ge epitaxial layer 63 induces misfit dislocations at the interface between the first epitaxial silicon layer 62 and the Si/Ge epitaxial layer 63 .
- These misfit dislocations are the result of a mismatch between the lattice of the crystalline silicon (from the first epitaxial silicon layer 62 ) and the lattice of germanium (from the Si/Ge epitaxial layer 63 ), the germanium atoms being much larger than the silicon ones.
- These dislocations serve as efficient carrier recombination centers for devices, such as transistors later formed on the partially-depleted SOI substrate 100 (FIG. 10).
- the recombination centers allow charge carriers, which typically accumulate near the drain/source region of a transistor and are stored in a floating body, to recombine and be removed.
- misfit dislocations are rather random at the epitaxial silicon and Si/Ge interface.
- concentration can be predicted based on the thickness of the two adjacent layers, the first epitaxial silicon layer 62 and the Si/Ge epitaxial layer 63 , respectively, and upon the germanium concentration in the Si/Ge epitaxial layer 63 .
- persons skilled in the art will be able to predict the number of charge recombination centers and/or proximity sites present in a SOI device based on the germanium concentration in the Si/Ge epitaxial layer 63 (FIG. 7).
- a second epitaxial silicon layer 64 is grown over the thin Si/Ge epitaxial layer 63 , in the same reaction chamber used for the formation of the previous epitaxially grown layers, by shutting off the germanium gaseous source.
- the second epitaxial silicon layer 64 is grown at high temperatures, of about 900-120° C., and by employing same silicon gas source that was used in the previous steps, with respect to the gaseous species containing silicon (Si).
- the thickness of the second epitaxial silicon layer 64 is of about 300-1500 Angstroms, more preferably of about 500 Angstroms.
- Misfit dislocations similar to those present at the interface between the first epitaxial silicon layer 62 and the thin Si/Ge epitaxial layer 63 , also occur at the interface between the thin Si/Ge epitaxial layer 63 and the second epitaxial silicon layer 64 . These misfit dislocations also create additional carrier recombination centers and gettering sites for the partially-depleted SOI substrate 100 .
- the second silicon substrate 60 , the first epitaxial silicon layer 62 , the thin Si/Ge epitaxial layer 63 , together with the second epitaxial silicon layer 64 form a Si/Ge layered structure 66 (FIG. 8), which, as explained above, induces misfit dislocations and allows a predictable number of recombination centers to form at the interfaces between the epitaxial silicon layer 62 , 64 and the Si/Ge epitaxial layer 63 .
- FIG. 9 shows the Si/Ge layered structure 66 being brought into contact with the first silicon substrate 50 , which has the thermally grown silicon dioxide layer 52 formed thereover, so that the second epitaxial silicon layer 64 opposes the thermally grown silicon dioxide layer 52 .
- Processing steps for the fabrication of the partially-depleted SOI substrate 100 are now carried out in accordance with those of the prior art and explained above with reference to FIGS. 2 - 4 .
- the first silicon substrate 50 with the thermally grown silicon dioxide layer 52 , is contacted with the Si/Ge layered structure 66 to form a resultant two-substrate structure 77 (FIG. 10).
- the two-substrates structure 77 is then heated to a temperature of about 900-1200° C., more preferably of about 1000° C., so that the crystalline silicon from the second epitaxial silicon layer 64 adheres and bounds to the silicon dioxide layer 52 .
- the second silicon substrate 60 of the two-substrate structure 77 of FIG. 10 is etched back to form a partially-depleted SOI substrate 100 (FIG. 11) of about 1.5 microns thick.
- the partially-depleted SOI substrate 100 is thus formed of the first silicon substrate 50 , the thermally grown silicon dioxide layer 52 , the second epitaxial silicon layer 64 , the thin Si/Ge epitaxial layer 63 , and the first epitaxial silicon layer 62 .
- the thin Si/Ge epitaxial layer 63 formed between the first and second epitaxial silicon layers 62 , and 64 , respectively, induces the misfit dislocations discussed above into the resulting substrate structure at the interface of layers 62 , 63 and 63 , 64 .
- the partially-depleted SOI substrate 100 (FIG. 11) fabricated in accordance with the present invention may now be used for the fabrication of a MOSFET, for example, an n-p-n type transistor 200 (FIG. 13).
- the first epitaxial silicon layer 62 of the partially-depleted SOI substrate 100 is first implanted with p-type dopant impurity ions, such as boron (B), beryllium (Be) or magnesium (Mg), to form a p-type silicon layer 65 (FIG. 12).
- p-type dopant impurity ions such as boron (B), beryllium (Be) or magnesium (Mg)
- an ion implantation mask (not shown) is formed on the p-type silicon layer 65 , so that the p-type silicon layer 65 undergoes another ion implantation, this time with n-type dopant impurity ions, such as phosphorus (P), arsenic (As), or sulfur (S).
- n-type dopant impurity ions such as phosphorus (P), arsenic (As), or sulfur (S).
- source and drain regions 80 (FIG. 12), which are heavily doped with n-type impurity ions, are formed within the p-type silicon layer 65 .
- a gate stack 90 (FIG. 13) is subsequently formed over the p-type silicon layer 65 , including the already formed source/drain doped regions 80 , by well-known methods of the art.
- the gate stack 90 includes an oxide layer 92 , a conductive layer 94 , such as polysilicon, a nitride cap 96 , and nitride spacers 98 .
- an n-p-n type transistor 200 (FIG. 13) is formed of the gate stack 90 , and the n-type source/drain regions 80 of the p-type silicon layer 65 .
- Transistor 200 may be used as an access transistor in a memory device such as a random access memory device.
- further well-known processing steps to create a functional memory cell containing the partially-depleted SOI substrate 100 (FIG. 11) may now be carried out.
- a typical processor based system 400 which includes a memory circuit 448 , for example a DRAM, containing a partially-depleted SOI substrate according to the present invention is illustrated in FIG. 14.
- a processor system such as a computer system, generally comprises a central processing unit (CPU) 444 , such as a microprocessor, a digital signal processor, or other programmable digital logic devices, which communicates with an input/output (I/O) device 446 over a bus 452 .
- the memory 448 communicates with the system over bus 452 .
- the processor system may include peripheral devices such as a floppy disk drive 454 and a compact disk (CD) ROM drive 456 which also communicate with CPU 444 over the bus 452 .
- Memory 448 is preferably constructed as an integrated circuit, which includes the partially-depleted SOI substrate 100 formed as previously described with respect to FIGS. 5 - 11 .
- the memory 448 may be combined with the processor, e.g. CPU 444 , in a single integrated circuit.
- the invention has been illustrated for a MOSFET device fabricated on a p-type substrate, the invention could also be fabricated on an n-type substrate, as well-known in the art. This, of course, will change the doping or conductivity of the operative layers in the fabricated device.
- the invention has been illustrated for an n-p-n type transistor, such as the n-p-n type transistor 200 (FIG. 13), employing a p-type silicon layer, such as the p-type silicon layer 65 , formed by ion implantation after the formation of the partially-depleted SOI substrate 100 (FIG. 11), it must be understood that the present invention is not limited to this exemplary embodiment. Accordingly, the conductivity doping of the silicon layer 65 (FIGS. 12 - 13 ) could be also conducted during, and not after, the formation of the partially-depleted SOI substrate. For example, after the growth of the first epitaxial silicon layer 62 (FIG. 6) over the second silicon substrate 60 , the first epitaxial silicon layer 62 can be doped with n-type or p-type dopant impurity atoms, to achieve the desired conductivity.
- FIG. 15 a partially-depleted SOI substrate 101 includes two thin Si/Ge layer epitaxial layers 63 , and 65 , respectively, interleaved with three epitaxial silicon layers 62 , 64 , and 66 , respectively.
- the second Si/Ge layer epitaxial layers 65 may be fabricated in the same manner and to the same thickness as that for the formation of the Si/Ge layer epitaxial layers 63 , described above with reference to FIG. 7.
- the third epitaxial silicon layers 66 may be fabricated in a manner similar to that employed for the fabrication of the second epitaxial silicon layer 64 , described above with reference to FIG. 8.
Abstract
A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.
Description
- The present invention relates to the field of semiconductor integrated circuits and, in particular, to partially-depleted Silicon on Insulator (PD-SOI) substrates and devices.
- Silicon on Insulator (SOI) technology employs a layer of semiconductor material formed over an insulating layer on a supporting bulk wafer. The structure can be formed by different well-known techniques in the art, for example, separation by implanted oxygen (SIMOX), bonding and etching back (BESOI), and zone melting and recrystallization (ZMR), among others. Typically, the structure comprises a film of monocrystalline silicon formed on a buried layer of silicon oxide which is formed on a monocrystalline silicon substrate. As such, in many SOI applications, an epitaxial (epi) silicon layer is used as a top silicon layer, which is generally formed by one of two methods: (1) bonding followed by etch back; or (2) epitaxial layer transfer (ELTRAN) process.
- One technique for the formation of a SOI substrate by a conventional bonding and etching back method of the prior art is illustrated in FIGS.1-4. The process starts with the preparation of a silicon substrate 10 (FIG. 1). The
silicon substrate 10 is thermally oxidized to grow a layer of silicon oxide 12 (FIG. 1), with a thickness of about 1 micron. Subsequently, an n-type singlecrystalline silicon substrate 14 is opposed to thesilicon oxide layer 12, as shown in FIG. 2. Thesilicon substrate 10, with theoxide layer 12, is then contacted with thecrystalline silicon substrate 14, and the resultant structure is heated to a temperature of about 1000° C., so that the n-type crystalline silicon of thecrystalline silicon substrate 14 adheres to thesilicon oxide layer 12, as shown in FIG. 3. Next, as illustrated in FIG. 4, the n-typecrystalline silicon substrate 14 is polished and its thickness is decreased to approximately 1.5 microns. Thus, a SOI substrate 15 (FIG. 4) is formed of thesilicon substrate 10, thesilicon oxide layer 12, and the n-typecrystalline silicon substrate 14. - Field effect transistors such as MOSFETs, which are fabricated in the upper silicon layer of a SOI structure, such as the
SOI substrate 15 of FIG. 4, have multiple advantages over the transistors fabricated on the conventional bulk silicon substrates. These advantages include, among others, resistance to short-channel effect, increased current drive, higher packing density, and reduced parasitic capacitance. However, despite all these attractive properties, SOI technology still has some drawbacks, which reduce the benefits of using it for high-performance and high-density ultra large scale integrated (ULSI) circuits. - One drawback of the SOI technology is the conductivity of the top Si layer and its inherent floating body effect, which has particular significance for partially-depleted (PD) or non-fully depleted SOI devices. The floating body effect in such devices occurs as a result of the buried oxide that isolates the channel region of such device and allows charge carriers to build up in the channel region. In a partially-depleted MOSFET, charge carriers (holes in an nMOSFET and electrons in a pMOSFET), generated by impact ionization near the drain/source region, accumulate near the source/drain region of the transistor. When sufficient carriers accumulate, they are stored in the floating body, which is formed right below the channel region, and alter the floating body potential. As a result, kinks in the I/V curve occur, the threshold voltage is lowered, and the overall electrical performance of the device may be severely degraded.
- To diminish the negative effects of the charge build up, so-called “recombination centers” can be introduced into the transistor channel region. According to this technique, damage areas containing implanted ions are placed where the charges accumulate, so that holes and electrons can combine or recombine and accumulated charges removed.
- Another technique for diminishing the negative effects of the charge build up has been to provide an extra electrical connection by adding a contact to the body for hole current collection. However, the currently available hole collection schemes, such as the use of a side-contact, are inefficient, require very complex processing steps, and consume a great amount of device area.
- Accordingly, there is a need for an improved method for forming a partially-depleted SOI device having reduced charge build up and accompanying threshold voltage changes and charge leakage. There is also a need for an integrated process for epi-SOI wafer fabrication, in which recombination centers are created with fewer processing steps and which saves wafer area. A defect-free partially-depleted SOI substrate is also needed.
- The present invention provides a simple method for forming a partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up to mitigate the floating body effect, which can be further used for the fabrication of SOI devices with reduced threshold voltage and leakage.
- The method of the present invention employs a thin Si/Ge epitaxial layer grown between two adjacent epitaxial silicon layers of the partially-depleted SOI substrate. The thin Si/Ge epitaxial layer, grown during the epitaxial growth of silicon, introduces misfit dislocations, which are formed as a result of the lattice mismatch between the silicon and germanium atoms, and which act as both recombination sites and proximity gettering sites. After the growth of the thin Si/Ge epitaxial layer and the formation of the partially-depleted (PD) SOI device, the newly-formed dislocations lie close to the buried oxide and remove the accumulated charges, so that the performance of the partially-depleted (PD) SOI device remains largely unaffected by charge build up.
- The above and other advantages and features of the present invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
- FIG. 1 is a cross-sectional view of a SOI substrate at an initial stage of processing and in accordance with a method of the prior art.
- FIG. 2 is a cross-sectional view of the SOI substrate of FIG. 1 at a stage of processing subsequent to that shown in FIG. 1.
- FIG. 3 is a cross-sectional view of the SOI substrate of FIG. 1 at a stage of processing subsequent to that shown in FIG. 2.
- FIG. 4 is a cross-sectional view of the SOI substrate of FIG. 1 at a stage of processing subsequent to that shown in FIG. 3.
- FIG. 5 is a cross-sectional view of a partially-depleted SOI substrate at an initial stage of processing and in accordance with a first embodiment of the present invention.
- FIG. 6 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 5.
- FIG. 7 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 6.
- FIG. 8 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 7.
- FIG. 9 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 8.
- FIG. 10 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 9.
- FIG. 11 is a cross-sectional view of the partially-depleted SOI substrate of FIG. 5 at a stage of processing subsequent to that shown in FIG. 10.
- FIG. 12 is a cross-sectional view of a portion of a MOSFET having a partially-depleted SOI substrate according to the present invention.
- FIG. 13 is a cross-sectional view of the MOSFET structure of FIG. 12 at a stage of processing subsequent to that shown in FIG. 12.
- FIG. 14 is an illustration of a computer system having a memory cell access transistor constructed on a partially-depleted SOI substrate according to the present invention.
- FIG. 15 a cross-sectional view of a partially-depleted SOI substrate at an initial stage of processing and in accordance with a second embodiment of the present invention.
- In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that various structural, logical, and electrical changes may be made without departing from the spirit or scope of the invention.
- The present invention provides a method for forming a partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and reduced floating body effect. The method of the present invention employs a thin Si/Ge epitaxial layer formed between two adjacent epitaxial silicon layers of a partially-depleted SOI device. The thin Si/Ge epitaxial layer, grown during the epitaxial growth of silicon, introduces misfit dislocations, which are formed as a result of the lattice mismatch between the silicon and germanium atoms and which act as both recombination sites and proximity gettering sites.
- Referring now to the drawings, where like elements are designated by like reference numerals, FIGS.5-11 illustrate a method for the fabrication of a partially-depleted SOI substrate 100 (FIG. 11) according to the present invention, in which the floating body effect is suppressed.
- First, as shown in FIG. 5, a
first silicon substrate 50 is oxidized to thermally grow aninsulating layer 52, for example, a siliconoxide insulating layer 52. The thermal oxidation of thefirst silicon substrate 50 could take place, for example, in an oxygen (O2) or water (H2O) vapor ambient, at temperatures of about 750-1000° C., depending on the desired oxidation rate. The siliconoxide insulating layer 52 may be formed, for example, of silicon dioxide (SiO2), up to a thickness of approximately 1 micron. However, as well-known in the art, the thickness of the siliconoxide insulating layer 52 may vary greatly, depending on the processing requirements and desired device characteristics. - Although reference to the thermally grown
insulating layer 52 will be made in this application as to thesilicon dioxide layer 52, it must be understood that the present invention has applicability to other types of thermally grown insulating oxides. Thus, the present invention is not limited to silicon oxides, and other oxides, such as a oxynitrides and saphire-intermediate oxides grown by chemical vapor deposition (CVD), may be used also in accordance with the characteristics of the particular SOI device. - Similarly, although the present invention is explained with reference to a silicon substrate, such as the first silicon substrate50 (FIG. 5), it must be understood that the substrate need not be silicon-based. Thus, the invention has equal applicability to other semiconductor substrates, such as, for example, silicon-germanium, germanium, silicon-on-saphire, or gallium-arsenide substrates.
- Referring now to FIG. 6, on a
second silicon substrate 60, a firstepitaxial silicon layer 62 is formed according to well-known methods of the art. The firstepitaxial silicon layer 62 could be formed by a process such as liquid phase epitaxy (LPE), ultra high vacuum (UHV) chemical vapor deposition (CVD), vapor phase epitaxy (VPE), or metal organic vapor phase epitaxy (MOVPE), among others. - In an exemplary embodiment of the present invention, the first epitaxial silicon layer62 (FIG. 6) is grown by epitaxy in a reaction chamber at high temperatures, of about 900-1200° C., and by employing a silicon gas source that introduces a gaseous species containing silicon (Si) into the reaction chamber. As known in the art, the silicon gas source may be silane (SiH4), higher order silanes, such as disilane (Si2H6), as well as other gaseous sources of silicon, such as dichlorsilane (SiH2Cl2), trichlorsilane (SiHCl3), or tetrachlorsilane (SiCl4). In any event, the first
epitaxial silicon layer 62 is grown over thesecond silicon substrate 60 to a thickness of about 500-3,000 Angstroms, and preferably of about 1,500 Angstroms. - Once the growth of the first
epitaxial silicon layer 62 is completed, and while thesecond silicon substrate 60 is still in the reaction chamber, a silicon (Si) and germanium (Ge) gas source is next used to introduce a gaseous species containing silicon and germanium in the same reaction chamber, for a further deposition of a thin Si/Ge epitaxial layer 63, shown in FIG. 7. - The silicon gas source may be, for example, a silane (SiH4) source or any other silicon gas source employed in the formation of the first epitaxially grown layer 62 (FIG. 6). The germanium gas source may be, for example, a germane (GeH4) source, or any other gaseous source containing germanium. The combination of the two gaseous sources allows deposition of the thin Si/Ge epitaxial layer 63 (FIG. 7) to a thickness of about 100-300 Angstroms, more preferably of about 200 Angstroms, at a deposition temperature of about 900-1200° C.
- The thin Si/
Ge epitaxial layer 63 has a germanium composition of approximately 0.5-6% of the total composition, more preferably of about 2%. The thickness of the Si/Ge epitaxial layer 63 is proportional to, and depends upon, the deposition time. - The presence of the thin Si/Ge epitaxial layer63 (FIG. 7) induces misfit dislocations at the interface between the first
epitaxial silicon layer 62 and the Si/Ge epitaxial layer 63. These misfit dislocations are the result of a mismatch between the lattice of the crystalline silicon (from the first epitaxial silicon layer 62) and the lattice of germanium (from the Si/Ge epitaxial layer 63), the germanium atoms being much larger than the silicon ones. These dislocations serve as efficient carrier recombination centers for devices, such as transistors later formed on the partially-depleted SOI substrate 100 (FIG. 10). The recombination centers allow charge carriers, which typically accumulate near the drain/source region of a transistor and are stored in a floating body, to recombine and be removed. - These misfit dislocations are rather random at the epitaxial silicon and Si/Ge interface. However, their concentration can be predicted based on the thickness of the two adjacent layers, the first
epitaxial silicon layer 62 and the Si/Ge epitaxial layer 63, respectively, and upon the germanium concentration in the Si/Ge epitaxial layer 63. Thus, persons skilled in the art will be able to predict the number of charge recombination centers and/or proximity sites present in a SOI device based on the germanium concentration in the Si/Ge epitaxial layer 63 (FIG. 7). - Reference is now made to FIG. 8. After the growth of the thin Si/
Ge epitaxial layer 63, a secondepitaxial silicon layer 64 is grown over the thin Si/Ge epitaxial layer 63, in the same reaction chamber used for the formation of the previous epitaxially grown layers, by shutting off the germanium gaseous source. Thus, the secondepitaxial silicon layer 64 is grown at high temperatures, of about 900-120° C., and by employing same silicon gas source that was used in the previous steps, with respect to the gaseous species containing silicon (Si). The thickness of the secondepitaxial silicon layer 64 is of about 300-1500 Angstroms, more preferably of about 500 Angstroms. - Misfit dislocations, similar to those present at the interface between the first
epitaxial silicon layer 62 and the thin Si/Ge epitaxial layer 63, also occur at the interface between the thin Si/Ge epitaxial layer 63 and the secondepitaxial silicon layer 64. These misfit dislocations also create additional carrier recombination centers and gettering sites for the partially-depletedSOI substrate 100. - The
second silicon substrate 60, the firstepitaxial silicon layer 62, the thin Si/Ge epitaxial layer 63, together with the secondepitaxial silicon layer 64 form a Si/Ge layered structure 66 (FIG. 8), which, as explained above, induces misfit dislocations and allows a predictable number of recombination centers to form at the interfaces between theepitaxial silicon layer Ge epitaxial layer 63. - Reference is now made to FIG. 9, which shows the Si/Ge layered
structure 66 being brought into contact with thefirst silicon substrate 50, which has the thermally grownsilicon dioxide layer 52 formed thereover, so that the secondepitaxial silicon layer 64 opposes the thermally grownsilicon dioxide layer 52. Processing steps for the fabrication of the partially-depleted SOI substrate 100 (FIG. 11) are now carried out in accordance with those of the prior art and explained above with reference to FIGS. 2-4. - Thus, referring now to FIG. 10, the
first silicon substrate 50, with the thermally grownsilicon dioxide layer 52, is contacted with the Si/Ge layeredstructure 66 to form a resultant two-substrate structure 77 (FIG. 10). The two-substrates structure 77 is then heated to a temperature of about 900-1200° C., more preferably of about 1000° C., so that the crystalline silicon from the secondepitaxial silicon layer 64 adheres and bounds to thesilicon dioxide layer 52. - Next, the
second silicon substrate 60 of the two-substrate structure 77 of FIG. 10 is etched back to form a partially-depleted SOI substrate 100 (FIG. 11) of about 1.5 microns thick. The partially-depletedSOI substrate 100 is thus formed of thefirst silicon substrate 50, the thermally grownsilicon dioxide layer 52, the secondepitaxial silicon layer 64, the thin Si/Ge epitaxial layer 63, and the firstepitaxial silicon layer 62. The thin Si/Ge epitaxial layer 63, formed between the first and second epitaxial silicon layers 62, and 64, respectively, induces the misfit dislocations discussed above into the resulting substrate structure at the interface oflayers - The partially-depleted SOI substrate100 (FIG. 11) fabricated in accordance with the present invention may now be used for the fabrication of a MOSFET, for example, an n-p-n type transistor 200 (FIG. 13). For this, the first
epitaxial silicon layer 62 of the partially-depletedSOI substrate 100 is first implanted with p-type dopant impurity ions, such as boron (B), beryllium (Be) or magnesium (Mg), to form a p-type silicon layer 65 (FIG. 12). Subsequently, an ion implantation mask (not shown) is formed on the p-type silicon layer 65, so that the p-type silicon layer 65 undergoes another ion implantation, this time with n-type dopant impurity ions, such as phosphorus (P), arsenic (As), or sulfur (S). This way, source and drain regions 80 (FIG. 12), which are heavily doped with n-type impurity ions, are formed within the p-type silicon layer 65. - A gate stack90 (FIG. 13) is subsequently formed over the p-
type silicon layer 65, including the already formed source/drain dopedregions 80, by well-known methods of the art. Thegate stack 90 includes anoxide layer 92, aconductive layer 94, such as polysilicon, anitride cap 96, andnitride spacers 98. Thus, an n-p-n type transistor 200 (FIG. 13) is formed of thegate stack 90, and the n-type source/drain regions 80 of the p-type silicon layer 65.Transistor 200 may be used as an access transistor in a memory device such as a random access memory device. To this end, further well-known processing steps to create a functional memory cell containing the partially-depleted SOI substrate 100 (FIG. 11) may now be carried out. - A typical processor based
system 400 which includes amemory circuit 448, for example a DRAM, containing a partially-depleted SOI substrate according to the present invention is illustrated in FIG. 14. A processor system, such as a computer system, generally comprises a central processing unit (CPU) 444, such as a microprocessor, a digital signal processor, or other programmable digital logic devices, which communicates with an input/output (I/O) device 446 over abus 452. Thememory 448 communicates with the system overbus 452. - In the case of a computer system, the processor system may include peripheral devices such as a
floppy disk drive 454 and a compact disk (CD)ROM drive 456 which also communicate withCPU 444 over thebus 452.Memory 448 is preferably constructed as an integrated circuit, which includes the partially-depletedSOI substrate 100 formed as previously described with respect to FIGS. 5-11. Thememory 448 may be combined with the processor,e.g. CPU 444, in a single integrated circuit. - Although the invention has been illustrated for a MOSFET device fabricated on a p-type substrate, the invention could also be fabricated on an n-type substrate, as well-known in the art. This, of course, will change the doping or conductivity of the operative layers in the fabricated device.
- Similarly, although the invention has been illustrated for an n-p-n type transistor, such as the n-p-n type transistor200 (FIG. 13), employing a p-type silicon layer, such as the p-
type silicon layer 65, formed by ion implantation after the formation of the partially-depleted SOI substrate 100 (FIG. 11), it must be understood that the present invention is not limited to this exemplary embodiment. Accordingly, the conductivity doping of the silicon layer 65 (FIGS. 12-13) could be also conducted during, and not after, the formation of the partially-depleted SOI substrate. For example, after the growth of the first epitaxial silicon layer 62 (FIG. 6) over thesecond silicon substrate 60, the firstepitaxial silicon layer 62 can be doped with n-type or p-type dopant impurity atoms, to achieve the desired conductivity. - Although the present invention has been described for a partially-depleted SOI substrate100 (FIGS. 5-11) with a thin Si/Ge layer epitaxial layer formed by a bonding and etching back method, it must be understood that the present invention is not limited to the above fabrication method. Accordingly, other methods known in the art, for example, the ELTRAN process, may be also used, as long as a thin Si/Ge layer epitaxial layer is formed between two epitaxial layers of silicon.
- Further, although the exemplary embodiment of the present invention has been described for a partially-depleted SOI substrate100 (FIGS. 5-11) with only one thin Si/Ge
layer epitaxial layer 63, it must be understood that the present invention is not limited to the above-described exemplary embodiment and a plurality of thin Si/Ge layer epitaxial layers may be interleaved with epitaxial silicon layers to create a plurality of misfit dislocation regions. For example, one such embodiment is illustrated in FIG. 15, in which a partially-depletedSOI substrate 101 includes two thin Si/Ge layer epitaxial layers 63, and 65, respectively, interleaved with three epitaxial silicon layers 62, 64, and 66, respectively. This way, misfit dislocation regions are created in the partially-depletedSOI substrate 101 at the interface oflayers epitaxial silicon layer 64, described above with reference to FIG. 8. - The above description illustrates preferred embodiments that achieve the features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Modifications and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.
Claims (93)
1. A SOI structure comprising:
a silicon/germanium layer formed between a first silicon layer and a second silicon layer, said silicon/germanium layer being in contact with said first and second silicon layers; and
an oxide layer formed over a semiconductor substrate, said oxide layer being in contact with said second silicon layer.
2. The SOI structure of , wherein said silicon/germanium layer is an epitaxial silicon/germanium layer.
claim 1
3. The SOI structure of , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.
claim 1
4. The SOI structure of , wherein said silicon/germanium layer is approximately 200 Angstroms thick.
claim 1
5. The SOI structure of , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.
claim 1
6. The SOI structure of , wherein said silicon/germanium layer comprises approximately 5% germanium.
claim 1
7. The SOI structure of , wherein said first silicon layer is an epitaxial silicon layer.
claim 1
8. The SOI structure of , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.
claim 7
9. The SOI structure of , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick.
claim 7
10. The SOI structure of , wherein said second silicon layer is an epitaxial silicon layer.
claim 1
11. The SOI structure of , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.
claim 10
12. The SOI structure of , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick.
claim 10
13. The SOI structure of , wherein said oxide layer is approximately 1 micron thick.
claim 1
14. The SOI structure of , wherein said semiconductor substrate is a silicon substrate.
claim 1
15. The SOI structure of , wherein said semiconductor substrate is a silicon-on-saphire substrate.
claim 1
16. The SOI structure of wherein said semiconductor substrate is a germanium substrate.
claim 1
17. The SOI structure of , wherein said semiconductor substrate is a gallium-arsenide substrate.
claim 1
18. The SOI structure of , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.
claim 1
19. The SOI structure of , wherein said oxide layer is formed of silicon dioxide.
claim 16
20. A method for forming a SOI structure, comprising the steps of:
forming an oxide layer over a first semiconductor substrate;
forming a first silicon layer over a second silicon substrate;
forming a silicon/germanium layer over said first silicon layer;
forming a second silicon layer over said silicon/germanium layer; and
bonding said second silicon layer to said oxide layer.
21. The method of , wherein said silicon/germanium layer is grown epitaxially over said first silicon layer.
claim 20
22. The method of , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.
claim 20
23. The method of , wherein said silicon/germanium layer is approximately 200 Angstroms thick.
claim 20
24. The method of , wherein said silicon/germanium layer comprises approximately 0.5 to 6% of germanium.
claim 20
25. The method of , wherein said silicon/germanium layer comprises approximately 5% of germanium.
claim 20
26. The method of , wherein said first silicon layer is an epitaxial silicon layer.
claim 20
27. The method of , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.
claim 26
28. The method of , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick.
claim 26
29. The method of , wherein said second silicon layer is an epitaxial silicon layer.
claim 20
30. The method of , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.
claim 29
31. The method of , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick.
claim 29
32. The method of further including the step of etching back said second silicon substrate after said step of bonding said second silicon layer to said oxide layer.
claim 20
33. The method of , wherein said step of forming said oxide layer over said first semiconductor substrate further comprises thermally oxidizing said first semiconductor substrate.
claim 20
34. A memory cell, comprising:
a SOI substrate comprising a silicon/germanium layer formed between a first silicon layer and a second silicon layer, and an oxide layer bonded to said second silicon layer, said oxide layer being formed on a semiconductor substrate; and
a transistor including a gate fabricated on said SOI substrate and including source and drain regions fabricated adjacent to said gate.
35. The memory cell of , wherein said silicon/germanium layer is an epitaxial silicon/germanium layer.
claim 34
36. The memory cell of , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.
claim 34
37. The memory cell of , wherein said silicon/germanium layer is approximately 200 Angstroms thick.
claim 34
38. The memory cell of , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.
claim 34
39. The memory cell of , wherein said silicon/germanium layer comprises approximately 5% germanium.
claim 34
40. The memory cell of , wherein said first silicon layer is an epitaxial silicon layer.
claim 34
41. The memory cell of , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.
claim 40
42. The memory cell of , wherein said first epitaxial silicon layer is approximately 1,500 Angstroms thick.
claim 40
43. The memory cell of , wherein said second silicon layer is an epitaxial silicon layer.
claim 34
44. The memory cell of , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.
claim 43
45. The memory cell of , wherein said second epitaxial silicon layer is approximately 500 Angstroms thick.
claim 43
46. The memory cell of , wherein said oxide layer is approximately 1micron thick.
claim 34
47. The memory cell of , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.
claim 34
48. A processor system comprising:
a processor; and
an integrated circuit coupled to said processor and comprising a SOI substrate, said SOI substrate comprising a silicon/germanium layer formed between a first epitaxial silicon layer and a second epitaxial silicon layer, and an oxide layer bonded to said second epitaxial silicon layer, said oxide layer being formed on a semiconductor substrate.
49. The processor system of , wherein said silicon/germanium layer is an epitaxially grown layer.
claim 48
50. The processor system of , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.
claim 48
51. The processor system of , wherein said silicon/germanium layer is approximately 200 Angstroms thick.
claim 48
52. The processor system of , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.
claim 48
53. The processor system of , wherein said silicon/germanium layer comprises approximately 5% germanium.
claim 48
54. The processor system of , wherein said first epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.
claim 48
55. The processor system of , wherein said second epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.
claim 48
56. The processor system of , wherein said oxide layer is approximately 1micron thick.
claim 48
57. The processor system of , wherein said semiconductor substrate is a silicon substrate.
claim 48
58. The processor system of , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.
claim 48
59. The processor system of , wherein said integrated circuit is a memory device.
claim 48
60. The processor system of , wherein said memory device is a random access memory device.
claim 59
61. A SOI substrate comprising:
a first silicon substrate, said first silicon substrate having at least one layer of misfit dislocation regions formed therein at an intermediate location relative to first and second silicon surfaces of said substrate; and
an oxide layer formed over a second silicon substrate, said oxide layer being bonded to one of said first and second silicon surfaces of said first silicon substrate.
62. The SOI substrate of , wherein said misfit dislocation regions are formed at an interface of two material layers which have different crystalline properties.
claim 61
63. The SOI substrate of , wherein said two material layers are a first silicon layer and a silicon/germanium layer.
claim 62
64. The SOI substrate of , wherein said silicon/germanium layer is approximately 100 to 300 Angstroms thick.
claim 63
65. The SOI substrate of , wherein said silicon/germanium layer is approximately 200 Angstroms thick.
claim 63
66. The SOI substrate of , wherein said silicon/germanium layer comprises approximately 0.5 to 6% germanium.
claim 63
67. The SOI substrate of , wherein said silicon/germanium layer comprises approximately 5% germanium.
claim 63
68. The SOI substrate of , wherein said first silicon layer is a first epitaxial silicon layer.
claim 63
69. The SOI substrate of , wherein said first epitaxial silicon layer is approximately 300 to 1,500 Angstroms thick.
claim 68
70. The SOI substrate of , wherein said first epitaxial silicon layer is approximately 500 Angstroms thick.
claim 68
71. The SOI substrate of further comprising a second misfit dislocation region between said silicon/germanium layer and a second silicon layer, said silicon/germanium layer being in contact with said first silicon layer and said second silicon layer.
claim 63
72. The SOI substrate of , wherein said second silicon layer is a second epitaxial silicon layer.
claim 71
73. The SOI substrate of , wherein said second epitaxial silicon layer is approximately 500 to 3,000 Angstroms thick.
claim 72
74. The SOI substrate of , wherein said second epitaxial silicon layer is approximately 1,500 Angstroms thick.
claim 72
75. The SOI substrate of , wherein said oxide layer is approximately 1micron thick.
claim 61
76. The SOI substrate of , wherein said semiconductor substrate is a silicon substrate.
claim 61
77. The SOI substrate of , wherein said semiconductor substrate is a silicon-on-saphire substrate.
claim 61
78. The SOI substrate of , wherein said semiconductor substrate is a germanium substrate.
claim 61
79. The SOI substrate of , wherein said semiconductor substrate is a gallium-arsenide substrate.
claim 61
80. The SOI substrate of , wherein said oxide layer is formed of a material selected from the group consisting of silicon oxides, oxynitrides, and saphire-intermediate oxides.
claim 61
81. A SOI structure comprising:
a first silicon/germanium layer formed between a first silicon layer and a second silicon layer, said first silicon/germanium layer being in contact with said first and second silicon layers;
a second silicon/germanium layer formed between a third silicon layer and said second silicon layer, said second silicon/germanium layer being in contact with said second and third silicon layers; and
an oxide layer formed over a semiconductor substrate, said oxide layer being in contact with said third silicon layer.
82. The SOI structure of , wherein said first and second silicon/germanium layers are epitaxially grown layers.
claim 81
83. The SOI structure of , wherein said first and second silicon/germanium layers are approximately 100 to 300 Angstroms thick.
claim 81
84. The SOI structure of , wherein said first and second silicon/germanium layers are approximately 200 Angstroms thick.
claim 81
85. The SOI structure of , wherein said first and second silicon/germanium layers comprise approximately 0.5 to 6% germanium.
claim 81
86. The SOI structure of , wherein said first and second silicon/germanium layers comprise approximately 5% germanium.
claim 81
87. The SOI structure of , wherein said first silicon layer is an epitaxial silicon layer.
claim 81
88. The SOI structure of , wherein said first silicon layer is approximately 500 to 3,000 Angstroms thick.
claim 81
89. The SOI structure of , wherein said second silicon layer is an epitaxial silicon layer.
claim 81
90. The SOI structure of , wherein said second silicon layer is approximately 300 to 1,500 Angstroms thick.
claim 81
91. The SOI structure of , wherein said third silicon layer is an epitaxial silicon layer.
claim 81
92. The SOI structure of , wherein said third silicon layer is approximately 300 to 1,500 Angstroms thick.
claim 81
93. The SOI structure of , wherein said oxide layer is approximately 1micron thick.
claim 81
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US09/930,451 US20010052621A1 (en) | 2000-06-05 | 2001-08-16 | PD-SOI substrate with suppressed floating body effect and method for its fabrication |
US10/443,023 US6746937B2 (en) | 2000-06-05 | 2003-05-22 | PD-SOI substrate with suppressed floating body effect and method for its fabrication |
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US09/587,190 US6437375B1 (en) | 2000-06-05 | 2000-06-05 | PD-SOI substrate with suppressed floating body effect and method for its fabrication |
US09/930,451 US20010052621A1 (en) | 2000-06-05 | 2001-08-16 | PD-SOI substrate with suppressed floating body effect and method for its fabrication |
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US09/930,451 Abandoned US20010052621A1 (en) | 2000-06-05 | 2001-08-16 | PD-SOI substrate with suppressed floating body effect and method for its fabrication |
US10/443,023 Expired - Lifetime US6746937B2 (en) | 2000-06-05 | 2003-05-22 | PD-SOI substrate with suppressed floating body effect and method for its fabrication |
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Also Published As
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US6746937B2 (en) | 2004-06-08 |
US20030203593A1 (en) | 2003-10-30 |
US6437375B1 (en) | 2002-08-20 |
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