US20020000871A1 - Trimmable reference generator - Google Patents
Trimmable reference generator Download PDFInfo
- Publication number
- US20020000871A1 US20020000871A1 US09/408,789 US40878999A US2002000871A1 US 20020000871 A1 US20020000871 A1 US 20020000871A1 US 40878999 A US40878999 A US 40878999A US 2002000871 A1 US2002000871 A1 US 2002000871A1
- Authority
- US
- United States
- Prior art keywords
- capacitor
- voltage
- programmed
- reference voltage
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
- H03K4/023—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform by repetitive charge or discharge of a capacitor, analogue generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Abstract
Description
- 1. Field of the Invention
- This invention relates to the field of electronic devices, and in particular to voltage generators for memory devices.
- 2. Description of Related Art
- The reliability, or longevity, of a semiconductor memory device has been found to be related to the stress imposed on the device by rapid voltage transitions, particularly rapid high voltage transitions used to write or erase the memory contents.
- Electrically erasable (EE) memory devices are particularly well suited for techniques that control the application of stress-inducing voltage transitions in order to improve the longevity of the device. Typically, EE devices are used as programmable read-only memories, wherein the EE device is relatively infrequently programmed to contain a data set that is frequently read. Because the programming is relatively infrequent, the speed at which the programming occurs is not as critical as other parameters of the design, and in particular, less critical than the longevity of the device.
- FIG. 1 illustrates an
example voltage generator 100 commonly used for programming and erasing an electrically erasable memory device. Thegenerator 100 is designed to provide anoutput voltage 165 that increases from zero volts to a high voltage reference voltage at a controlled rate. The value of the high voltage reference, typically in the 10 to 12 volt range, is determined by fabricating and testing samples of the device to determine an optimal value, based on process parameters and other factors. Areference voltage Vref 115 is provided for controlling the peak value of theoutput voltage 165, typically from a band-gap voltage source, common in the art. Thecontroller 190 effects a charge transfer from the source of thereference voltage 115 to acomparator 150, viaswitches S1 110 andS2 120, andcapacitors C1 130 andC2 140, using techniques common in the art. Thecontroller 190 asserts switch control Sa 101 to effect a charging ofcapacitor C1 130 to thereference voltage 115, while de-assertingswitch control Sb 102 to isolatecapacitor C1 130 fromC2 140. Thereafter, thecontroller 190 de-asserts switch control Sa 101 and assertsswitch control Sb 102, thereby isolatingcapacitor C1 130 from thereference voltage Vref 115, and coupling thecapacitors C1 130 andC2 140 together. If the voltage ofcapacitor C2 140 at the time of coupling tocapacitor C1 130 is less than the voltage on the capacitor C1 130 (which, at the time of coupling, is equal to the reference voltage 115),capacitor C1 130 transfers charge tocapacitor C2 140, thereby raising the voltage level ofcapacitor C2 140. The ratio of the capacitance ofcapacitor C1 130 andcapacitor C2 140, and the difference in voltage between thecapacitors voltage Vramp 145 on thecapacitor C2 140 increases asymptotically to thevoltage reference 115, the rate of increase being determined by the ratio of the capacitance of thecapacitors - A voltage controlled high-
voltage source 160 provides the high-voltage output 165. Thecontrol voltage 155 that controls the high-voltage source 160 is provided by a closed-loop feedback system comprising ascaler 170 and thecomparator 150. Thescaler 170 scales the high-voltage output 165 by a factor S, and this scaledvoltage 175 is compared to theaforementioned voltage Vramp 145. Thefeedback control signal 155 controls the high-voltage output 165 to track theVramp 145 signal, at the scale factor S. That is, if the scale factor S is 5/8, the high-voltage output 165 is 8/5 *Vramp 145. Because Vramp 145 increases toVref 115, the high-voltage output 165 increases to 8/5 *Vref 115. After providing the increasing high-voltage output 165 to the device that utilizes this voltage source, such as an EE memory device, thecontroller 190closes switch SO 180 to deplete the charge on capacitor C2 and reduce its voltage to zero, thereby reducing theoutput voltage 165 to zero. The above process is repeated as required, whenever the increasingoutput voltage 165 is required. - As mentioned above, the peak of the high-
voltage output 165 is preferably trimmed to optimize the longevity of the device that receives this high-voltage output 165. This trim is effected by modifying the scale factor S, typically by physically modifying the devices that form thescaler 170. For example, aconventional scaler 170 is a capacitor divider circuit, and the trimming of the scaler is effected by increasing or decreasing the plate area of one or more of the capacitors forming thescaler 170. This typically requires a change to at least one of the metal masks used to fabricate the device, and cannot be economically applied to customize the high-voltage output 165 ofindividual voltage generators 100. - It is an object of this invention to provide a high-voltage generator that can be trimmed without a mask change. It is a further object of this invention to provide a voltage generator that can be individually trimmed after fabrication. It is a further object of this invention to provide a high-voltage generator that can be optimized for writing and erasing electrically erasable programmable devices.
- These objects, and others, are achieved by providing a programmable reference voltage that is used for controlling a high-voltage source. A programmable voltage divider is used to scale a fixed reference voltage to a scaled reference value that is used to control the generation of a high voltage source. A comparator provides a feedback signal that is based on a difference between the scaled reference voltage and a scaled output voltage. This feedback signal controls the voltage-controlled output voltage source, so as to track the scaled reference value. In a preferred embodiment, the scale factor associated with the output voltage remains constant, whereas the scale factor associated with the reference voltage is programmable. In alternative embodiments of this invention, the reference scaling factor defaults to a mid-range value, and a bias offset is provided to easily select an output voltage value for either programming or erasing the contents of a programmable memory device.
- The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein:
- FIG. 1 illustrates an example prior art high-voltage reference generator.
- FIG. 2 illustrates an example high-voltage reference generator in accordance with this invention.
- FIG. 3 illustrates an example timing diagram of a high-voltage reference generator in accordance with this invention.
- FIG. 4 illustrates an example embodiment of a circuit that provides the programmable voltage reference in accordance with this invention.
- Throughout the drawings, the same reference numeral indicates a similar or corresponding feature or function.
- FIG. 2 illustrates an example high-
voltage reference generator 200 in accordance with this invention. As in theprior art generator 100 of FIG. 1, the high-voltage reference generator 200 includes acomparator 150, a voltage controlledhigh voltage source 160, and scaler 170 to effect a feedback circuit that controls theoutput voltage 265 to a scaled value of thealternative input 245 of thecomparator 150. As compared to theprior art generator 100, thegenerator 200 provides a programmable scaledvalue 245 of thereference voltage 115 as thealternative input 245 to thecomparator 150. Thus, thefeedback signal 255 that controls thevoltage source 160 is based on the difference between the scaledvalue 175 of theoutput voltage 265 and a programmed scaledvalue 245 of thefixed reference voltage 115. - A voltage divider network comprising C1 130,
C2 140, andC3 240 provides theprogrammable reference voltage 245 in a preferred embodiment. The capacitance ofcapacitor C3 240 is variable, preferably by program command, as will be detailed below. In operation, acontroller 290 asserts control signals Sa 201 and Sa′ 201′ to place charge ontocapacitor C1 130, and simultaneously remove charge fromcapacitor C3 240. The charge is placed on thecapacitor C1 130 from thereference voltage Vref 115, viaswitch S1 110, and the charge is removed from thecapacitor C3 240 to aground reference 241, viaswitch S4 210. Thereafter, thecontroller 290 de-asserts control signals Sa 201 and Sa′ 201′, and assertscontrol signals Sb 202 and Sb′ 202′, and the charge oncapacitor C1 130 is shared among thecapacitors C2 140 andC3 240, viaswitches S2 120 andS3 220. Thus, as compared to theconventional generator 100 of FIG. 1, thecapacitor C2 140 receives a smaller proportion of the charge fromcapacitor C1 130, the smaller proportion being determined by the relative size ofcapacitor C3 240 compared tocapacitor C1 130. Repeated cycles of alternating assertions and de-assertions of the control signals Sa 201, Sa′ 201′ andSb 202, Sb′ 202′ add repeated charge tocapacitor C2 140, while repeatedly depleting a portion of the charge viacapacitor C3 240. The steady state voltage on thecapacitor C2 140 is proportional to thereference voltage 115, the proportion being determined by the ratio of the capacitance ofC1 130 to the total capacitance ofC1 130 andC3 240. To deplete the charge on capacitor C2 and return itsvoltage 245, and corresponding, theoutput voltage 265, to zero, thecontroller 290 asserts control signals Sa′ 201′ and Sb′ 202′ simultaneously, whileSb 202 is de-asserted. - FIG. 3 illustrates an example timing diagram for the resultant
ramp voltage Vramp 245 as a function of the capacitance C3. Illustrated in FIG. 3 are five voltages Vv, Vw, Vx, Vy, and Vz corresponding to five values ofC3 240, from a low value through increasingly higher values, respectively. As in theprior art device 100, thevoltage output 265 is a scaled, typically higher, value of theramp voltage Vramp 245 at the alternative input of thecomparator 150, via the operation of the controlledvoltage source 160 andscaler 170, as detailed above. - FIG. 4 illustrates an example block diagram of a voltage divider network with a
programmable capacitor C3 240 that comprisesselectable capacitors switches memory elements programmable capacitor C3 240 are common in the art. In a preferred embodiment of this invention, thecapacitors Capacitor 242 is half the capacitance ofcapacitor 241;capacitor 243 is half the capacitance ofcapacitor 242; and so on. In this manner,N capacitors memory element 431 is configured to selectcapacitor 241 in opposition to the sense of theother memory elements reference voltage 245 corresponds to a nominal target value, so that an adjustment of thecapacitance 240 effects an increase or decrease relative to this nominal target value. For example, in FIG. 3, the programmed reference value Vx is the nominal target value, about which alternative higher Vv, Vw and lower Vy, Vz voltages can be selected, via a selection of theappropriate capacitors scaler 170 of FIG. 2 is determined based on this nominal voltage Vx and the corresponding desired nominal voltage level at theoutput voltage 265. Any number of means, common in the art, can be used to determine the appropriate component values corresponding to the desired nominal value for theoutput voltage 265. The subsequent selection ofalternative capacitors generator 200 that contains theprogrammable capacitor C3 240. - The foregoing merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are thus within its spirit and scope. For example, the controls for the
switches memory elements particular capacitors specific capacitor capacitor C3 240. Selectively connecting or disconnecting such a capacitor effects a voltage level change in theoutput voltage 265, as discussed above. In like manner, the programmedreference voltage 245 need not be a highlyaccurate reference voltage 115, for applications in which the programmedreference voltage 245 is customized for each device. In these applications, thecapacitor 240 is trimmed to also compensate for any inaccuracies in thereference voltage 115. These and other system configuration and optimization features will be evident to one of ordinary skill in the art in view of this disclosure, and are included within the scope of the following claims.
Claims (17)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/408,789 US6448845B2 (en) | 1999-09-30 | 1999-09-30 | Trimmable reference generator |
PCT/EP2000/009410 WO2001024191A1 (en) | 1999-09-30 | 2000-09-25 | Trimmable reference generator |
DE60045278T DE60045278D1 (en) | 1999-09-30 | 2000-09-25 | ADJUSTABLE REFERENCE GENERATOR |
JP2001527291A JP2003510756A (en) | 1999-09-30 | 2000-09-25 | Trimmable reference generator |
EP00967795A EP1149383B1 (en) | 1999-09-30 | 2000-09-25 | Trimmable reference generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/408,789 US6448845B2 (en) | 1999-09-30 | 1999-09-30 | Trimmable reference generator |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020000871A1 true US20020000871A1 (en) | 2002-01-03 |
US6448845B2 US6448845B2 (en) | 2002-09-10 |
Family
ID=23617776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/408,789 Expired - Fee Related US6448845B2 (en) | 1999-09-30 | 1999-09-30 | Trimmable reference generator |
Country Status (5)
Country | Link |
---|---|
US (1) | US6448845B2 (en) |
EP (1) | EP1149383B1 (en) |
JP (1) | JP2003510756A (en) |
DE (1) | DE60045278D1 (en) |
WO (1) | WO2001024191A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020168952A1 (en) * | 2001-01-12 | 2002-11-14 | Vishakhadatta G. Diwakar | Apparatus and methods for calibrating signal-processing circuitry |
EP1566723A1 (en) * | 2004-02-20 | 2005-08-24 | STMicroelectronics S.r.l. | A power management unit for a flash memory with single regulation of multiple charge pumps |
US20140229667A1 (en) * | 1999-10-19 | 2014-08-14 | Rambus Inc. | Memory System with Calibrated Data Communication |
US20150042366A1 (en) * | 2009-10-30 | 2015-02-12 | Deka Products Limited Partnership | Apparatus and method for detecting disconnection of an intravascular access device |
US20180268589A1 (en) * | 2017-03-16 | 2018-09-20 | Linden Research, Inc. | Virtual reality presentation of body postures of avatars |
US11033671B2 (en) | 2011-05-24 | 2021-06-15 | Deka Products Limited Partnership | Systems and methods for detecting vascular access disconnection |
US11145368B2 (en) * | 2020-01-06 | 2021-10-12 | Microchip Technology Incorporated | Method and system for reliable and secure memory erase |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030184314A1 (en) * | 2002-03-26 | 2003-10-02 | Ilan Barak | Apparatus and method of providing output voltage |
US7952937B2 (en) | 2006-03-16 | 2011-05-31 | Freescale Semiconductor, Inc. | Wordline driver for a non-volatile memory device, a non-volatile memory device and method |
WO2007104337A1 (en) | 2006-03-16 | 2007-09-20 | Freescale Semiconductor, Inc. | Bitline current generator for a non-volatile memory array and a non-volatile memory array |
US7948803B2 (en) | 2006-03-16 | 2011-05-24 | Freescale Semiconductor, Inc. | Non-volatile memory device and a programmable voltage reference for a non-volatile memory device |
US10345348B2 (en) | 2014-11-04 | 2019-07-09 | Stmicroelectronics S.R.L. | Detection circuit for an active discharge circuit of an X-capacitor, related active discharge circuit, integrated circuit and method |
KR102515455B1 (en) * | 2016-02-26 | 2023-03-30 | 에스케이하이닉스 주식회사 | Internal voltage generating circuit and system using the same |
Family Cites Families (12)
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DE2437713A1 (en) * | 1974-08-06 | 1976-02-26 | Bosch Gmbh Robert | DEVICE TO REDUCE HARMFUL COMPONENTS IN COMBUSTION ENGINE EXHAUST GAS |
US4709225A (en) | 1985-12-16 | 1987-11-24 | Crystal Semiconductor Corporation | Self-calibration method for capacitors in a monolithic integrated circuit |
JPH0827662B2 (en) * | 1987-06-12 | 1996-03-21 | 沖電気工業株式会社 | Comparison voltage generation circuit and voltage detection circuit using the same |
US5315547A (en) * | 1988-07-11 | 1994-05-24 | Hitachi, Ltd. | Nonvolatile semiconductor memory device with selective tow erasure |
US5168174A (en) | 1991-07-12 | 1992-12-01 | Texas Instruments Incorporated | Negative-voltage charge pump with feedback control |
US5258760A (en) * | 1992-07-13 | 1993-11-02 | Allegro Microsystems, Inc. | Digitally dual-programmable integrator circuit |
US5319370A (en) | 1992-08-31 | 1994-06-07 | Crystal Semiconductor, Inc. | Analog-to-digital converter with a continuously calibrated voltage reference |
JPH0721790A (en) | 1993-07-05 | 1995-01-24 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
US5497119A (en) * | 1994-06-01 | 1996-03-05 | Intel Corporation | High precision voltage regulation circuit for programming multilevel flash memory |
US5627784A (en) * | 1995-07-28 | 1997-05-06 | Micron Quantum Devices, Inc. | Memory system having non-volatile data storage structure for memory control parameters and method |
US5793249A (en) | 1996-09-30 | 1998-08-11 | Advanced Micro Devices, Inc. | System for providing tight program/erase speeds that are insensitive to process variations |
IT1302432B1 (en) | 1998-08-13 | 2000-09-05 | Texas Instruments Italia Spa | SECTOR BLOCKING SYSTEM WITH SECTORS OF MEMORY DEVICES AND SEMICONDUCTURE FLASH |
-
1999
- 1999-09-30 US US09/408,789 patent/US6448845B2/en not_active Expired - Fee Related
-
2000
- 2000-09-25 DE DE60045278T patent/DE60045278D1/en not_active Expired - Lifetime
- 2000-09-25 JP JP2001527291A patent/JP2003510756A/en not_active Withdrawn
- 2000-09-25 EP EP00967795A patent/EP1149383B1/en not_active Expired - Lifetime
- 2000-09-25 WO PCT/EP2000/009410 patent/WO2001024191A1/en active Application Filing
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9164933B2 (en) | 1999-10-19 | 2015-10-20 | Rambus Inc. | Memory system with calibrated data communication |
US10310999B2 (en) | 1999-10-19 | 2019-06-04 | Rambus Inc. | Flash memory controller with calibrated data communication |
US9785589B2 (en) | 1999-10-19 | 2017-10-10 | Rambus Inc. | Memory controller that calibrates a transmit timing offset |
US20140229667A1 (en) * | 1999-10-19 | 2014-08-14 | Rambus Inc. | Memory System with Calibrated Data Communication |
US8948212B2 (en) * | 1999-10-19 | 2015-02-03 | Rambus Inc. | Memory controller with circuitry to set memory device-specific reference voltages |
US9405678B2 (en) | 1999-10-19 | 2016-08-02 | Rambus Inc. | Flash memory controller with calibrated data communication |
US7031683B2 (en) * | 2001-01-12 | 2006-04-18 | Silicon Laboratories Inc. | Apparatus and methods for calibrating signal-processing circuitry |
US20020168952A1 (en) * | 2001-01-12 | 2002-11-14 | Vishakhadatta G. Diwakar | Apparatus and methods for calibrating signal-processing circuitry |
US7403441B2 (en) | 2004-02-20 | 2008-07-22 | Stmicroelectronics, S.R.L. | Power management unit for a flash memory with single regulation of multiple charge pumps |
US20060119383A1 (en) * | 2004-02-20 | 2006-06-08 | Enrico Castaldo | Power management unit for a flash memory with single regulation of multiple charge pumps |
EP1566723A1 (en) * | 2004-02-20 | 2005-08-24 | STMicroelectronics S.r.l. | A power management unit for a flash memory with single regulation of multiple charge pumps |
US20150042366A1 (en) * | 2009-10-30 | 2015-02-12 | Deka Products Limited Partnership | Apparatus and method for detecting disconnection of an intravascular access device |
US10201650B2 (en) * | 2009-10-30 | 2019-02-12 | Deka Products Limited Partnership | Apparatus and method for detecting disconnection of an intravascular access device |
US11197951B2 (en) | 2009-10-30 | 2021-12-14 | Deka Products Limited Partnership | Apparatus and method for detecting disconnection of an intravascular access device |
US11033671B2 (en) | 2011-05-24 | 2021-06-15 | Deka Products Limited Partnership | Systems and methods for detecting vascular access disconnection |
US20180268589A1 (en) * | 2017-03-16 | 2018-09-20 | Linden Research, Inc. | Virtual reality presentation of body postures of avatars |
US11145368B2 (en) * | 2020-01-06 | 2021-10-12 | Microchip Technology Incorporated | Method and system for reliable and secure memory erase |
Also Published As
Publication number | Publication date |
---|---|
US6448845B2 (en) | 2002-09-10 |
WO2001024191A1 (en) | 2001-04-05 |
EP1149383A1 (en) | 2001-10-31 |
EP1149383B1 (en) | 2010-11-24 |
DE60045278D1 (en) | 2011-01-05 |
JP2003510756A (en) | 2003-03-18 |
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